阅读说明：本技术 有条件退让给管理程序指令 (Conditional yield to hypervisor instructions ) 是由 W·J·迪肯 M·津吉尔 于 2020-01-07 设计创作，主要内容包括：本发明公开了一种装置,该装置包括处理电路(16),该处理电路具有用于执行管理程序的管理程序执行模式,以及比该管理程序执行模式权限更低的至少一个较低权限执行模式,该管理程序用于管理在处理电路上执行的一个或多个虚拟处理器。响应于在该至少一个较低权限执行模式下执行的有条件退让给管理程序指令,指令解码器(14)控制处理电路(16)来：确定是否满足至少一个陷阱条件,以及当确定满足该至少一个陷阱条件时,将处理电路切换为管理程序执行模式；以及将至少一项调度提示信息存储在该管理程序执行模式下执行的指令可访问的至少一个存储元件中,该至少一项调度提示信息用于估计是否仍然满足该至少一个陷阱条件。(An apparatus includes a processing circuit (16) having a hypervisor execution mode for executing a hypervisor for managing one or more virtual processors executing on the processing circuit, and at least one lower-privilege execution mode lower-privilege than the hypervisor execution mode. In response to a conditional yield to hypervisor instructions executing in the at least one lower-privilege execution mode, instruction decoder (14) controls processing circuitry (16) to: determining whether at least one trap condition is satisfied, and switching the processing circuitry to a hypervisor execution mode when it is determined that the at least one trap condition is satisfied; and storing at least one scheduling hint information in at least one storage element accessible to instructions executing in the hypervisor execution mode, the at least one scheduling hint information used to estimate whether the at least one trap condition is still satisfied.)

1. An apparatus, the apparatus comprising:

processing circuitry to perform data processing; and

an instruction decoder for decoding instructions to control the processing circuitry to perform the data processing; wherein:

the processing circuitry has a hypervisor execution mode for executing a hypervisor for managing one or more virtual processors executing on the processing circuitry, and at least one lower-privilege execution mode that is lower-privileged than the hypervisor execution mode;

In response to a conditional yield to hypervisor instructions executing in the at least one lower-privilege execution mode, the instruction decoder is configured to control the processing circuitry to:

determining whether at least one trap condition is satisfied, an

When it is determined that the at least one trap condition is satisfied:

switching the processing circuit to the hypervisor execution mode; and

storing at least one scheduling hint information in at least one storage element accessible to instructions executing in the hypervisor execution mode, the at least one scheduling hint information used to estimate whether the at least one trap condition is still satisfied.

2. The apparatus of claim 1, wherein the scheduling hint information comprises an indication of at least one register specifier specified by the conditional yield to hypervisor instruction.

3. The apparatus of claim 2, wherein the scheduling hint information comprises an indication of a register width of at least one register specified by the at least one register specifier.

4. The apparatus of any of claims 2 and 3, wherein the scheduling hint information comprises an indication of a plurality of register specifiers specified by the conditional yield to hypervisor instruction.

5. The apparatus of any preceding claim, wherein the conditional yield to hypervisor instruction comprises a wait for event instruction to instruct the processing circuitry to wait until one of a class of one or more events is indicated as having occurred; and is

The processing circuit is configured to determine that the at least one trap condition is not satisfied when one of the one or more events of the category is indicated as having occurred.

6. The apparatus of claim 5, the class of one or more events comprising detection of a memory access to a trace address tracked by a proprietary monitor.

7. The apparatus of claim 6, wherein the at least one scheduling hint information comprises a hint address corresponding to the trace address tracked by the dedicated monitor when executing the wait for event instruction.

8. The apparatus of claim 7, comprising address translation circuitry to translate a virtual address specified by an instruction executed by the processing circuitry to a physical address identifying a memory location corresponding to the virtual address based on first address translation data indicating a mapping between the virtual address and an intermediate address and second address translation data indicating a mapping between the intermediate address and the physical address;

Wherein the tracking address is a physical address and the hint address is the intermediate address corresponding to the tracking address.

9. The apparatus of claim 8, wherein the scheduling hint information comprises a valid indication that is set according to whether the intermediate address corresponding to the trace address is available when switching to the hypervisor execution mode.

10. The apparatus according to any of claims 6 to 9, wherein in response to a load-specific instruction specifying a target address, the instruction decoder is configured to control the processing circuitry to trigger the specific monitor to set the target address to the trace address.

11. The apparatus of claim 10, comprising address translation circuitry to translate a virtual address specified by an instruction executed by the processing circuitry to a physical address identifying a memory location corresponding to the virtual address based on first address translation data indicating a mapping between the virtual address and an intermediate address and second address translation data indicating a mapping between the intermediate address and the physical address;

The address translation circuitry comprises a combined translation cache memory comprising a plurality of cache entries each for storing a virtual to physical address mapping; and is

In response to the load-specific instruction, the address translation circuitry is configured to: triggering a lookup of the first address translation data to obtain the intermediate address corresponding to the target address of the load-specific instruction even when the combined translation cache memory already includes a cache entry storing the virtual-to-physical address mapping corresponding to the target address.

12. The apparatus according to any of claims 6 to 11, wherein the at least one scheduling hint information comprises a valid indication set according to whether the dedicated monitor is tracking any address that is the tracking address at the time the wait for event instruction is executed.

13. The apparatus of any preceding claim, comprising a hypervisor control register to store a trap control indicator indicating whether the conditional yield to hypervisor instruction should trap to the hypervisor; wherein:

In response to the conditional yield to a hypervisor instruction, the processing circuitry is configured to determine whether the at least one trap condition is satisfied in accordance with the trap control indicator.

14. The apparatus of any of claims 5 to 12, comprising a hypervisor control register to store a trap control indicator, the trap control indicator having one of a first value and a second value;

when the trap control indicator has the first value, the processing circuitry is configured to determine that the at least one trap condition is not satisfied regardless of whether one of the class of one or more events is indicated as having occurred; and is

When the trap control indicator has the second value, the processing circuitry is configured to determine that the at least one trap condition is satisfied when none of the one or more events of the class is indicated as having occurred.

15. A data processing method for an apparatus, the apparatus comprising: processing circuitry having a hypervisor execution mode for executing a hypervisor and at least one lower privilege execution mode lower privilege than the hypervisor execution mode privilege, the hypervisor to manage one or more virtual processors executing on the processing circuitry; the method comprises the following steps:

Decoding a conditional yield to hypervisor instruction executed in the at least one lower-privilege execution mode; and

in response to decoding the conditional yield to a hypervisor instruction:

determining whether at least one trap condition is satisfied, an

When it is determined that the at least one trap condition is satisfied:

switching the processing circuit to the hypervisor execution mode; and

storing at least one scheduling hint information in at least one storage element accessible to instructions executing in the hypervisor execution mode, the at least one scheduling hint information used to estimate whether the at least one trap condition is still satisfied.

16. A computer program for controlling a host data processing apparatus to provide an instruction execution environment for executing instructions; the computer program includes:

instruction decode program logic to decode instructions of object code for execution in the instruction execution environment to control the host data processing apparatus to perform data processing corresponding to the instructions of the object code, the instruction execution environment having a hypervisor execution mode to execute a hypervisor to manage one or more virtual processors executing in the instruction execution environment and at least one lower-privilege execution mode that is lower-privileged than the hypervisor execution mode; wherein:

In response to a conditional yield of the object code executing in the at least one lower-privilege execution mode to hypervisor instructions, the instruction decode program logic is configured to control the host data processing apparatus to:

determining whether at least one trap condition is satisfied, an

When it is determined that the at least one trap condition is satisfied:

switching the instruction execution environment to the hypervisor execution mode; and

storing at least one scheduling hint information in at least one data structure accessible to instructions of the object code executing in the hypervisor execution mode, the at least one scheduling hint information used to estimate whether the at least one trap condition is still satisfied.

17. A storage medium storing the computer program according to claim 16.