阅读说明：本技术 一种宽范围输入输出接口电路 (Wide-range input/output interface circuit ) 是由 陈雷 倪劼 李学武 孙华波 王文锋 郭琨 孙健爽 刘亚泽 赫彩 甄淑琦 张玉 于 2020-12-07 设计创作，主要内容包括：一种宽范围输入输出接口电路,属于集成电路领域；作为输出接口的情况下,利用辅助电压产生单元(103)的开启与关闭,通过双模式电平转换单元,使输出驱动单元(101)中PMOS晶体管栅源电压等于内核工作电源电压；作为输入接口的情况下,利用辅助电压产生单元(103)的开启与关闭,通过耐压输入缓冲器单元(104)和耐压输入缓冲器单元(105)的开启与关闭,使耐压输入缓冲器单元(104)中PMOS晶体管栅源电压等于输入输出接口电源电压。(A wide-range input/output interface circuit belongs to the field of integrated circuits; under the condition of being used as an output interface, the grid-source voltage of a PMOS (P-channel metal oxide semiconductor) transistor in the output driving unit (101) is enabled to be equal to the voltage of a kernel working power supply through the dual-mode level conversion unit by utilizing the on and off of the auxiliary voltage generation unit (103); in the case of an input interface, the gate-source voltage of a PMOS transistor in a withstand voltage input buffer unit (104) is made equal to the input-output interface power supply voltage by turning on and off a withstand voltage input buffer unit (104) and a withstand voltage input buffer unit (105) by turning on and off an auxiliary voltage generation unit (103).)

1. A wide-range input/output interface circuit is characterized by comprising an output driving unit (101), a dual-mode level conversion unit, an auxiliary voltage generation unit (103), and voltage-resistant input buffer units (104 and 105);

under the condition that the wide-range input/output interface circuit is used as an output interface, when the input/output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit (103) is started to generate an auxiliary voltage which is equal to the difference between the input/output interface power supply voltage and the kernel working power supply voltage, and the grid-source voltage of a PMOS (P-channel metal oxide semiconductor) transistor in the output driving unit (101) is equal to the kernel working power supply voltage through the dual-mode level conversion unit; when the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generation unit (103) is closed, and the grid-source voltage of the PMOS transistor in the output driving unit (101) is equal to the input/output interface power supply voltage through the dual-mode level conversion unit;

when the wide-range input/output interface circuit is used as an input interface, when the input/output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit (103) is started to generate an auxiliary voltage which is equal to the subtraction of the input/output interface power supply voltage and the kernel working power supply voltage, the voltage-resistant input buffer unit (104) is closed, and the voltage-resistant input buffer unit (105) is started to enable the grid-source voltage of a PMOS transistor in the voltage-resistant input buffer unit (105) to be equal to the kernel working power supply voltage; when the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generation unit (103) is closed, the voltage-resistant input buffer unit (104) is opened, and the voltage-resistant input buffer unit (105) is closed, so that the gate-source voltage of the PMOS transistor in the voltage-resistant input buffer unit (104) is equal to the input/output interface power supply voltage.

2. The wide-range input/output interface circuit of claim 1, wherein the output driving unit (101) comprises 4P-channel MOS transistors (P1, P2, P3, P4) and 3N-channel MOS transistors (N1, N2, N3),

the source of a P-channel MOS tube P1(207) and the source of a P-channel MOS tube P2(211) are connected with an input/output interface power supply VCCO, the gate of the P-channel MOS tube P1(207) and the gate of the P-channel MOS tube P2(211) are connected with an input port PG1(201) of the output drive unit (101), the drain of the P-channel MOS tube P1(207) and the drain of the P-channel MOS tube P2(211) are connected with an output port PIP (204) of the output drive unit (101), the source of the P-channel MOS tube P3(208) and the source of the P-channel MOS tube P4(212) are connected with the output port PIP (204) of the output drive unit (101), the gate of the P-channel MOS tube P3(208) and the gate of the P4(212) are connected with an input port PG2(202) of the output drive unit (101), the drain of the P-channel MOS tube P3(208) and the drain of the P PAD tube P4(212) are connected with a bidirectional drive port of the output drive unit (101), the drain of an N-channel MOS tube N1(209) is connected with a bidirectional port PAD (205) of an output driving unit (101), the gate of an N-channel MOS tube N1(209) is connected with a kernel working power supply VCCI, the source of an N-channel MOS tube N1(209) is connected with an output port PIN (206) of the output driving unit (101), the drain of an N-channel MOS tube N2(210) and the drain of an N-channel MOS tube N3(213) are connected with the output port PIN (206) of the output driving unit (101), the gate of an N-channel MOS tube N2(210) and the gate of an N-channel MOS tube N3(213) are connected with an input interface NG1(203) of the output driving unit (101), and the source of the N-channel MOS tube N2(210) and the source of an N3(213) are connected with the ground.

3. The wide-range input-output interface circuit according to claim 1, wherein the dual-mode level shift unit includes 8P-channel MOS transistors (P5, P6, P7, P8), 10N-channel MOS transistors (N8, N8), and 2 inverters (I8, I8), wherein the source of P-channel MOS transistor P8 (306) and the source of P-channel MOS transistor P8 (320) are connected to the input-output interface power supply VCCO, the gate of P-channel MOS transistor P8 (306) is connected to the drain of P-channel MOS transistor P8 (316) and the drain of N-channel transistor N8(317), the gate of P-channel MOS transistor P8 (320) is connected to the drain of P-channel MOS transistor P8 (307) and the drain of P-channel MOS transistor P8 (P8), and the drain of P-channel MOS transistor P8 (310) are connected to the drain of P-channel MOS transistor P8 (P8) and the drain of P-channel MOS transistor P8 (P8) are connected to the drain (P8, the, the grid of a P-channel MOS tube P7(307), the grid of a P-channel MOS tube P9(311), the grid of a P-channel MOS tube P10(316) and the grid of a P-channel MOS tube P8(321) are connected with the input port VA (301) of the dual-mode level shift unit, the drain of the P-channel MOS tube P7(307) is connected with the source of the P-channel MOS tube P9(311), the source of the P-channel MOS tube P11(308) and the grid of an N-channel MOS tube N4(309), the drain of the P-channel MOS tube P8(321), the source of the P-channel MOS tube P10(316), the source of the P-channel MOS tube P12(322) and the grid of the N-channel MOS tube N5(323) are connected with Z (304), the grid of the P-channel MOS tube P11(308) is connected with the source of the N-channel MOS tube N4(309) and the drain of the N6(310), the drain of the P-channel MOS tube P12 and the drain of the N-channel MOS tube N9 6 (324) are connected with the source of the N-channel MOS tube N, the drain of a P-channel MOS tube P11(308) is connected with the drain of an N-channel MOS tube N4(309), the drain of a P-channel MOS tube P12(302) is connected with the drain of an N-channel MOS tube N5(323), the gate of an N-channel MOS tube N6(310), the gate of an N-channel MOS tube N7(312), the gate of an N-channel MOS tube N8(317) and the gate of an N-channel MOS tube N9(324) are connected with a kernel operating power supply VCCI, the source of an N-channel MOS tube N6(310) is connected with the source of an N-channel MOS tube N10(313) and the drain of an N-channel MOS tube N12(314), the source of an N-channel MOS tube N9(324) is connected with the source of an N-channel MOS tube N11(318) and the drain of an N-channel MOS tube N13(319), the source of an N-channel MOS tube N7(312) is connected with the drain of an N10(313), the drain of an N-channel MOS tube N638 (313), the drain of an N638 (318) is connected with the drain of an N-channel MOS tube N638 input port of an N-channel MOS tube VS unit VS 302, and the, the output end of the inverter I3(305) is connected with the grid of an N-channel MOS tube N10(313) and the grid of an N-channel MOS tube N11(318), the input end of the inverter I4(315) and the grid of an N-channel MOS tube N12(314) are connected with the input end A (303) of the dual-mode level conversion unit, the output end of the inverter I4(315) is connected with the grid of an N-channel MOS tube N13(319), and the source of the N-channel MOS tube N12(314) and the source of the N-channel MOS tube N13(319) are connected with the ground.

4. The wide-range input/output interface circuit according to claim 1, wherein the auxiliary voltage generating unit (103) comprises 2P-channel MOS transistors (P13, P14), 2N-channel MOS transistors (N14, N15), 1 operational amplifier (X1), 2 resistors (R1, R2) and 1 alternative multiplexer (M3), a negative input terminal of the operational amplifier X1(404) is connected to the input port VREF (401), a positive input terminal of the operational amplifier X1(404) is connected to a drain of the P-channel MOS transistor P13(405) and a positive terminal of the resistor R1(407), an output terminal of the operational amplifier X1(404) is connected to a gate of the P-channel MOS transistor P13(405) and a gate of the P-channel MOS transistor P14(406), a source of the P-channel MOS transistor P13(405) and a source of the P14 MOS transistor P14 (VCCI), and a negative terminal of the resistor R1 (CI) is connected to the core operating power supply (VCCI), the drain of a P-channel MOS tube P14(406) is connected with the drain of an N-channel MOS tube N14(408), the gate of an N-channel MOS tube N14(408) and the gate of an N-channel MOS tube N15(409), the drain of an N-channel MOS tube N15(409) is connected with the negative terminal of a resistor R2(410) and the second input terminal A2(413) of an alternative multiplexer M3(411), the source of the N-channel MOS tube N15(409) is connected with the ground, the positive terminal of a resistor R2(410) is connected with an input/output interface power supply VCCO, the first input terminal A1(412) of the alternative multiplexer M3(411) is connected with the ground, the selection terminal S (414) of the alternative multiplexer M3(411) is connected with the input port VS (402), the output terminal Z (415) of the alternative multiplexer M3(411) is connected with the output terminal VA (403), the resistor R48 (407) is connected with the same resistance as the resistor R2, the N-channel MOS tube N2, the N-channel MOS tube N408 and the N-channel MOS tube N2, the width ratio of the P-channel MOS tube P13(405) to the P14(406) is the same as the ratio of the voltage of the input port VREF (401) to the voltage of the kernel operating power supply VCCI, the output end Z (415) of the alternative multiplexer M3(411) selects the output end A1(412) to output when the selection end S (414) is logic low, and the output end Z (415) of the alternative multiplexer M3(411) selects the output end A2(413) to output when the selection end S (414) is logic high.

5. The wide-range input/output interface circuit according to claim 1, wherein the voltage-tolerant input buffer (104) includes 3P-channel MOS transistors (P15, P16, P17), 1N-channel MOS transistor (N16) and 1 inverter (I5), the source of the P-channel MOS transistor P15(505) is connected to the input/output interface power VCCO, the gate of the P-channel MOS transistor P15(505) is connected to the input port VSb (501), the drain of the P-channel MOS transistor P15(505) is connected to the source of the P-channel MOS transistor P16(506), the gate of the P-channel MOS transistor P15(506) is connected to the input port VA (502), the source of the P-channel MOS transistor P15(506) is connected to the source of the P-channel MOS transistor P17(507), the gate of the P-channel MOS transistor P17(507) and the gate of the N-channel MOS transistor N16(508) are connected to the input port (503), the drain of the P-channel MOS transistor P17 and the drain of the N-channel MOS transistor P16 (36508) are connected to the input port N16, the source electrode of the N-channel MOS tube N16(508) is connected with the ground, and the output port of the inverter I5(509) is connected with the output port Z (504);

the voltage-resistant input buffer (105) comprises 8P-channel MOS transistors (P18, P19, P20, P21, P22, P23, P24, P25) and 7N-channel MOS transistors (N17, N18, N19, N20, N21), wherein the source of the P-channel MOS transistor P21 (606) and the source of the P-channel MOS transistor P21 (613) are connected with the input/output interface power VCCO, the gate of the P-channel MOS transistor P21 (606) and the gate of the P-channel MOS transistor P21 (613) are connected with the input port VSb (601), the drain of the P-channel MOS transistor P21 (606) is connected with the source of the P-channel MOS transistor P21 (607), the drain of the P-channel MOS transistor P21 (613) is connected with the source of the P-channel MOS transistor P21(614), the drain of the P21 (607) is connected with the source of the P-channel MOS transistor P21 (36616), the drain of the P-channel MOS transistor P21 (21) is connected with the source of the P36616), the P36616) and the drain of the P-channel MOS transistor P21 (21) is connected with the source of the P36616), the gates of a P-channel MOS tube P22(608) and a P-channel MOS tube P23(615) are connected to the input port VA (603), the drain of the P-channel MOS tube P22(608) is connected to the source of the P-channel MOS tube P24(608) and the gate of an N-channel MOS tube N17(610), the drain of the P-channel MOS tube P23(615) is connected to the source of the P-channel MOS tube P25(161) and the gate of the N-channel MOS tube N18(617), the gate of the P-channel MOS tube P24(609) is connected to the source of the N-channel MOS tube N17(610) and the drain of the N-channel MOS tube N19(611), the gate of the P-channel MOS tube P25(616) is connected to the source of the N-channel MOS tube N18(617), the drain of the N-channel MOS tube N20(618) and the drain of the N-channel MOS tube N632 (620), the drain of the P24(609) is connected to the drain of the N-channel MOS tube P638 (616), and the drain of the N-channel MOS tube N638 (616) is connected to the drain of the N-channel MOS tube N, the grid electrode of an N-channel MOS tube N19(611), the grid electrode of an N-channel MOS tube N20(618) and the grid electrode of an N-channel MOS tube N23(620) are connected with a kernel working power supply VCCI, the source electrode of the N-channel MOS tube N23(620) is connected with an output port Z (605), the source electrode of the N-channel MOS tube N19(611) is connected with the drain electrode of the N-channel MOS tube N21(612) and the grid electrode of the N-channel MOS tube N22(619), the grid electrode of the N-channel MOS tube N21(612) is connected with an input port PIN (604), the source electrode of the N-channel MOS tube N21(612) is connected with the ground, and the source electrode of the N22(619) is connected with the ground.

Technical Field

The invention relates to a wide-range input/output interface circuit, in particular to an input/output interface circuit which is optimally designed according to the application requirements of a programmable logic device and can adapt to various power supply voltages, belonging to the field of integrated circuits.

Background

The programmable logic device has the advantages of high flexibility, low cost, short period and the like, can greatly shorten the development period of products and maximally reduce risks, and becomes a core component in the integrated circuit industry. The programmable logic device comprises two power supplies, wherein one power supply is a kernel working power supply, the kernel working power supply works under a fixed power supply voltage for the whole circuit performance and power consumption, and the other power supply is an input/output interface power supply, has the communication function of the programmable logic device and other devices, and needs to be selected according to the voltage requirement of peripheral devices. In order to ensure direct connection with various peripheral devices, the input/output interface power supply of the programmable logic device needs to work in a wide voltage range, and the input/output interface power supply voltage may be higher than the core operating power supply voltage and may also be lower than the core operating power supply voltage. Therefore, a wide range of input/output interface circuits dedicated to programmable logic devices need to be designed to meet the requirements of various protocols and interface power supply voltages.

The traditional input/output interface circuit is designed aiming at specific power supply voltage, and has a structure that the power supply voltage of the input/output interface is higher than the core working voltage. The structure that the input/output interface power supply voltage is lower than the core working voltage is limited by the problems of the working voltage and the reliability of the transistor device, and the structure cannot work under the condition that the input/output interface power supply voltage is higher than the core working voltage. Therefore, a wide range of input/output interface circuits must be designed for the requirements of the programmable logic device for a variety of input/output interface supply voltages. Meanwhile, the condition that the power supply voltage of the input/output interface is higher than the core working voltage and the condition that the power supply voltage of the input/output interface is lower than or equal to the core working voltage are met, the data transmission speed during working under various power supply voltages is ensured, and the requirements of application of the programmable logic device are met.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the wide-range input/output interface circuit overcomes the defects of the prior art, provides the requirements for the programmable logic device to work under various power supply voltages, simultaneously meets the conditions that the input/output interface power supply voltage is higher than the kernel working voltage and the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, ensures the data transmission speed during working under various power supply voltages, and adapts to the requirements of the application of the programmable logic device.

The purpose of the invention is realized by the following technical scheme:

a wide-range input/output interface circuit includes an output drive unit (101), a dual-mode level shift unit, an auxiliary voltage generation unit (103), and withstand voltage input buffer units (104 and 105);

under the condition that the wide-range input/output interface circuit is used as an output interface, when the input/output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit (103) is started to generate an auxiliary voltage which is equal to the difference between the input/output interface power supply voltage and the kernel working power supply voltage, and the grid-source voltage of a PMOS (P-channel metal oxide semiconductor) transistor in the output driving unit (101) is equal to the kernel working power supply voltage through the dual-mode level conversion unit; when the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generation unit (103) is closed, and the grid-source voltage of the PMOS transistor in the output driving unit (101) is equal to the input/output interface power supply voltage through the dual-mode level conversion unit;

when the wide-range input/output interface circuit is used as an input interface, when the input/output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit (103) is started to generate an auxiliary voltage which is equal to the subtraction of the input/output interface power supply voltage and the kernel working power supply voltage, the voltage-resistant input buffer unit (104) is closed, and the voltage-resistant input buffer unit (105) is started to enable the grid-source voltage of a PMOS transistor in the voltage-resistant input buffer unit (105) to be equal to the kernel working power supply voltage; when the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generation unit (103) is closed, the voltage-resistant input buffer unit (104) is opened, and the voltage-resistant input buffer unit (105) is closed, so that the gate-source voltage of the PMOS transistor in the voltage-resistant input buffer unit (104) is equal to the input/output interface power supply voltage.

In the wide-range input/output interface circuit, the output driving unit (101) preferably includes 4P-channel MOS transistors (P1, P2, P3, P4) and 3N-channel MOS transistors (N1, N2, N3),

the source of a P-channel MOS tube P1(207) and the source of a P-channel MOS tube P2(211) are connected with an input/output interface power supply VCCO, the gate of the P-channel MOS tube P1(207) and the gate of the P-channel MOS tube P2(211) are connected with an input port PG1(201) of the output drive unit (101), the drain of the P-channel MOS tube P1(207) and the drain of the P-channel MOS tube P2(211) are connected with an output port PIP (204) of the output drive unit (101), the source of the P-channel MOS tube P3(208) and the source of the P-channel MOS tube P4(212) are connected with the output port PIP (204) of the output drive unit (101), the gate of the P-channel MOS tube P3(208) and the gate of the P4(212) are connected with an input port PG2(202) of the output drive unit (101), the drain of the P-channel MOS tube P3(208) and the drain of the P PAD tube P4(212) are connected with a bidirectional drive port of the output drive unit (101), the drain of an N-channel MOS tube N1(209) is connected with a bidirectional port PAD (205) of an output driving unit (101), the gate of an N-channel MOS tube N1(209) is connected with a kernel working power supply VCCI, the source of an N-channel MOS tube N1(209) is connected with an output port PIN (206) of the output driving unit (101), the drain of an N-channel MOS tube N2(210) and the drain of an N-channel MOS tube N3(213) are connected with the output port PIN (206) of the output driving unit (101), the gate of an N-channel MOS tube N2(210) and the gate of an N-channel MOS tube N3(213) are connected with an input interface NG1(203) of the output driving unit (101), and the source of the N-channel MOS tube N2(210) and the source of an N3(213) are connected with the ground.

In the wide-range input/output interface circuit, preferably, the dual-mode level shift unit includes 8P-channel MOS transistors (P5, P6, P7, P8), 10N-channel MOS transistors (N8, N8), and 2 inverters (I8, I8), a source of the P-channel MOS transistor P8 (306) and a source of the P-channel MOS transistor P8 (320) are connected to the input/output interface power VCCO, a gate of the P-channel MOS transistor P8 (306) is connected to a drain of the P-channel MOS transistor P8 (316) and a drain of the N-channel MOS transistor N8(317), a gate of the P-channel MOS transistor P8 (320) is connected to a drain of the P-channel MOS transistor P8 (P8) and a drain of the N-channel MOS transistor P8 (307), and a drain of the P8 (P8) is connected to a drain of the P8 (P8) and a drain of the P8 (307) and a drain of the P-channel MOS transistor P8 (P36320), the grid of a P-channel MOS tube P7(307), the grid of a P-channel MOS tube P9(311), the grid of a P-channel MOS tube P10(316) and the grid of a P-channel MOS tube P8(321) are connected with the input port VA (301) of the dual-mode level shift unit, the drain of the P-channel MOS tube P7(307) is connected with the source of the P-channel MOS tube P9(311), the source of the P-channel MOS tube P11(308) and the grid of an N-channel MOS tube N4(309), the drain of the P-channel MOS tube P8(321), the source of the P-channel MOS tube P10(316), the source of the P-channel MOS tube P12(322) and the grid of the N-channel MOS tube N5(323) are connected with Z (304), the grid of the P-channel MOS tube P11(308) is connected with the source of the N-channel MOS tube N4(309) and the drain of the N6(310), the drain of the P-channel MOS tube P12 and the drain of the N-channel MOS tube N9 6 (324) are connected with the source of the N-channel MOS tube N, the drain of a P-channel MOS tube P11(308) is connected with the drain of an N-channel MOS tube N4(309), the drain of a P-channel MOS tube P12(302) is connected with the drain of an N-channel MOS tube N5(323), the gate of an N-channel MOS tube N6(310), the gate of an N-channel MOS tube N7(312), the gate of an N-channel MOS tube N8(317) and the gate of an N-channel MOS tube N9(324) are connected with a kernel operating power supply VCCI, the source of an N-channel MOS tube N6(310) is connected with the source of an N-channel MOS tube N10(313) and the drain of an N-channel MOS tube N12(314), the source of an N-channel MOS tube N9(324) is connected with the source of an N-channel MOS tube N11(318) and the drain of an N-channel MOS tube N13(319), the source of an N-channel MOS tube N7(312) is connected with the drain of an N10(313), the drain of an N-channel MOS tube N638 (313), the drain of an N638 (318) is connected with the drain of an N-channel MOS tube N638 input port of an N-channel MOS tube VS unit VS 302, and the, the output end of the inverter I3(305) is connected with the grid of an N-channel MOS tube N10(313) and the grid of an N-channel MOS tube N11(318), the input end of the inverter I4(315) and the grid of an N-channel MOS tube N12(314) are connected with the input end A (303) of the dual-mode level conversion unit, the output end of the inverter I4(315) is connected with the grid of an N-channel MOS tube N13(319), and the source of the N-channel MOS tube N12(314) and the source of the N-channel MOS tube N13(319) are connected with the ground.

Preferably, the auxiliary voltage generating unit (103) includes 2P-channel MOS transistors (P13, P14), 2N-channel MOS transistors (N14, N15), 1 operational amplifier (X1), 2 resistors (R1, R2) and 1 alternative multiplexer (M3), a negative input terminal of the operational amplifier X1(404) is connected to the input port VREF (401), a positive input terminal of the operational amplifier X1(404) is connected to the drain of the P-channel MOS transistor P13(405) and the positive terminal of the resistor R1(407), an output terminal of the operational amplifier X1(404) is connected to the gate of the P-channel MOS transistor P13(405) and the gate of the P-channel MOS transistor P14(406), a source of the P-channel transistor P686405 and a source of the P-channel MOS transistor P406 (406) are connected to the core working power supply VCCI, the resistor R1(407) is connected to the negative terminal of the P-channel MOS transistor P14(406), and a drain of the N-channel MOS transistor P36408 (36408) is connected to the drain of the N-channel MOS transistor P14, The grid of an N-channel MOS tube N14(408) is connected with the grid of an N-channel MOS tube N15(409), the drain of the N-channel MOS tube N15(409) is connected with the negative end of a resistor R2(410) and the second input end A2(413) of an alternative multiplexer M3(411), the source of the N-channel MOS tube N15(409) is connected with the ground, the positive end of the resistor R2(410) is connected with an input-output interface power supply VCCO, the first input end A1(412) of the alternative multiplexer M3(411) is connected with the ground, the selection end S (414) of the alternative multiplexer M3(411) is connected with an input port VS (402), the output end Z (415) of the alternative multiplexer M3(411) is connected with an output port VA (403), the resistor R1(407) and the resistor R2(410) have the same resistance, the N-channel MOS tube N14(408) is connected with the grid of the N15, the N-channel MOS tube N15(409) and the inner core of the MOS tube N-channel MOS tube N15, the inner core of which has the same voltage, the same ratio, the voltage of the inner core of the inner Similarly, the output terminal Z (415) of the one-out multiplexer M3(411) selects the output terminal a1(412) to output when the select terminal S (414) is logic low, and the output terminal Z (415) of the one-out multiplexer M3(411) selects the output terminal a2(413) to output when the select terminal S (414) is logic high.

In the wide-range input/output interface circuit, preferably, the voltage-tolerant input buffer (104) includes 3P-channel MOS transistors (P15, P16, P17), 1N-channel MOS transistor (N16) and 1 inverter (I5), the source of the P-channel MOS transistor P15(505) is connected to the input/output interface power supply VCCO, the gate of the P-channel MOS transistor P15(505) is connected to the input port VSb (501), the drain of the P-channel MOS transistor P15(505) is connected to the source of the P-channel MOS transistor P16(506), the gate of the P-channel MOS transistor P15(506) is connected to the input port VA (502), the source of the P-channel MOS transistor P15(506) is connected to the source of the P-channel MOS transistor P17(507), the gate of the P-channel MOS transistor P17(507) and the gate of the N-channel MOS transistor N16(508) are connected to the input port (502), the drain of the P-channel MOS transistor P17 (P17) and the drain of the N-channel MOS transistor N39509 are connected to the input port (508), the source electrode of the N-channel MOS tube N16(508) is connected with the ground, and the output port of the inverter I5(509) is connected with the output port Z (504);

the voltage-resistant input buffer (105) comprises 8P-channel MOS transistors (P18, P19, P20, P21, P22, P23, P24, P25) and 7N-channel MOS transistors (N17, N18, N19, N20, N21), wherein the source of the P-channel MOS transistor P21 (606) and the source of the P-channel MOS transistor P21 (613) are connected with the input/output interface power VCCO, the gate of the P-channel MOS transistor P21 (606) and the gate of the P-channel MOS transistor P21 (613) are connected with the input port VSb (601), the drain of the P-channel MOS transistor P21 (606) is connected with the source of the P-channel MOS transistor P21 (607), the drain of the P-channel MOS transistor P21 (613) is connected with the source of the P-channel MOS transistor P21(614), the drain of the P21 (607) is connected with the source of the P-channel MOS transistor P21 (36616), the drain of the P-channel MOS transistor P21 (21) is connected with the source of the P36616), the P36616) and the drain of the P-channel MOS transistor P21 (21) is connected with the source of the P36616), the gates of a P-channel MOS tube P22(608) and a P-channel MOS tube P23(615) are connected to the input port VA (603), the drain of the P-channel MOS tube P22(608) is connected to the source of the P-channel MOS tube P24(608) and the gate of an N-channel MOS tube N17(610), the drain of the P-channel MOS tube P23(615) is connected to the source of the P-channel MOS tube P25(161) and the gate of the N-channel MOS tube N18(617), the gate of the P-channel MOS tube P24(609) is connected to the source of the N-channel MOS tube N17(610) and the drain of the N-channel MOS tube N19(611), the gate of the P-channel MOS tube P25(616) is connected to the source of the N-channel MOS tube N18(617), the drain of the N-channel MOS tube N20(618) and the drain of the N-channel MOS tube N632 (620), the drain of the P24(609) is connected to the drain of the N-channel MOS tube P638 (616), and the drain of the N-channel MOS tube N638 (616) is connected to the drain of the N-channel MOS tube N, the grid electrode of an N-channel MOS tube N19(611), the grid electrode of an N-channel MOS tube N20(618) and the grid electrode of an N-channel MOS tube N23(620) are connected with a kernel working power supply VCCI, the source electrode of the N-channel MOS tube N23(620) is connected with an output port Z (605), the source electrode of the N-channel MOS tube N19(611) is connected with the drain electrode of the N-channel MOS tube N21(612) and the grid electrode of the N-channel MOS tube N22(619), the grid electrode of the N-channel MOS tube N21(612) is connected with an input port PIN (604), the source electrode of the N-channel MOS tube N21(612) is connected with the ground, and the source electrode of the N22(619) is connected with the ground.

Compared with the prior art, the invention has the following beneficial effects:

(1) the invention can provide the capability of data output under various input and output interface power supply voltages by using the auxiliary voltage generating unit and the dual-mode level conversion unit, when the input and output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit is started to generate an auxiliary voltage which is equal to the subtraction of the input and output interface power supply voltage and the kernel working power supply voltage, the grid source voltage of the PMOS transistor in the output driving unit is equal to the kernel working power supply voltage by the dual-mode level conversion unit, thereby not only ensuring the reliability of the transistor, but also providing the maximum output driving capability, when the input and output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generating unit is closed, and the grid source voltage of the PMOS transistor in the output driving unit is equal to the input and output interface power, providing maximum output drive capability.

(2) The invention can provide the data input capability under various input and output interface power supply voltages by using an auxiliary voltage generating unit and two voltage-resistant input buffer units, when the input and output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit is started to generate an auxiliary voltage which is equal to the subtraction of the input and output interface power supply voltage and the kernel working power supply voltage, the first voltage-resistant input buffer unit is closed, the second voltage-resistant input buffer unit is started to ensure that the grid source voltage of a PMOS transistor in the second input buffer unit is equal to the kernel working power supply voltage, thereby ensuring the reliability of the transistor and providing the maximum conversion speed, when the input and output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generating unit is closed, the first voltage-resistant input buffer unit is started, the second voltage-resistant input buffer unit is closed, and making the grid-source voltage of the PMOS transistor in the first input buffer unit equal to the power supply voltage of the input/output interface, thereby providing the maximum conversion speed.

(3) The invention can adapt to the input and output interface of the programmable device under the requirements of various protocols by using the output driving unit; according to different protocols and requirements of driving capability, the programmable logic device can select the number of the output interface parallel transistors, and the design requirements of the programmable logic device can be met only by adjusting the number of the output driving units to match the number of the output parallel transistors without changing the design of the auxiliary voltage generating unit and the dual-mode level conversion unit.

(4) The auxiliary voltage generating unit is used for generating the auxiliary voltage of subtracting the kernel working power supply voltage from the input/output interface power supply voltage, so that the invention can adapt to various different input/output interface power supply voltage ranges, thereby providing the maximum output driving capability and input conversion speed.

(5) The invention generates an auxiliary voltage of subtracting the kernel working power supply voltage from the input/output interface power supply voltage by using the auxiliary voltage generating unit, can design a plurality of groups of input/output interface power supplies in the programmable logic device, and each group of input/output interface power supplies can share one auxiliary voltage generating unit, thereby improving the design efficiency of the programmable logic device.

(6) The invention selects the number of the output driving units according to the magnitude of the required driving current, and the configuration is flexible.

Drawings

FIG. 1 is a schematic diagram of a wide range input-output interface circuit of the present invention;

FIG. 2 is a circuit diagram of an output driving unit according to the present invention;

FIG. 3 is a circuit schematic of the dual mode level shifting unit of the present invention;

FIG. 4 is a circuit diagram of an auxiliary voltage generating unit according to the present invention;

FIG. 5 is a schematic circuit diagram of a first voltage tolerant input buffer cell of the present invention;

FIG. 6 is a circuit diagram of a second voltage-tolerant input buffer unit according to the present invention;

FIG. 7 is a waveform diagram of the I/O interface of the present invention when the power supply voltage is higher than the core power supply voltage;

FIG. 8 is a waveform diagram of the input/output interface of the present invention when the power supply voltage is lower than the core operating power supply voltage.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The technical scheme of the invention is as follows: a wide-range input/output interface circuit comprises an output driving unit, three dual-mode level conversion units, an auxiliary voltage generating unit, two voltage-resistant input buffers and two multiplexers. The combination of the auxiliary voltage generating unit and the dual-mode level converting unit meets the capability of data output under various input and output interface power supply voltages, when the input/output interface power supply voltage is higher than the core operating power supply voltage, the auxiliary voltage generating unit is turned on to generate an auxiliary voltage equal to the input/output interface power supply voltage minus the core operating power supply voltage, by the dual-mode level conversion unit, the grid-source voltage of the PMOS transistor in the output driving unit is equal to the kernel working power supply voltage, thereby ensuring the reliability of the transistor and providing the maximum output driving capability, when the power voltage of the input/output interface is lower than or equal to the power voltage of the kernel working power supply, the auxiliary voltage generating unit is closed, through the dual-mode level conversion unit, the grid-source voltage of the PMOS transistor of the output driving unit is equal to the power supply voltage of the input and output interface, and the maximum output driving capability is provided. When the input/output interface power supply voltage is higher than the kernel working power supply voltage, the auxiliary voltage generating unit is started to generate an auxiliary voltage which is equal to the subtraction of the input/output interface power supply voltage and the kernel working power supply voltage, the first voltage-resistant input buffer unit is closed, the second voltage-resistant input buffer unit is started to enable the grid source voltage of a PMOS transistor in the second input buffer unit to be equal to the kernel working power supply voltage, so that the transistor reliability is ensured and the maximum conversion speed is provided, when the input/output interface power supply voltage is lower than or equal to the kernel working power supply voltage, the auxiliary voltage generating unit is closed, the first voltage-resistant input buffer unit is opened, and the second voltage-resistant input buffer unit is closed, and making the grid-source voltage of the PMOS transistor in the first input buffer unit equal to the power supply voltage of the input/output interface, thereby providing the maximum conversion speed. Compared with the traditional input/output interface circuit, the invention can provide a larger input/output interface power supply voltage range, and can provide a faster data transmission speed under different input/output interface power supply voltages.

The invention is described in further detail below with reference to the figures and the specific embodiments,

a wide-range input-output interface circuit, as shown in fig. 1, including an output driving unit (101), three dual-mode level conversion units (102, 108, and 109), an auxiliary voltage generation unit (103), two voltage-tolerant input buffer units (104 and 105), two alternative multiplexers (106 and 107), an and gate (110), a nand gate (111), and two inverters (112 and 113);

an output driving unit (101), as shown in fig. 2, includes 4P-channel MOS transistors and 3N-channel MOS transistors, the source of the P-channel MOS transistor P1(207) and the source of the P-channel MOS transistor P2(211) are connected to the input/output interface power supply VCCO, the gate of the P-channel MOS transistor P1(207) and the gate of the P-channel MOS transistor P2(211) are connected to the input port PG1(201), the drain of the P-channel MOS transistor P1(207) and the drain of the P-channel MOS transistor P2(211) are connected to the output port PIP (204), the source of the P-channel MOS transistor P3(208) and the source of the P-channel MOS transistor P4(212) are connected to the output port PIP (204), the gate of the P-channel MOS transistor P3(208) and the gate of the P4(212) are connected to the input port PG2(202), the drain of the P-channel MOS transistor P3(208) and the drain of the P4 (P4) are connected to the bi-directional port PAD (205), the drain electrode of an N-channel MOS tube N1(209) is connected with a bidirectional port PAD (205), the grid electrode of an N-channel MOS tube N1(209) is connected with a kernel working power supply VCCI, the source electrode of an N-channel MOS tube N1(209) is connected with an output port PIN (206), the drain electrode of an N-channel MOS tube N2(210) and the drain electrode of an N-channel MOS tube N3(213) are connected with the output port PIN (206), the grid electrode of an N-channel MOS tube N2(210) and the grid electrode of an N-channel MOS tube N3(213) are connected with an input interface NG1(203), and the source electrode of the N-channel MOS tube N2(210) and the source electrode of an N-channel MOS tube N3(213) are connected with the ground;

the dual-mode level shift unit (102, 108 and 109), as shown in fig. 3, includes 8P-channel MOS transistors, 10N-channel MOS transistors and 2 inverters, the source of P-channel MOS transistor P5(306) and the source of P-channel MOS transistor P6(320) are connected to the input/output interface power supply VCCO, the gate of P-channel MOS transistor P5(306) is connected to the drain of P-channel MOS transistor P10(316) and the drain of N-channel MOS transistor N8(317), the gate of P-channel MOS transistor P6(320) is connected to the drain of P-channel MOS transistor P9(311) and the drain of N-channel MOS transistor N7(310), the drain of P-channel MOS transistor P5(306) is connected to the source of P-channel MOS transistor P7(307), the drain of P6(320) is connected to the source of P-channel MOS transistor P8(312), the gate of P7(307), the gate of P-channel MOS transistor P8545, P82311 is connected to the gate of P-channel MOS transistor P8536 (316) and the gate of P-channel MOS transistor VA (8), the drain of a P-channel MOS tube P7(307) is connected with the source of a P-channel MOS tube P9(311), the source of a P-channel MOS tube P11(308) and the gate of an N-channel MOS tube N4(309), the drain of a P-channel MOS tube P8(321), the source of a P-channel MOS tube P10(316), the source of a P-channel MOS tube P12(322) and the gate of an N-channel MOS tube N5(323) are connected with an output port Z (304), the gate of a P-channel MOS tube P11(308) is connected with the source of an N-channel MOS tube N4(309) and the drain of an N-channel MOS tube N6(310), the gate of a P-channel MOS tube P12(322) is connected with the source of an N-channel MOS tube N5(323) and the drain of an N-channel MOS tube N9(324), the drain of a P-channel MOS tube P11(308) is connected with the drain of an N-channel MOS tube N4(309), the drain of an N-channel MOS tube P638 (323) is connected with the drain of an N-channel MOS tube N12, and the drain of an N-channel MOS tube N-channel, The grid of an N-channel MOS tube N7(312), the grid of an N-channel MOS tube N8(317) and the grid of an N-channel MOS tube N9(324) are connected with a kernel working power supply VCCI, the source of the N-channel MOS tube N6(310) is connected with the source of an N-channel MOS tube N10(313) and the drain of an N-channel MOS tube N12(314), the source of the N-channel MOS tube N9(324) is connected with the source of an N-channel MOS tube N11(318) and the drain of an N-channel MOS tube N13(319), the source of the N-channel MOS tube N7(312) is connected with the drain of an N-channel MOS tube N10(313), the source of an N-channel MOS tube N8(317) is connected with the drain of an N-channel MOS tube N11(318), the input end of an inverter I3 (VS 305) is connected with an input port (302), the output end 3(305) of an N-channel MOS tube N10(313), the input end of an N-channel MOS tube N638 (315) is connected with the input end of an N638A and the input end of an N638 (303) of an N-channel MOS tube N638, the output end of the inverter I4(315) is connected with the gate of an N-channel MOS tube N13(319), and the source of the N-channel MOS tube N12(314) and the source of the N-channel MOS tube N13(319) are connected with the ground;

the auxiliary voltage generating unit (103), as shown in fig. 4, includes 2P-channel MOS transistors, 2N-channel MOS transistors, 1 operational amplifier, 2 resistors and 1 alternative multiplexer, the negative input terminal of the operational amplifier X1(404) is connected to the input port VREF (401), the positive input terminal of the operational amplifier X1(404) is connected to the drain of the P-channel MOS transistor P13(405) and the positive terminal of the resistor R1(407), the output terminal of the operational amplifier X1(404) is connected to the gate of the P-channel MOS transistor P13(405) and the gate of the P-channel MOS transistor P14(406), the source of the P-channel MOS transistor P13(405) and the source of the P-channel MOS transistor P14(406) are connected to the core operating power supply VCCI, the negative terminal of the resistor R1(407) is connected to ground, the drain of the P-channel MOS transistor P14(406) is connected to the drain of the N-channel MOS transistor N14(408), the drain of the N-channel MOS transistor N14(408) and the gate of the P-channel MOS transistor P15 (408), the drain of an N-channel MOS tube N15(409) is connected with the negative end of a resistor R2(410) and the second input end A2(413) of an alternative multiplexer M3(411), the source of the N-channel MOS tube N15(409) is connected with the ground, the positive end of a resistor R2(410) is connected with an input/output interface power supply VCCO, the first input end A1(412) of the alternative multiplexer M3(411) is connected with the ground, the selection end S (414) of the alternative multiplexer M3(411) is connected with an input port VS (402), the output end Z (415) of the alternative multiplexer M3(411) is connected with an output end VA (403), the resistance R1(407) is the same as the resistance value of the resistor R2(410), the widths of the N-channel MOS tube N14(408) and the N15(409) are the same, the widths of the P-channel MOS tube P13(405) and the P-channel MOS tube P14 are the same as the ratio of the voltage of the input port VCCO (406), the two-select multiplexer M3(411) selects the output from the input terminal a1(412) by the output terminal Z (415) when the select terminal S (414) is logic low, and the two-select multiplexer M3(411) selects the output from the input terminal a2(413) by the output terminal Z (415) when the select terminal S (414) is logic high;

a first voltage-tolerant input buffer (104), as shown in fig. 5, comprising 3P-channel MOS transistors, 1N-channel MOS transistor and 1 inverter, the source of the P-channel MOS transistor P15(505) is connected to the input/output interface power supply VCCO, the gate of the P-channel MOS transistor P15(505) is connected to the input port VSb (501), the drain of the P-channel MOS transistor P15(505) is connected to the source of the P-channel MOS transistor P16(506), the gate of the P-channel MOS transistor P15(506) is connected to the input port VA (502), the source of the P-channel MOS transistor P15(506) is connected to the source of the P-channel MOS transistor P17(507), the gate of the P-channel MOS transistor P17(507) and the gate of the N-channel MOS transistor N16(508) are connected to the input port PIN (503), the drain of the P-channel MOS transistor P17(507) and the drain of the N-channel MOS transistor N584 (508) are connected to the input port I5(509), and the source of the N-channel MOS transistor P16 (508) is connected to the input port, the output port of the inverter I5(509) is connected to the output port Z (504);

a second voltage-tolerant input buffer (105), as shown in fig. 6, includes 8P-channel MOS transistors and 7N-channel MOS transistors, the source of the P-channel MOS transistor P18(606) and the source of the P-channel MOS transistor P19(613) are connected to the input/output interface power supply VCCO, the gate of the P-channel MOS transistor P18(606) and the gate of the P-channel MOS transistor P19(613) are connected to the input port VSb (601), the drain of the P-channel MOS transistor P18(606) is connected to the source of the P-channel MOS transistor P20(607), the drain of the P-channel MOS transistor P19(613) is connected to the source of the P-channel MOS transistor P21(614), the gate of the P-channel MOS transistor P20(607) is connected to the input port (602), the drain of the P20(607) is connected to the source of the P-channel MOS transistor P22(608) and the gate of the P21(615), the drain of the P21(615) is connected to the P23, the gates of a P-channel MOS tube P22(608) and a P-channel MOS tube P23(615) are connected to the input port VA (603), the drain of the P-channel MOS tube P22(608) is connected to the source of the P-channel MOS tube P24(608) and the gate of an N-channel MOS tube N17(610), the drain of the P-channel MOS tube P23(615) is connected to the source of the P-channel MOS tube P25(161) and the gate of the N-channel MOS tube N18(617), the gate of the P-channel MOS tube P24(609) is connected to the source of the N-channel MOS tube N17(610) and the drain of the N-channel MOS tube N19(611), the gate of the P-channel MOS tube P25(616) is connected to the source of the N-channel MOS tube N18(617), the drain of the N-channel MOS tube N20(618) and the drain of the N-channel MOS tube N632 (620), the drain of the P24(609) is connected to the drain of the N-channel MOS tube P638 (616), and the drain of the N-channel MOS tube N638 (616) is connected to the drain of the N-channel MOS tube N, the grid electrode of an N-channel MOS tube N19(611), the grid electrode of an N-channel MOS tube N20(618) and the grid electrode of an N-channel MOS tube N23(620) are connected with a kernel working power supply VCCI, the source electrode of the N-channel MOS tube N23(620) is connected with an output port Z (605), the source electrode of the N-channel MOS tube N19(611) is connected with the drain electrode of the N-channel MOS tube N21(612) and the grid electrode of the N-channel MOS tube N22(619), the grid electrode of the N-channel MOS tube N21(612) is connected with an input port PIN (604), the source electrode of the N-channel MOS tube N21(612) is connected with the ground, and the source electrode of the N22(619) is connected with the ground.

The working mode of the wide-range input/output interface circuit designed by the invention is as follows: under the condition that the input/output interface power supply voltage is higher than the kernel working power supply voltage, the input port VS (118) is set to be at a high level, the auxiliary voltage generating unit (103) is started to generate an auxiliary voltage (VCCO-VCCI) which is equal to the difference between the input/output interface power supply voltage and the kernel working power supply voltage, the two-way multiplexer M1(106) selects the second input end A2(702) to output, the N-channel MOS tube N10(313) and the N-channel MOS tube N11(318) in the dual-mode level conversion units (102, 108 and 109) are closed, the P-channel MOS tube P5(306), the P-channel MOS tube P6(320), the P-channel MOS tube P7(307), the P-channel MOS tube P8(321), the P-channel MOS tube P9(311), the P-channel MOS tube P10(316), the P-channel MOS tube P11(308), the P-channel MOS tube P12(322), the N-channel MOS tube N4), N-channel MOS transistor N5(323), N-channel MOS transistor N6(310), N-channel MOS transistor N9(324), N-channel MOS transistor N12(314) and N-channel MOS transistor N13(319) work, when the wide-range input/output interface circuit outputs logic high, the input port PG1(201) and the input port PG2(202) of the output driving unit (101) are auxiliary voltage (VCCO-VCCI), the input port NG1(203) of the output driving unit (101) is ground voltage, the output voltage of the bidirectional port PAD (114) is input/output interface power Voltage (VCCO), when the wide-range input/output interface circuit outputs logic low, the input port PG1(201) of the output driving unit (101) is input/output power Voltage (VCCO), the input port PG2(202) of the output driving unit (101) is auxiliary voltage (VCCO-VCCI), the input port NG 4 (203) of the output driving unit (101) is core work power Voltage (VCCI), the output voltage of the bidirectional port PAD (114) is the ground voltage, when the wide-range input/output interface circuit inputs, the second voltage-resistant input buffer (105) is started, the first voltage-resistant input buffer (104) is closed, and the second-selection multiplexer M2(107) selects the output of the second input voltage-resistant buffer (105) to be output to the output port DI (119);

when the input/output interface power supply voltage is lower than or equal to the core operating power supply voltage, the input port VS (118) is set to a low level, the auxiliary voltage generation unit (103) is turned off to generate a ground voltage, the two-way multiplexer M1(106) selects the first input terminal a1(701) to output, the N-channel MOS transistor N10(313) and the N-channel MOS transistor N11(318) in the dual-mode level conversion unit (102, 108, and 109) are turned on, the P-channel MOS transistor P5(306), the P-channel MOS transistor P6(320), the P-channel MOS transistor P7(307), the P-channel MOS transistor P8(321), the P-channel MOS transistor P9(311), the P-channel MOS transistor P10(316), the N-channel MOS transistor N7(312), the N-channel MOS transistor N8(317), the N-channel MOS transistor N10(313), the N-channel MOS transistor N11(318), the N-channel MOS transistor N12), and the N-channel MOS transistor N13(319) in the dual-mode level conversion unit (102, 108, and 109), when the wide range input output interface circuit outputs a logic high, the input port PG1(201) and the input port PG2(202) of the output drive unit (101) are at ground voltage, the input port NG1(203) of the output drive unit (101) is at ground voltage, the bidirectional port PAD (114) output voltage is at input-output interface power supply Voltage (VCCO), when the wide range input-output interface circuit outputs a logic low, the input port PG1(201) of the output drive unit (101) is at input-output power supply Voltage (VCCO), the input port PG2(202) of the output drive unit (101) is at core operating power supply Voltage (VCCI), the input port NG1(203) of the output drive unit (101) is at core operating power supply Voltage (VCCI), the bidirectional port PAD (114) output voltage is at ground voltage, when the wide range input-output interface circuit outputs, the first withstand voltage input buffer (104) is turned on, the second voltage-tolerant input buffer 105 is turned off, and the output of the first voltage-tolerant buffer 104 is selected to the output port DI 119 by the alternative multiplexer M2 107.

FIG. 7 is a graph of the voltage waveforms of the wide range I/O interface circuit of the present invention when the I/O interface power supply voltage is higher than the core operating power supply voltage, where the first line is the voltage waveform of the input port DO (115), the second line is the voltage waveform of the bi-directional port PAD (114), the third line is the voltage waveform of the output port DI (119), where the core operating power supply voltage is 1.8V,

the power supply voltage of the input/output interface is 3.3V;

FIG. 8 is a voltage waveform of the wide-range I/O interface circuit of the present invention when the I/O interface power voltage is lower than the core power voltage, wherein the first line is the voltage waveform of the input port DO (115), the second line is the voltage waveform of the bi-directional port PAD (114), and the third line is the voltage waveform of the output port DI (119), wherein the core power voltage is 1.8V, and the I/O interface power voltage is 1.2V; the invention can reach the input and output power Voltage (VCCO) under the condition that the input and output interface power voltage is higher than the kernel working power voltage and under the condition that the input and output interface power voltage is lower than or equal to the kernel working power voltage, and meanwhile, the data transmission rate is kept consistent, thereby being capable of meeting the data transmission requirements under various power voltages.

Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.