阅读说明：本技术 一种基于dds的数字移相方法 (Digital phase shifting method based on DDS ) 是由 练小庆 于 2020-12-18 设计创作，主要内容包括：本发明实施例公开了一种基于DDS的数字移相方法,涉及相控阵雷达技术领域,能够任意调整所需相位并降低插损。本发明包括：FPGA(1)控制中频信号所用DDS(3)产生中频信号,和FPGA(1)控制本振信号所用DDS(4)产生本振信号；将所产生的中频信号和本振信号传输至混频器(5)；混频器(5)将输入的中频信号和本振信号进行变频处理,转换为待发送的射频信号之后向发射单元(6)传输,由发射单元(6)将射频信号放大后通过天线单元(7)向外发送。本发明适用于相控阵雷达的移相器。(The embodiment of the invention discloses a digital phase shifting method based on a DDS (direct digital synthesizer), which relates to the technical field of phased array radars and can be used for randomly adjusting required phases and reducing insertion loss. The invention comprises the following steps: the FPGA (1) controls a DDS (3) used by the intermediate frequency signal to generate the intermediate frequency signal, and the FPGA (1) controls a DDS (4) used by the local oscillator signal to generate the local oscillator signal; transmitting the generated intermediate frequency signal and the local oscillation signal to a mixer (5); the mixer (5) carries out frequency conversion processing on the input intermediate frequency signal and the local oscillator signal, converts the intermediate frequency signal and the local oscillator signal into a radio frequency signal to be transmitted, transmits the radio frequency signal to the transmitting unit (6), amplifies the radio frequency signal by the transmitting unit (6), and transmits the radio frequency signal to the outside through the antenna unit (7). The phase shifter is suitable for the phase shifter of the phased array radar.)

1. A digital phase shifting method based on DDS is characterized in that the method is used for a radar device, all antenna modules in the radar device are connected with a control console (8), and each antenna module at least comprises an FPGA (1), a reference clock (2), a DDS (3) for intermediate frequency signals, a DDS (4) for local oscillation signals, a mixer (5), a transmitting unit (6) and an antenna unit (7);

the FPGA (1) is respectively connected with a DDS (3) for intermediate frequency signals and a DDS (4) for local oscillation signals; the reference clock (2) is respectively connected with a DDS (3) used by the intermediate frequency signal and a DDS (4) used by the local oscillator signal; the mixer (5) is respectively connected with a DDS (3) for the intermediate frequency signal and a DDS (4) for the local oscillator signal; the mixer (5) is connected with the transmitting unit (6), and the transmitting unit (6) is connected with the antenna unit (7);

the method comprises the following steps:

the FPGA (1) controls a DDS (3) used by the intermediate frequency signal to generate the intermediate frequency signal, and the FPGA (1) controls a DDS (4) used by the local oscillator signal to generate the local oscillator signal;

transmitting the generated intermediate frequency signal and the local oscillation signal to a mixer (5);

the mixer (5) carries out frequency conversion processing on the input intermediate frequency signal and the local oscillator signal, converts the intermediate frequency signal and the local oscillator signal into a radio frequency signal to be transmitted, transmits the radio frequency signal to the transmitting unit (6), amplifies the radio frequency signal by the transmitting unit (6), and transmits the radio frequency signal to the outside through the antenna unit (7).

2. The method of claim 1, wherein the structure of the DDS comprises: a phase accumulator, an adder, a waveform memory (ROM), a D/A converter (D/AC), and a Low Pass Filter (LPF);

inputting a frequency control word into the phase accumulator, wherein the phase accumulator takes the frequency control word K as an accumulation at each rising edge of a reference clock fc, fc representing the frequency of the reference clock (2), and fc is simultaneously input into the phase accumulator and a D/a converter (D/AC);

inputting a phase control word into the adder, adding an N-bit binary code output by the adder and the phase control word P, taking the addition result as an address of a waveform memory (ROM), and triggering the waveform memory (ROM) to perform addressing processing, wherein N represents the word length of the phase accumulator;

the waveform memory (ROM) outputs sine amplitude S (n) of D bits, S (n) is converted into an analog signal S (t) through a D/A converter (DAC) and is input into a low-pass filter (LPF), wherein D represents the length of data in the waveform memory (ROM) and the word length of the D/A converter (DAC), and the length of the data in the waveform memory (ROM) and the word length of the D/A converter (DAC) are D bits;

a Low Pass Filter (LPF) smoothes s (t) to obtain a composite signal waveform.

3. The method of claim 2, further comprising:

the phase accumulator accumulates the frequency control word once on each rising clock edge when the phase accumulator is greater than 2^NThe accumulator overflows and begins counting again.

4. A method according to claim 2 or 3, characterized in that the sine amplitude is looked up from a waveform memory (ROM), wherein a sine lookup table is stored in the waveform memory (ROM), the value of the phase accumulator is added to the phase control word as an address in the sine lookup table, and the sine amplitude corresponding to the address in the sine lookup table is stored in the waveform memory (ROM);

the sine amplitude obtained by inquiry is processed by a D/A converter (D/AC) and a Low Pass Filter (LPF) in sequence, and a frequency signal f is output from the Low Pass Filter (LPF)_oWherein, in the step (A),

5. the method of claim 4, further comprising:

adjusting the Phase of the output signal by adjusting the value of the Phase control word P, wherein the Phase of the output signal is related to the Phase control word:

6. method according to claim 4, characterized in that the DDS (3) used for the intermediate frequency signal generates an intermediate frequency signal comprising:

DDS (3) used by the intermediate frequency signal generates linear frequency modulation;

and each clock is stepped according to the frequency of the linear frequency modulation in sequence, wherein the 1 st clock rising edge inputs the frequency control word corresponding to the basic frequency of the linear frequency modulation into the DDS (3) used by the intermediate frequency signal, the 2 nd clock rising edge inputs the frequency control word corresponding to the basic frequency of the linear frequency modulation after being stepped for +1 time into the DDS (3) used by the intermediate frequency signal, until the nth clock rising edge inputs the frequency control word corresponding to the basic frequency of the linear frequency modulation after being stepped for + n-1 time into the DDS (3) used by the intermediate frequency signal, and n is a serial number of the clock and is a positive integer.

7. The method of claim 6, wherein the generated chirp range includes 100MHz to 120MHz and a pulse width of 10us, the reference clock is set to 500MHz, and the clock period is 0.002us, a fundamental frequency of 100MHz, a frequency step of

The 1 st rising edge of the clock is used for controlling the frequency corresponding to 100MHzDDS (3) for inputting intermediate frequency signals;

the 5000 th rising edge of the clock generates a frequency control word corresponding to 120MHz DDS (3) for inputting the intermediate frequency signal.

8. The method of claim 4, wherein generating the local oscillator signal with the DDS (4) for the local oscillator signal comprises:

according to the value of the local oscillation signal required to be generated and the frequency of the reference clock, acquiring a frequency control word and inputting a DDS (4) for the local oscillation signal, wherein the frequency control word

9. The method of claim 4, wherein generating the local oscillator signal with the DDS (4) for the local oscillator signal comprises:

acquiring the phase of the output signal according to the phase value required to be adjusted and inputting the DDS (4) for the local oscillator signal, wherein the phase of the output signal

Technical Field

The invention relates to the technical field of phased array radars, in particular to a digital phase shifting method based on a DDS (direct digital synthesizer).

Background

In the phased array radar, the antenna pattern of the directional antenna is determined by the amplitude and the phase of the current on each unit, and meanwhile, the phased array antenna can change the phase of the current on each unit to realize electronic scanning, wherein, the phase shifter of the phased array is a core component.

Early on with analog phase shifters, the phase shift could be continuously adjusted, but the relationship between control current or voltage and phase was typically non-linear. Later digital phase shifters appeared with the phase values taking discrete values, usually binary steps, e.g. N-bit phase shifters covering 360 ° phase change in 2N steps. In some phased array radars, a 5-bit phase shifter is typically used, with a phase increment of 11.25 °. And the digital phase shifter of practical use is based on diode phase shifter principle, and its phase accuracy requires more, and the more that adopts also, leads to its insertion loss also great, often has 5 ~ 10 dB. In order to achieve both insertion loss and phase accuracy, the number of bits in a typical digital phase shifter is up to 6 bits, i.e., 5.625 ° in accuracy.

Therefore, how to further improve the accuracy and reduce the insertion loss on the basis of the digital phase shifter becomes a future development direction of the digital phase shifting scheme.

Disclosure of Invention

The embodiment of the invention provides a digital phase shifting method based on DDS, which can arbitrarily adjust the required phase and reduce the insertion loss.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

specifically, the method is used for a radar device, in the radar device, all antenna modules are connected with a console (8), and each antenna module at least comprises an FPGA (1), a reference clock (2), a DDS (3) for an intermediate frequency signal, a DDS (4) for a local oscillator signal, a mixer (5), a transmitting unit (6) and an antenna unit (7); the FPGA (1) is respectively connected with a DDS (3) for intermediate frequency signals and a DDS (4) for local oscillation signals; the reference clock (2) is respectively connected with a DDS (3) used by the intermediate frequency signal and a DDS (4) used by the local oscillator signal; the mixer (5) is respectively connected with a DDS (3) for the intermediate frequency signal and a DDS (4) for the local oscillator signal; the mixer (5) is connected with the transmitting unit (6), and the transmitting unit (6) is connected with the antenna unit (7);

the method comprises the following steps: the FPGA (1) controls a DDS (3) used by the intermediate frequency signal to generate the intermediate frequency signal, and the FPGA (1) controls a DDS (4) used by the local oscillator signal to generate the local oscillator signal; transmitting the generated intermediate frequency signal and the local oscillation signal to a mixer (5); the mixer (5) carries out frequency conversion processing on the input intermediate frequency signal and the local oscillator signal, converts the intermediate frequency signal and the local oscillator signal into a radio frequency signal to be transmitted, transmits the radio frequency signal to the transmitting unit (6), amplifies the radio frequency signal by the transmitting unit (6), and transmits the radio frequency signal to the outside through the antenna unit (7).

The original phase shift is adjusted by a digital phase shifter in the transmit unit after the mixer output and before the radiating unit. The digital phase shifting method based on the DDS provided by the embodiment of the invention removes the digital phase shifter on the receiving and sending unit, and shifts the phase by adjusting the phase of the intermediate frequency signal before mixing or the phase of the local oscillation signal of the mixer. Both the intermediate frequency signal and the local oscillator signal can be generated by a DDS technique, which generally consists of a phase accumulator, an adder, a waveform memory (ROM), a D/a converter, and a low pass filter. Where K is the frequency control word, P is the phase control word, fc is the reference clock frequency, N is the word length of the phase accumulator, and D is the word length of the ROM data and D/a converter. The phase accumulator accumulates by step length K under the control of clock fc, the output N bit binary code is added with phase control word P and used as the address of waveform ROM, the waveform ROM is addressed, the amplitude code S (N) of the output D bit of the waveform ROM is converted into analog signal S (t) by D/A converter, and the analog signal S (t) is smoothed by low-pass filter to obtain the synthesized signal waveform. On each clock edge, the accumulator is accumulated once with the frequency control word K, when the accumulator is greater than 2^NIn time, the accumulator is equivalent to performing modulo operation once. And in each clock cycle, the sine lookup table ROM sends the data obtained by adding the value of the accumulator and the phase control word to an address of the ROM, takes out the sine amplitude value which is stored in the ROM and corresponds to the address, and finally sends the value to the DAC and the low-pass filter to realize the conversion from the quantized amplitude value to the sine signal. From this, it can be obtained that the relationship between the output frequency and the clock frequency isThe phase of the output frequency is related to the phase control wordThe phase of the output signal can be adjusted by simply adjusting the value of the phase control word P. The mixer converts the frequency of the input intermediate frequency signal and the local oscillator signal and sends the converted signals to the transceiving unit, and the phase of the mixer has linear characteristic during mixing, so that the mixer has the advantages of low cost and high efficiencyThe phase control word in the DDS used for generating the input intermediate frequency signal or the local oscillator signal is adjusted, so that the phase of the signal after frequency conversion can be adjusted. For a DDS system with N phase accumulator bits, the phase precision is 360 DEG/2^NThe accumulator bit of the DDS is high and can reach 32 bits or 48 bits, so that the phase precision is far less than 0.1 degree, and the required phase can be adjusted freely. And the phase adjustment at this time has no influence on the power of the DAC output signal, so that no signal loss is brought. Therefore, the required phase can be adjusted at will, and the accuracy of phase adjustment is improved. And the adjustment phase has no influence on the power of the D/AC output signal at the moment, and the signal loss is almost zero theoretically.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block diagram of an embodiment of the present invention;

fig. 2 is a schematic diagram of a DDS circuit provided in an embodiment of the invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention. As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or coupled. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The original phase shift is adjusted by a digital phase shifter in the transmit unit before the antenna unit after the mixer output. The design idea of the invention is to remove the digital phase shifter on the transceiving unit and shift the phase by adjusting the phase of the intermediate frequency signal before mixing or the phase of the local oscillation signal of the mixer.

In the digital phase shifting method based on the DDS provided in the embodiment of the present invention, as shown in fig. 1, the method is applied to a radar apparatus, in the radar apparatus, all antenna modules are connected to a console (8), and each antenna module at least includes an FPGA (1), a reference clock (2), a DDS (3) for an intermediate frequency signal, a DDS (4) for a local oscillation signal, a mixer (5), a transmitting unit (6), and an antenna unit (7).

The FPGA (1) is respectively connected with a DDS (3) for intermediate frequency signals and a DDS (4) for local oscillation signals. The reference clock (2) is respectively connected with a DDS (3) used by the intermediate frequency signal and a DDS (4) used by the local oscillator signal. The mixer (5) is respectively connected with a DDS (3) for the intermediate frequency signal and a DDS (4) for the local oscillator signal. The mixer (5) is connected with the transmitting unit (6), and the transmitting unit (6) is connected with the antenna unit (7).

The method comprises the following steps:

s1, the FPGA (1) controls the DDS (3) used by the intermediate frequency signal to generate the intermediate frequency signal, and the FPGA (1) controls the DDS (4) used by the local oscillation signal to generate the local oscillation signal.

And S2, transmitting the generated intermediate frequency signal and the local oscillation signal to a mixer (5).

S3, the mixer (5) carries out frequency conversion processing on the input intermediate frequency signal and the local oscillator signal, converts the intermediate frequency signal and the local oscillator signal into a radio frequency signal to be transmitted, transmits the radio frequency signal to the transmitting unit (6), and the transmitting unit (6) amplifies the radio frequency signal and then transmits the radio frequency signal to the outside through the antenna unit (7).

The phase of the mixer has linear characteristics during mixing, so that the phase of the frequency-converted signal can be adjusted by adjusting a phase control word in a DDS (direct digital synthesizer) used for generating an input intermediate frequency signal or a local oscillator signal. And the intermediate frequency signal and the local oscillator signal can be generated by the DDS technique. For example: for a DDS system with N phase accumulator bits, the phase precision is 360 DEG/2^NThe accumulator bit of the DDS is high and can reach 32 bits or 48 bits, so that the phase precision is far less than 0.1 degree, and the required phase can be adjusted freely. And the adjustment phase has no influence on the power of the D/AC output signal at the moment, and the signal loss is almost zero theoretically.

As shown in particular in fig. 2, a frequency control word is input to the phase accumulator. The phase control word is input to the adder, and the N-bit binary code output by the adder is added to the phase control word P, and then the addition result is used as the address of a waveform memory (ROM) and triggers the waveform memory (ROM) to perform addressing processing. Wherein the phase accumulator takes the frequency control word K as an accumulation at each rising edge of a reference clock fc, fc representing the frequency of the reference clock (2), and fc is input to both the phase accumulator and the D/a converter (D/AC). Specifically, the structure of the DDS includes: phase accumulators, adders, waveform memory (ROM), D/A converters (D/AC), and Low Pass Filters (LPF). N represents the word length of the phase accumulator.

The waveform memory (ROM) outputs the sine amplitude S (n) of D bit, S (n) is converted into analog signal S (t) by D/A converter (DAC) and input to Low Pass Filter (LPF). Where D denotes the length of data in the waveform memory (ROM) and the word length of the D/a converter (DAC), and both the length of data in the waveform memory (ROM) and the word length of the D/a converter (DAC) are D bits.

A Low Pass Filter (LPF) smoothes s (t) to obtain a composite signal waveform. Wherein the phase accumulator accumulates the frequency control word once per clock rising edge when the phase accumulator is greater than 2^NThe accumulator overflows and begins counting again.

Further, the sinusoidal amplitude needs to be looked up from a waveform memory (ROM). The sine amplitude obtained by inquiry is processed by a D/A converter (D/AC) and a Low Pass Filter (LPF) in sequence, and a frequency signal f is output from the Low Pass Filter (LPF)_oWherein, in the step (A),wherein the sine lookup table is stored in a waveform memory (ROM), data obtained by adding a value of the phase accumulator to a phase control word is used as an address in the sine lookup table, and a sine amplitude value corresponding to the address in the sine lookup table is stored in the waveform memory (ROM). For example:

the word length N of the phase accumulator is only 4 bits, 2^4 ^ 16 address states, namely 0000, 0001, 0010..1101, 1110 and 1111, and the sine amplitude value stored in each address sequentially corresponds to 0, 0.383, 0.707, 0.924, 1, 0.924, 0.707, 0.383, 0, -0.383, -0.707, -0.924, -1, -0.924, -0.707 and-0.383; when the frequency control word is set to 0010 and the phase control word is set to 0001, the initial value is 0010+ 0001-0011, and the address corresponds to a sine amplitude of 0.924; after the first frequency control word is accumulated, 0011+0010 is 0101, the sine amplitude value corresponding to the address is 0.924, after the second frequency control word is accumulated, 0100+0010 is 0111, the sine amplitude value corresponding to the address is 0.383, the steps are carried out subsequently, when the accumulated value reaches 1110, the next accumulation is 1110+0010 is 0000, the accumulated value overflows, and the process of repeated and continuous accumulation is carried out.

Further, the method also comprises the following steps: adjusting the Phase of the output signal by adjusting the value of the Phase control word P, wherein the Phase of the output signal is related to the Phase control word:

in this embodiment, the DDS (3) for the intermediate frequency signal generates the intermediate frequency signal, which includes:

DDS (3) used for the intermediate frequency signal generates linear frequency modulation. Each clock is stepped in turn according to the frequency of the chirp.

The 1 st clock rising edge inputs a frequency control word corresponding to the basic frequency of the linear frequency modulation into a DDS (3) used by the intermediate frequency signal, the 2 nd clock rising edge inputs a frequency control word corresponding to the basic frequency of the linear frequency modulation after being stepped for +1 times into the DDS (3) used by the intermediate frequency signal, until the nth clock rising edge inputs the frequency control word corresponding to the basic frequency of the linear frequency modulation after being stepped for + n-1 times into the DDS (3) used by the intermediate frequency signal, and n is a sequential number of the clock and is a positive integer.

The generated linear frequency modulation range comprises 100MHz to 120MHz and the pulse width is 10us, a set reference clock is 500MHz, the clock period is 0.002us, the basic frequency is 100MHz, and the frequency is steppedThe 1 st rising edge of the clock is used for controlling the frequency corresponding to 100MHzDDS (3) for inputting the intermediate frequency signal. The 5000 th rising edge of the clock generates a frequency control word corresponding to 120MHzDDS (3) for inputting the intermediate frequency signal. For example:

the frequency of each clock is stepped toThe 1 st rising edge of the clock is used for controlling the frequency corresponding to 100MHzFeeding the DDS; the 2 nd rising edge of the clock is used for controlling the frequency of 100.004MHz corresponding frequency control wordFeeding a frequency control word corresponding to 104MHz on the 1000 th clock rising edgeFeeding a frequency control word corresponding to 120MHz at the rising edge of the 5000 th clock The DDS is fed in.

The DDS (4) used by the local oscillator signal generates the local oscillator signal, which comprises the following steps: according to the value of the local oscillation signal required to be generated and the frequency of the reference clock, acquiring a frequency control word and inputting a DDS (4) for the local oscillation signal, wherein the frequency control wordThe DDS (4) used by the local oscillator signal generates the local oscillator signal, which comprises the following steps: acquiring the phase of the output signal according to the phase value required to be adjusted and inputting the DDS (4) for the local oscillator signal, wherein the phase of the output signalThe local frequency generally generates dot frequency, such as 2500MHz, 6000MHz reference clock, and frequency control wordFeeding DDS, when phase 11 is to be adjusted^°When in use, willThe DDS is fed in.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points. The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.