阅读说明：本技术 一种雷达感应组件 (Radar response subassembly ) 是由 徐乃昊 于 2020-11-27 设计创作，主要内容包括：本公开实施例中提供了一种雷达感应组件,属于信号处理技术领域,具体包括降幅模组,所述降幅模组的输入端与市电接口电连接,所述降幅模组针对所述市电接口输出的市电信号进行降幅处理,得到并输出降幅后的基准信号；雷达传感器,包括时钟电路、发射电路和接收电路；所述时钟电路的输入端与所述降幅模组的输出端电连接,用于接收所述基准信号并基于所述基准信号提供时钟信号,所述时钟信号的频率为工频的整数倍；所述发射电路用于发射射频信号；所述接收电路接收反射后的射频信号,并基于所述时钟信号对所述反射后的射频信号进行处理得到感应结果。通过本公开的处理方案,提高了雷达传感器的时钟精度。(The embodiment of the disclosure provides a radar sensing assembly, which belongs to the technical field of signal processing, and specifically comprises an amplitude reduction module, wherein the input end of the amplitude reduction module is electrically connected with a mains supply interface, and the amplitude reduction module performs amplitude reduction processing on a mains supply signal output by the mains supply interface to obtain and output an amplitude-reduced reference signal; the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit; the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integral multiple of the power frequency; the transmitting circuit is used for transmitting radio frequency signals; and the receiving circuit receives the reflected radio frequency signal and processes the reflected radio frequency signal based on the clock signal to obtain a sensing result. Through the processing scheme disclosed by the invention, the clock precision of the radar sensor is improved.)

1. A radar sensing assembly, comprising:

the amplitude reduction module is electrically connected with the mains supply interface at the input end and is used for carrying out amplitude reduction processing on a mains supply signal output by the mains supply interface to obtain and output an amplitude-reduced reference signal;

the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit;

the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integral multiple of the power frequency;

the transmitting circuit is used for transmitting radio frequency signals;

and the receiving circuit receives the reflected radio frequency signal and processes the reflected radio frequency signal based on the clock signal to obtain a sensing result.

2. The radar sensing assembly of claim 1, wherein the droop module comprises a voltage divider circuit, an input terminal of the voltage divider circuit is electrically connected to the utility power interface, and an output terminal of the voltage divider circuit is electrically connected to an input terminal of the clock circuit.

3. The radar sensing assembly of claim 2, wherein the voltage divider circuit comprises a first impedance and a second impedance, a first end of the first impedance is electrically connected to the utility power interface, a second end of the first impedance is electrically connected to a first end of the second impedance, a second end of the second impedance is electrically connected to ground, and a first end of the second impedance is electrically connected to the input terminal of the clock circuit.

4. The radar sensing assembly of claim 1, wherein the reference signal is a sine wave signal; the clock circuit comprises a sine wave to square wave circuit and a frequency multiplier circuit;

the input end of the sine wave to square wave conversion circuit is electrically connected with the output end of the amplitude reduction module, and the sine wave to square wave conversion circuit receives the reference signal and converts the reference signal into a square wave signal;

the input end of the frequency doubling circuit is electrically connected with the output end of the sine wave to square wave circuit, and the frequency doubling circuit receives the square wave signal and converts the square wave signal into the clock signal.

5. The radar sensing assembly of claim 1, wherein the receive circuit comprises a radio frequency receiver, a modulation circuit, and a timing analysis circuit;

the radio frequency receiver receives and outputs the reflected radio frequency signal;

the input end of the modulation circuit is electrically connected with the output end of the radio frequency receiver, and the modulation circuit converts the reflected radio frequency signal to obtain a zero intermediate frequency signal;

the input end of the time sequence analysis circuit is electrically connected with the output end of the modulation circuit, the clock end of the time sequence analysis circuit is electrically connected with the output end of the clock circuit, and the time sequence analysis circuit obtains an induction result based on the zero intermediate frequency signal and the clock signal.

6. The radar sensing assembly of claim 5, wherein the timing analysis circuit is a digital circuit; the receiving circuit further comprises an analog-to-digital conversion circuit, a clock end of the analog-to-digital conversion circuit is electrically connected with an output end of the clock circuit, an input end of the analog-to-digital conversion circuit is electrically connected with an output end of the modulation circuit, and an output end of the analog-to-digital conversion circuit is electrically connected with an input end of the time sequence analysis circuit.

7. The radar sensing assembly of claim 5, wherein the receive circuit further comprises a filter circuit;

the input end of the filter circuit is electrically connected with the output end of the modulation circuit, and the filter circuit filters power frequency and frequency multiplication thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;

the input end of the time sequence analysis circuit is electrically connected with the output end of the filter circuit, and the time sequence analysis circuit obtains an induction result based on the signal to be analyzed and the clock signal.

8. The radar sensing assembly of claim 7, wherein the filtering circuit includes a comb down-sampling filter;

the input end of the dressing down-sampling filter is electrically connected with the output end of the modulation circuit, and the output end of the dressing down-sampling filter is electrically connected with the input end of the time sequence analysis circuit.

9. The radar sensing assembly of claim 8, wherein the filter circuit further comprises a digital trap;

the input end of the digital wave trap is electrically connected with the output end of the dressing down-sampling filter, and the output end of the digital wave trap is electrically connected with the input end of the time sequence analysis circuit.

10. The radar sensing assembly of claim 5, wherein the modulation circuit comprises a mixer, an input of the mixer being electrically coupled to an output of the radio frequency receiver, an output of the mixer being electrically coupled to an input of the timing analysis circuit.

Technical Field

The present disclosure relates to the field of signal processing technologies, and in particular, to a radar sensing assembly.

Background

With the continuous development of science and technology and the continuous promotion of economic level, radar sensor not only is applied to military application, also begins to be applied to a plurality of daily fields such as automotive electronics, security protection, unmanned aerial vehicle, intelligent transportation.

In the related art, there is a problem that the clock accuracy of the radar sensor is low due to the influence of process variations and temperature variations.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a radar sensing assembly that at least partially solves the problems in the prior art.

In a first aspect, an embodiment of the present disclosure provides a radar sensing assembly, including:

the amplitude reduction module is electrically connected with the mains supply interface at the input end and is used for carrying out amplitude reduction processing on a mains supply signal output by the mains supply interface to obtain and output an amplitude-reduced reference signal;

the radar sensor comprises a clock circuit, a transmitting circuit and a receiving circuit;

the input end of the clock circuit is electrically connected with the output end of the amplitude reduction module and is used for receiving the reference signal and providing a clock signal based on the reference signal, and the frequency of the clock signal is an integral multiple of the power frequency;

the transmitting circuit is used for transmitting radio frequency signals;

and the receiving circuit receives the reflected radio frequency signal and processes the reflected radio frequency signal based on the clock signal to obtain a sensing result.

According to a specific implementation manner of the embodiment of the present disclosure, the amplitude reduction module includes a voltage division circuit, an input end of the voltage division circuit is electrically connected to the commercial power interface, and an output end of the voltage division circuit is electrically connected to an input end of the clock circuit.

According to a specific implementation manner of the embodiment of the present disclosure, the voltage dividing circuit includes a first impedance and a second impedance, a first end of the first impedance is electrically connected to the utility power interface, a second end of the first impedance is electrically connected to a first end of the second impedance, a second end of the second impedance is electrically connected to a ground terminal, and a first end of the second impedance is electrically connected to an input terminal of the clock circuit.

According to a specific implementation manner of the embodiment of the present disclosure, the reference signal is a sine wave signal; the clock circuit comprises a sine wave to square wave circuit and a frequency multiplier circuit;

the input end of the sine wave to square wave conversion circuit is electrically connected with the output end of the amplitude reduction module, and the sine wave to square wave conversion circuit receives the reference signal and converts the reference signal into a square wave signal;

the input end of the frequency doubling circuit is electrically connected with the output end of the sine wave to square wave circuit, and the frequency doubling circuit receives the square wave signal and converts the square wave signal into the clock signal.

According to a specific implementation manner of the embodiment of the present disclosure, the receiving circuit includes a radio frequency receiver, a modulation circuit, and a timing analysis circuit;

the radio frequency receiver receives and outputs the reflected radio frequency signal;

the input end of the modulation circuit is electrically connected with the output end of the radio frequency receiver, and the modulation circuit converts the reflected radio frequency signal to obtain a zero intermediate frequency signal;

the input end of the time sequence analysis circuit is electrically connected with the output end of the modulation circuit, the clock end of the time sequence analysis circuit is electrically connected with the clock circuit, and the time sequence analysis circuit obtains an induction result based on the zero intermediate frequency signal and the clock signal.

According to a specific implementation manner of the embodiment of the disclosure, the timing sequence analysis circuit is a digital circuit; the receiving circuit further comprises an analog-to-digital conversion circuit, a clock end of the analog-to-digital conversion circuit is electrically connected with the clock circuit, an input end of the analog-to-digital conversion circuit is electrically connected with an output end of the modulation circuit, and an output end of the analog-to-digital conversion circuit is electrically connected with an input end of the time sequence analysis circuit.

According to a specific implementation manner of the embodiment of the present disclosure, the receiving circuit further includes a filter circuit;

the input end of the filter circuit is electrically connected with the output end of the modulation circuit, and the filter circuit filters power frequency and frequency multiplication thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;

the input end of the time sequence analysis circuit is electrically connected with the output end of the filter circuit, and the time sequence analysis circuit obtains an induction result based on the signal to be analyzed and the clock signal.

According to a specific implementation of the disclosed embodiment, the filter circuit includes a comb down-sampling filter;

the input end of the dressing down-sampling filter is electrically connected with the output end of the modulation circuit, and the output end of the dressing down-sampling filter is electrically connected with the input end of the time sequence analysis circuit.

According to a specific implementation manner of the embodiment of the present disclosure, the filter circuit further includes a digital wave trap;

the input end of the digital wave trap is electrically connected with the output end of the dressing down-sampling filter, and the output end of the digital wave trap is electrically connected with the input end of the time sequence analysis circuit.

According to a specific implementation manner of the embodiment of the present disclosure, the modulation circuit includes a mixer, an input end of the mixer is electrically connected to an output end of the radio frequency receiver, and an output end of the mixer is electrically connected to an input end of the timing analysis circuit.

In the embodiment of the disclosure, the amplitude reduction module is used for carrying out amplitude reduction on a mains supply signal to obtain a reference voltage, the clock circuit obtains a clock signal based on the reference signal and then provides the clock signal to the receiving circuit, and the frequency of the clock signal is an integral multiple of the power frequency; in this way, the clock accuracy of the radar sensor can be ensured.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural view of a radar sensor in the related art;

fig. 2 is a schematic structural diagram of a radar sensing assembly according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a radar sensing assembly according to another embodiment of the present invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

In the related art, as shown in fig. 1, a chip clock of the radar sensor is generated by a rc oscillator 110, and the accuracy of the chip clock is low due to the influence of process variations and temperature variations.

An embodiment of the present disclosure provides a radar sensing assembly, as shown in fig. 2, including:

the amplitude reduction module 210 is configured, an input end of the amplitude reduction module 210 is electrically connected to the mains supply interface, and the amplitude reduction module 210 performs amplitude reduction processing on a mains supply signal output by the mains supply interface to obtain and output an amplitude-reduced reference signal;

a radar sensor 220 including a clock circuit 221, a transmission circuit 222, and a reception circuit 223;

the input end of the clock circuit 221 is electrically connected to the output end of the amplitude reduction module 210, and is configured to receive the reference signal and provide a clock signal based on the reference signal, where the frequency of the clock signal is an integer multiple of a power frequency;

the transmitting circuit 222 is used for transmitting radio frequency signals;

the receiving circuit 223 receives the reflected rf signal and processes the reflected rf signal based on the clock signal to obtain a sensing result.

In the embodiment of the present disclosure, the amplitude reduction module 210 performs amplitude reduction on the commercial power signal to obtain a reference voltage, the clock circuit 221 obtains a clock signal based on the reference signal and then provides the clock signal to the receiving circuit 223, and the frequency of the clock signal is an integer multiple of the power frequency; in this way, the clock accuracy of the radar sensor 220 can be ensured.

The functional devices in the radar sensor 220 may be driven by an operating voltage, which may be obtained by converting ac to dc and stabilizing voltage of a commercial power signal.

After the amplitude reduction module 210 receives the commercial power signal, the amplitude of the commercial power signal may be reduced through amplitude reduction processing, so as to obtain an amplitude-reduced reference signal. The amplitude reduction module 210 may be a device capable of changing the waveform amplitude, such as an amplitude regulator, a voltage divider circuit, etc., and is not limited herein.

The reference signal may have a parameter consistent with a parameter of the mains signal, except that the amplitude of the reference signal is smaller than the amplitude of the mains signal.

The radar sensor 220 may be a microwave radar sensor chip, a millimeter wave radar sensor chip, a radio frequency radar sensor chip, or the like. The radar sensor 220 transmits a radio frequency signal through the transmitting circuit 222, and then receives a radio frequency signal returned after the radio frequency signal is reflected by each object in the detection environment through the receiving circuit 223, so that a sensing result of the detection environment is obtained.

The input end of the clock circuit 221 is electrically connected to the output end of the amplitude reduction module 210, and is configured to receive the reference signal and obtain a clock signal based on the reference signal, where the frequency of the clock signal is an integer multiple of a power frequency, and the power frequency is a frequency of the commercial power signal. The clock signal may be obtained by performing a series of waveform processing on the reference signal, and may specifically be a sine wave to square wave, or may be pulse width modulated, or may be in other manners, which is not limited herein.

The clock circuit 221 is used as the clock of the receiving circuit 223 in the radar sensor 200, so that the clock accuracy of the radar sensor 220 is ensured, and the clock of the radar sensor 220 and the frequency of the commercial power signal have an integer relationship. Thus, compared with the case that the clock of the radar sensor 220 does not have an integer relationship with the frequency of the mains supply signal, the resource of the filter used by the receiving circuit 223 for filtering the power frequency interference of the mains supply signal can be greatly reduced, and the cost of the radar sensor 220 is reduced; meanwhile, the loss of the signal bandwidth caused by the use of the filter can be reduced.

Further, the amplitude reduction module 210 includes a voltage divider circuit, an input end of the voltage divider circuit is electrically connected to the commercial power interface, and an output end of the voltage divider circuit is electrically connected to an input end of the clock circuit 221.

In this embodiment, the voltage divider circuit divides the commercial power signal to obtain a reference signal having the same frequency as the commercial power signal but a lower voltage, wherein the amplitude of the reference signal can be adjusted by the configuration of the voltage divider circuit.

Specifically, as shown in fig. 3, the voltage divider circuit may include a first impedance R1 and a second impedance R2, a first end of the first impedance R1 is electrically connected to the utility power interface, a second end of the first impedance R1 is electrically connected to a first end of the second impedance R2, a second end of the second impedance R2 is electrically connected to a ground GND, and a first end of the second impedance R2 is electrically connected to the input end of the clock circuit 221.

Thus, a reference signal having the same frequency as the mains signal and having a voltage amplitude smaller than the mains voltage amplitude can be obtained at the second end of the first impedance R1 or the first end of the second impedance R2. The amplitude of the reference signal can be changed by changing the magnitude relationship between the first impedance R1 and the second impedance R2, taking the first impedance and the second impedance as an example: the voltage value of the reference signal is R2/(R1+ R2).

Further, the reference signal is a sine wave signal; the clock circuit 221 includes a sine wave to square wave circuit 2211 and a frequency multiplier circuit 2212;

the input end of the sine-to-square wave circuit 2211 is electrically connected to the output end of the amplitude reduction module 210, and the sine-to-square wave circuit 2211 receives the reference signal and converts the reference signal into a square wave signal;

the input end of the frequency doubling circuit 2212 is electrically connected to the output end of the sine wave to square wave circuit 2211, and the frequency doubling circuit 2212 receives the square wave signal and converts the square wave signal into the clock signal.

In this embodiment, the sine-to-square wave circuit 2211 converts the sine wave signal into a square wave signal with the same frequency. Specifically, when the reference signal is a 50Hz sine wave signal, the sine wave to square wave circuit 2211 receives the reference signal and outputs a 50Hz square wave signal.

The frequency doubling circuit 2212 is used for frequency doubling the square wave signal to a proper frequency. Specifically, the frequency multiplier 2212 may be a phase-locked loop or a frequency-locked loop. The clock signal obtained by multiplying the frequency of the square wave signal by the frequency multiplier circuit 2212 can be used as the clock of the receiving circuit 223.

The Phase-Locked Loop (PLL) is a feedback control circuit that controls the frequency and Phase of an internal oscillation signal of the Loop by using an externally input reference signal. In the working process of the phase-locked loop, when the frequency of the output signal is equal to that of the input signal, the output voltage and the input voltage keep a fixed phase difference value, namely the phase of the output voltage and the phase of the input voltage are locked.

The frequency-locked loop is an automatic control loop, which is an automatic frequency fine-tuning circuit that is dynamically used, and can allow a voltage-controlled oscillator (VCO) and a synchronization signal to have a small steady-state frequency error when locked.

Further, as shown in fig. 2, the receiving circuit 223 includes a radio frequency receiver 2231, a modulating circuit 2232, and a timing analyzing circuit 2233;

the rf receiver 2231 receives and outputs the reflected rf signal;

the input end of the modulation circuit 2232 is electrically connected to the output end of the radio frequency receiver 2231, and the modulation circuit 2232 converts the reflected radio frequency signal into a zero intermediate frequency signal;

the input end of the timing analysis circuit 2233 is electrically connected to the output end of the modulation circuit 2232, the clock end of the timing analysis circuit 2233 is electrically connected to the clock circuit 221, and the timing analysis circuit obtains an induction result based on the zero intermediate frequency signal and the clock signal.

The transmit circuit 222 transmits radio frequency signals to detect objects in the detection environment. The radio frequency signal is a high-frequency alternating current variable electromagnetic wave, and the electromagnetic frequency range which can be radiated to the space is 300 KHz-300 GHz. In particular, the transmit circuit 222 may include a radio frequency transmitter that radiates through an antenna resonance to the detection space.

The rf receiver 2231 receives the rf signal reflected back from the detection space through the antenna. The modulation circuit 2232 directly converts the rf signal received by the rf receiver 2231 to the baseband without performing modulation and demodulation of the intermediate frequency, so as to obtain a zero intermediate frequency signal. The timing analysis circuit 2233 performs time domain analysis based on the zero intermediate frequency signal and the clock signal, thereby obtaining a sensing result.

Further, as shown in fig. 2, the timing analysis circuit 2233 is a digital circuit; the receiving circuit 223 further includes an analog-to-digital conversion circuit 2234, a clock end of the analog-to-digital conversion circuit 2234 is electrically connected to the output end of the clock circuit 221, an input end of the analog-to-digital conversion circuit 2234 is electrically connected to the output end of the modulation circuit 2232, and an output end of the analog-to-digital conversion circuit 2234 is electrically connected to the input end of the timing analysis circuit 2233.

The analog-to-digital conversion circuit 2234 converts the zero intermediate frequency signal, which is originally an analog signal, into a digital signal based on the clock signal, so that the timing analysis circuit 2233 can smoothly perform time domain analysis based on the zero intermediate frequency signal.

Further, as shown in fig. 2, the receiving circuit 223 further includes a filtering circuit 2235;

the input end of the filter circuit 2235 is electrically connected to the output end of the modulation circuit 2232, and the filter circuit 2235 filters the power frequency and the frequency doubling thereof in the zero intermediate frequency signal to obtain a signal to be analyzed;

the input end of the timing analysis circuit 2233 is electrically connected to the output end of the filter circuit 2235, and the timing analysis circuit 2233 obtains a sensing result based on the signal to be analyzed and the clock signal.

In this embodiment, before time domain analysis is performed on the zero intermediate frequency signal by the time sequence analysis circuit 2233, the power frequency and the frequency multiplication thereof in the zero intermediate frequency signal are filtered by the filter circuit, so that the influence of the power frequency and the frequency multiplication thereof of the commercial power signal on the time sequence analysis can be reduced, and the sensing accuracy of the radar sensor is improved.

As shown in fig. 3, the filter circuit 2235 includes a comb down-sampling filter 22351;

an input end of the comb down-sampling filter 22351 is electrically connected to an output end of the modulation circuit 2232, and an output end of the comb down-sampling filter 22351 is electrically connected to an input end of the timing analysis circuit 2233.

The dressing down-sampling filter 22351 is used for reducing the signal sampling rate, reducing the processing difficulty of the time sequence analysis circuit 2233 on the zero intermediate frequency signal, and ensuring the rapidity of the induction result obtained by the radar sensor.

In addition, as shown in fig. 3, the filter circuit 2235 may further include a digital trap 22352;

an input terminal of the digital wave trap 22352 is electrically connected to an output terminal of the comb down-sampling filter 22351, and an output terminal of the digital wave trap 22352 is electrically connected to an input terminal of the timing analysis circuit 2233.

The digital trap 22352 can quickly attenuate the input signal at a certain frequency point to filter out the clutter in the zero intermediate frequency signal in a manner of blocking the passing of the frequency signal, thereby eliminating the influence of the clutter on the time sequence analysis and improving the sensing accuracy of the radar sensor.

Further, the modulation circuit 2232 includes a mixer, an input of which is electrically connected to the output of the radio frequency receiver, and an output of which is electrically connected to the input of the timing analysis circuit 2233.

In this embodiment, one input end of the mixer is electrically connected to an output end of the rf receiver, and an input signal of the mixer is an rf signal; the input signal received by the other input end of the mixer is a baseband signal, and the mixer directly obtains a zero intermediate frequency signal by mixing the reflected radio frequency signal with the baseband signal.

Of course, in other embodiments of the present disclosure, the modulation circuit 2232 may also convert the reflected rf signal into a zero intermediate frequency signal by other means, which is not limited herein.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.