阅读说明：本技术 存储器的时钟延时调整方法及装置、存储介质、终端 (Clock delay adjusting method and device of memory, storage medium and terminal ) 是由 程静思 陆炳华 丁展如 肖斌 于 2020-12-18 设计创作，主要内容包括：一种存储器的时钟延时调整方法及装置、存储介质、终端,所述方法包括：针对一个或多个存储器,在多种分析条件下,分别确定每个存储器的出端延迟裕量最小的时序路径,记为该存储器的最差时序路径,并确定所述最差时序路径的入端延迟裕量；根据所述最差时序路径的出端延迟裕量与入端延迟裕量,选择待调整存储器；根据预设调整比例,将所述待调整存储器所有时序路径的入端延迟裕量的一部分调整至出端延迟裕量。本发明可以有效优化和修正时序违例,提高通信准确性,进而提高芯片综合性能。(A clock delay adjusting method and device of a memory, a storage medium and a terminal are provided, the method comprises the following steps: aiming at one or more memories, respectively determining a timing sequence path with the minimum output end delay margin of each memory under various analysis conditions, marking the timing sequence path as the worst timing sequence path of the memory, and determining the input end delay margin of the worst timing sequence path; selecting a memory to be adjusted according to the output end delay allowance and the input end delay allowance of the worst time sequence path; and adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to a preset adjusting proportion. The invention can effectively optimize and correct the time sequence violation, improve the communication accuracy and further improve the comprehensive performance of the chip.)

1. A method for adjusting clock delay of a memory is characterized by comprising the following steps:

aiming at one or more memories, respectively determining a timing sequence path with the minimum output end delay margin of each memory under various analysis conditions, marking the timing sequence path as the worst timing sequence path of the memory, and determining the input end delay margin of the worst timing sequence path;

selecting a memory to be adjusted according to the output end delay allowance and the input end delay allowance of the worst time sequence path;

and adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to a preset adjusting proportion.

2. The method of adjusting clock latency of a memory according to claim 1, wherein the input-end delay margin is used to indicate a delay margin before data enters the memory, and the input-end delay margin checks a corresponding delay margin for a setup time;

the output end delay allowance is used for indicating the delay allowance after the data leaves the memory, and the output end delay allowance is the corresponding delay allowance of the establishment time check.

3. The method of claim 1, wherein selecting the memory to be adjusted according to an outbound delay margin and an inbound delay margin of the worst timing path comprises:

judging whether a memory meets the condition that the output end delay allowance of the worst time sequence path is smaller than a first allowance threshold value and the input end delay allowance is larger than or equal to a second allowance threshold value under various analysis conditions;

if yes, determining the memory as the memory to be adjusted;

wherein the first margin threshold is less than or equal to a second margin threshold.

4. The method of claim 1, wherein adjusting a portion of an ingress delay margin of all timing paths of the memory to be adjusted to an egress delay margin according to a preset adjustment ratio comprises:

determining a margin difference value between an output end delay margin and an input end delay margin of the worst timing sequence path of the memory to be adjusted;

calculating the product of the preset adjustment proportion and the margin difference value to obtain a margin product;

adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to the product of the allowances;

wherein a portion of the ingress delay margin is less than or equal to the margin product.

5. The method for adjusting clock delay of a memory according to claim 4, wherein the predetermined adjustment ratio is selected from 30% to 70%.

6. The method of claim 4, wherein adjusting a portion of an ingress delay margin to an egress delay margin of all timing paths of the memory to be adjusted according to the margin product comprises:

determining delay values of one or more clock buffers of the memory to be adjusted under various analysis conditions;

determining the number of clock buffers of the memory to be adjusted which need to be adjusted under various analysis conditions according to the product of the margin and the delay values under various analysis conditions;

determining the minimum value of the number of each clock buffer needing to be adjusted, and recording the minimum value as the minimum value;

under various analysis conditions, the minimum number of clock buffers of the memory to be adjusted is reduced so as to adjust a part of the input end delay margin of all timing paths of the memory to be adjusted to the output end delay margin.

7. The clock delay adjustment method of a memory according to claim 6,

determining the number of the clock buffers of the memory to be adjusted which need to be adjusted under various analysis conditions according to the margin product and the delay values under various analysis conditions comprises:

under various analysis conditions, respectively calculating the ratio of the margin product to the delay value;

and performing rounding-down processing on the obtained ratio to serve as the number of the clock buffers needing to be adjusted under the corresponding analysis condition.

8. The method for adjusting clock delay of a memory according to claim 6, further comprising:

and determining the actual adjustment delay values of the memory to be adjusted under various analysis conditions according to the product of the delay values of the one or more clock buffers of the memory to be adjusted under various analysis conditions and the minimum number.

9. The method for adjusting clock delay of a memory according to claim 8, further comprising:

under various analysis conditions, respectively determining a clock port of a starting point of a worst time sequence path of the memory to be adjusted;

and determining a timing constraint file under various analysis conditions based on the actual adjustment delay values of the memory to be adjusted under various analysis conditions and the clock port.

10. A clock delay adjustment apparatus for a memory, comprising:

the worst timing path determining module is used for respectively determining a timing path with the minimum output end delay margin of each memory under various analysis conditions for one or more memories, marking the timing path as the worst timing path of the memory, and determining the input end delay margin of the worst timing path;

a memory to be adjusted determining module, configured to select a memory to be adjusted according to an output end delay margin and an input end delay margin of the worst timing path;

and the delay margin adjusting module is used for adjusting a part of the input end delay margin of all the time sequence paths of the memory to be adjusted to the output end delay margin according to a preset adjusting proportion.

11. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the clock delay adjustment method of the memory according to any one of claims 1 to 9.

12. A terminal comprising a memory and a processor, said memory having stored thereon a computer program operable on said processor, wherein said processor executes the computer program to perform the steps of the clock delay adjustment method of the memory of any of claims 1 to 9.

Technical Field

The present invention relates to the field of chip design technologies, and in particular, to a clock delay adjustment method and apparatus for a memory, a storage medium, and a terminal.

Background

In the prior art, factors affecting chip Performance are complex and random, and in order to obtain better chip comprehensive Performance in a logic synthesis stage, for example, to better realize balance among low Power consumption, good Performance and small Area (PPA), clock delay of devices in a chip needs to be reasonably adjusted.

However, since a memory (memory) device has a characteristic of long access time (access time), it is difficult for a From-memory slice (From-memory slice) setup time check to satisfy a timing constraint, and a timing violation problem is easily caused.

There is a need for a method for adjusting clock delay of a memory, which can effectively correct timing violations, and further optimize the comprehensive performance of the chip.

Disclosure of Invention

The invention solves the technical problem that the method and the device for adjusting the clock delay of the memory, the storage medium and the terminal can optimize the comprehensive strategy by using the determined time sequence constraint file, effectively correct the time sequence violation and improve the communication accuracy and the comprehensive performance of a chip.

To solve the above technical problem, an embodiment of the present invention provides a method for adjusting clock delay of a memory, including the following steps: aiming at one or more memories, respectively determining a timing sequence path with the minimum output end delay margin of each memory under various analysis conditions, marking the timing sequence path as the worst timing sequence path of the memory, and determining the input end delay margin of the worst timing sequence path; selecting a memory to be adjusted according to the output end delay allowance and the input end delay allowance of the worst time sequence path; and adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to a preset adjusting proportion.

Optionally, the entry-end delay margin is a delay margin before data enters the memory, and the entry-end delay margin is a delay margin corresponding to the setup time check; the output end delay allowance is used for indicating the delay allowance after the data leaves the memory, and the output end delay allowance is the corresponding delay allowance of the establishment time check.

Optionally, selecting a memory to be adjusted according to an output end delay margin and an input end delay margin of the worst timing path includes: judging whether a memory meets the condition that the output end delay allowance of the worst time sequence path is smaller than a first allowance threshold value and the input end delay allowance is larger than or equal to a second allowance threshold value under various analysis conditions; if yes, determining the memory as the memory to be adjusted; wherein the first margin threshold is less than or equal to a second margin threshold.

Optionally, adjusting a part of the ingress delay margin of all timing paths of the memory to be adjusted to the egress delay margin according to a preset adjustment ratio includes: determining a margin difference value between an output end delay margin and an input end delay margin of the worst timing sequence path of the memory to be adjusted; calculating the product of the preset adjustment proportion and the margin difference value to obtain a margin product; adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to the product of the allowances; wherein a portion of the ingress delay margin is less than or equal to the margin product.

Optionally, the preset adjustment proportion is selected from 30% to 70%.

Optionally, adjusting a part of the ingress delay margin of all timing paths of the memory to be adjusted to the egress delay margin according to the product of the margins includes: determining delay values of one or more clock buffers of the memory to be adjusted under various analysis conditions; determining the number of clock buffers of the memory to be adjusted which need to be adjusted under various analysis conditions according to the product of the margin and the delay values under various analysis conditions; determining the minimum value of the number of each clock buffer needing to be adjusted, and recording the minimum value as the minimum value; under various analysis conditions, the minimum number of clock buffers of the memory to be adjusted is reduced so as to adjust a part of the input end delay margin of all timing paths of the memory to be adjusted to the output end delay margin.

Optionally, determining, according to the product of the margins and the delay values under the various analysis conditions, the number of the clock buffers of the memory to be adjusted that respectively need to be adjusted under the various analysis conditions includes: under various analysis conditions, respectively calculating the ratio of the margin product to the delay value; and performing rounding-down processing on the obtained ratio to serve as the number of the clock buffers needing to be adjusted under the corresponding analysis condition.

Optionally, the method for adjusting the clock delay of the memory further includes: and determining the actual adjustment delay values of the memory to be adjusted under various analysis conditions according to the product of the delay values of the one or more clock buffers of the memory to be adjusted under various analysis conditions and the minimum number.

Optionally, the method for adjusting the clock delay of the memory further includes: under various analysis conditions, respectively determining a clock port of a starting point of a worst time sequence path of the memory to be adjusted; and determining a timing constraint file under various analysis conditions based on the actual adjustment delay values of the memory to be adjusted under various analysis conditions and the clock port.

To solve the above technical problem, an embodiment of the present invention provides a clock delay adjusting apparatus for a memory, including: the worst timing path determining module is used for respectively determining a timing path with the minimum output end delay margin of each memory under various analysis conditions for one or more memories, marking the timing path as the worst timing path of the memory, and determining the input end delay margin of the worst timing path; a memory to be adjusted determining module, configured to select a memory to be adjusted according to an output end delay margin and an input end delay margin of the worst timing path; and the delay margin adjusting module is used for adjusting a part of the input end delay margin of all the time sequence paths of the memory to be adjusted to the output end delay margin according to a preset adjusting proportion.

To solve the above technical problem, an embodiment of the present invention provides a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the clock delay adjustment method for the memory.

In order to solve the above technical problem, an embodiment of the present invention provides a terminal, including a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes the steps of the clock delay adjustment method of the memory when running the computer program.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the embodiment of the invention, the memory to be adjusted is selected, and then a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted is adjusted to the output end delay allowance, so that the output end delay allowance meets the establishment time and has enough time allowance, the possibility of misreading of the next device behind the memory is reduced, the timing sequence violation is effectively corrected, the optimization strategy is changed through the determined timing sequence constraint file, and the communication accuracy and the comprehensive performance of a chip are improved.

Furthermore, by setting the delay margin at the input end as the delay margin corresponding to the setup time check and setting the delay margin at the output end as the delay margin corresponding to the setup time check, consistency with a determination method of the delay margin in the prior art can be maintained, and development complexity is reduced.

Further, whether the memory meets the condition that the outgoing end delay margin of the worst time sequence path is smaller than a first margin threshold value and the incoming end delay margin is larger than or equal to a second margin threshold value or not is judged, the memory to be adjusted is selected, namely, the memory with the greater severity of the time sequence violation is adjusted in a clock delay mode, and the memory with the lesser severity of the time sequence violation is not adjusted, so that the influence on other devices in the chip is reduced, and the performance of the chip is prevented from being influenced.

Further, determining a margin difference, and adjusting a part of the input end delay margin of all time sequence paths of the memory to be adjusted to the output end delay margin by adopting the product of a preset adjustment proportion and the margin difference, which is beneficial to determining a proper adjustment amount according to specific conditions and further improving the rationality and effectiveness of delay adjustment.

Furthermore, the number of one or more clock buffers of the memory to be adjusted is adjusted, and the minimum number of the clock buffers of the memory to be adjusted is reduced under various analysis conditions, so that a part of the input-end delay margin of all timing paths of the memory to be adjusted is adjusted to the output-end delay margin, namely, after a theoretical adjustment delay value is obtained through calculation, clock delay adjustment is performed as small as possible, the influence on the performance of the memory under other analysis conditions is reduced, the influence on the performance of a chip is further avoided, and the mode of reducing the number of the clock buffers is adopted, so that the adjustment cost is lower, and the adjustment efficiency is higher.

Further, under various analysis conditions, the ratio of the product of the margins and the delay value is respectively calculated and rounded down to serve as the number of clock buffers needing to be adjusted under the corresponding analysis conditions, so that the amplitude of clock delay adjustment is further reduced, the influence on the performance of the memory under other analysis conditions is further reduced, and the influence on the performance of the chip is further avoided.

Further, the actual adjustment delay values of the memory to be adjusted under various analysis conditions are determined according to the product of the delay values of the one or more clock buffers of the memory to be adjusted under various analysis conditions and the minimum number, and the actual adjustment condition can be determined on the basis of determining the theoretical adjustment delay values and reducing the amplitude of the clock delay adjustment.

Furthermore, the time sequence constraint file under various analysis conditions is determined based on the actual adjustment delay values of the memory to be adjusted under various analysis conditions and the clock port, the actual time sequence information of the chip can be effectively represented by the time sequence constraint file, the authenticity and traceability of information records are improved, and the reliability of subsequent simulation is improved. The time sequence constraint file can change the optimization strategy of the comprehensive tool and improve the comprehensive performance of the chip.

Drawings

FIG. 1 is a diagram illustrating an ingress delay margin and an egress delay margin of a timing path of a memory according to the prior art;

FIG. 2 is a flowchart of a method for adjusting clock delay of a memory according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a working scenario based on multiple analysis conditions according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a clock delay adjustment apparatus of a memory according to an embodiment of the present invention.

Detailed Description

As described above, in the prior art, the timing constraint is hard to be satisfied by the outgoing delay margin setup time check of the memory, and the timing violation problem is likely to occur. In addition, the comprehensive performance of the chip can be improved by adjusting the delay margin of the memory.

The inventor of the present invention finds, through research, that in the chip logic synthesis process in the prior art, the memory device has a characteristic of long access time, the retention time of data after entering the memory is often long, and the requirement of reading data can be met, however, when the data leaves the memory and enters the next device (such as a register), because the time consumption is long, the next device easily misreads the data of the previous batch as the currently received data, and communication errors are caused. That is, in the prior art, the memory often has a problem that an ingress delay margin (To-memory slot) is large, and an egress delay margin is small.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating an ingress delay margin and an egress delay margin of a timing path of a memory in the prior art.

As shown in FIG. 1, the incoming delay margin of the memory is 500 picoseconds (ps), so the setup time is easily satisfied and has a large time margin, while the outgoing delay margin of the memory is just 0 picoseconds, barely satisfies the setup time and has no time margin at all.

It is understood that the ingress delay margin is generally much larger than the egress delay margin due to the long access time characteristics of the memory device itself.

In the embodiment of the invention, the memory to be adjusted is selected, and then a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted is adjusted to the output end delay allowance, so that the output end delay allowance meets the establishment time and has enough time allowance, the possibility of misreading of the next device behind the memory is reduced, and the communication accuracy and the comprehensive performance of a chip are effectively improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 2, fig. 2 is a flowchart of a method for adjusting clock delay of a memory according to an embodiment of the present invention. The clock delay adjustment method may include steps S21 to S23:

step S21: aiming at one or more memories, respectively determining a timing sequence path with the minimum output end delay margin of each memory under various analysis conditions, marking the timing sequence path as the worst timing sequence path of the memory, and determining the input end delay margin of the worst timing sequence path;

step S22: selecting a memory to be adjusted according to the output end delay allowance and the input end delay allowance of the worst time sequence path;

step S23: and adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to a preset adjusting proportion.

In a specific implementation of step S21, the worst timing path for the memory is determined under a variety of analysis conditions.

Specifically, since factors affecting the performance of the chip are complex and random, and a tradeoff among a plurality of conditions, such as low power consumption, good performance, and small area, needs to be realized, a Multi-Mode Multi-condition (MMMC) method is often adopted to verify the performance of the chip. The multi-mode is also called as multiple working modes, and may include a function mode (function mode), a scan mode (scan mode), a sleep mode (sleep mode), a pending mode (standby mode), an active mode (active mode), and the like; the multi-condition (corner) may include Process, Voltage and Temperature (PVT), and the like.

In the MMMC mode, the timing, area and power consumption can be optimized under different analysis conditions (analysis view) for one or more memories, so that the memory can obtain better performance under one or more analysis conditions.

In a specific implementation, after the integration process is completed, the output delay margins of the timing paths of each memory are determined under various analysis conditions, and then the worst timing path of each memory is determined under various analysis conditions, where the determination method is to determine the timing path with the smallest output delay margin.

Referring to fig. 3, fig. 3 is a schematic diagram of a working scenario based on multiple analysis conditions in an embodiment of the present invention.

As shown in fig. 3, the margin information of the same batch of memories may be confirmed under the first analysis condition, the second analysis condition, and the nth analysis condition, respectively, that is, the first memory, the second memory, and the third memory through the mth memory may be confirmed under each analysis condition. Wherein M, N is a positive integer.

It should be noted that the worst timing path includes the case where both the incoming side and the outgoing side are worst (e.g., the delay margin is smallest).

Specifically, the worst timing path on the side of the egress end may be determined according to the minimum delay margin of the egress end, the ingress end may be determined according to the clock port, and the worst timing path on the side of the ingress end of the worst timing path may be obtained according to the minimum delay margin of the ingress end.

In a specific implementation, timing information, including the outbound delay margin, may be obtained by using conventional tool commands in an existing integrated database. Further, for each memory, according to the clock port of the starting point corresponding to the output-end delay margin of the worst timing path, obtaining an input-end delay margin under the control of the same clock port, that is, the input-end delay margin of the worst timing path.

Further, the input end delay margin is used for indicating a delay margin before data enters the memory, and the input end delay margin is a corresponding delay margin checked by the establishing time; the output end delay allowance is used for indicating the delay allowance after the data leaves the memory, and the output end delay allowance is the corresponding delay allowance of the establishment time check.

In the embodiment of the invention, the consistency with the determination method of the delay margin in the prior art can be kept and the development complexity can be reduced by setting the delay margin at the input end as the delay margin corresponding to the establishment time check and setting the delay margin at the output end as the delay margin corresponding to the establishment time check. Specifically, since the current integration tool only optimizes the setup time, the obtained ingress delay margin and the egress delay margin are both delay margins corresponding to the setup time check.

With continued reference to fig. 2, in a specific implementation of step S22, a memory to be adjusted is selected according to an outbound delay margin and an inbound delay margin of the worst timing path.

Further, the step of selecting a memory to be adjusted according to an output end delay margin and an input end delay margin of the worst timing path may include: judging whether a memory meets the condition that the output end delay allowance of the worst time sequence path is smaller than a first allowance threshold value and the input end delay allowance is larger than or equal to a second allowance threshold value under various analysis conditions; if yes, determining the memory as the memory to be adjusted; wherein the first margin threshold is less than or equal to a second margin threshold.

Specifically, under each analysis condition, an outgoing end delay margin and an incoming end delay margin of the same memory are compared, and whether the outgoing end delay margin meeting the worst timing path is smaller than a first margin threshold value or not is judged, and the incoming end delay margin is larger than or equal to a second margin threshold value.

Taking the value of N shown in fig. 3 as 3 and the value of M as 4 as an example, in a specific embodiment, under a first analysis condition, an outgoing delay margin of the worst timing path is less than a first margin threshold and an incoming delay margin is greater than or equal to a second margin threshold when the second memory and the third memory meet the worst timing path; under a second analysis condition, the second memory and the fourth memory meet the condition that the outgoing end delay allowance of the worst time sequence path is smaller than a first allowance threshold, and the incoming end delay allowance is larger than or equal to a second allowance threshold; under a third analysis condition, the second memory, the third memory and the fourth memory meet the condition that the outgoing delay allowance of the worst time sequence path is smaller than the first allowance threshold, and the incoming delay allowance is larger than or equal to the second allowance threshold.

And then determining whether conditions that the memory meets the first margin threshold value and the second margin threshold value under various analysis conditions exist or not based on all analysis conditions, and if so, determining that the memory is a memory to be adjusted.

As in the above-described embodiment, if only the second memory satisfies the condition that the first margin threshold and the second margin threshold are satisfied under the first analysis condition, the second analysis condition, and the third analysis condition, the second memory is determined as the memory to be adjusted.

In the embodiment of the invention, whether the memory meets the condition that the outgoing end delay margin of the worst time sequence path is smaller than the first margin threshold value and the incoming end delay margin is larger than or equal to the second margin threshold value under various analysis conditions is judged, and the memory to be adjusted is selected, namely, clock delay adjustment is only carried out on the memory with larger severity of the outgoing end time sequence violation or smaller delay margin, and the memory with smaller severity of the outgoing end time sequence violation or larger delay margin is not adjusted, so that the influence on other devices in a chip is reduced, and the performance of the chip is prevented from being influenced.

With continued reference to fig. 2, in a specific implementation of step S23, a part of the ingress delay margin of all timing paths of the memory to be adjusted is adjusted to the egress delay margin according to a preset adjustment ratio.

Further, the step of adjusting a part of the ingress delay margin of all timing paths of the memory to be adjusted to the egress delay margin according to a preset adjustment ratio may include: determining a margin difference value between an output end delay margin and an input end delay margin of the worst timing sequence path of the memory to be adjusted; calculating the product of the preset adjustment proportion and the margin difference value to obtain a margin product; adjusting a part of the input end delay allowance of all timing sequence paths of the memory to be adjusted to an output end delay allowance according to the product of the allowances; wherein a portion of the ingress delay margin is less than or equal to the margin product.

Specifically, for the selected memory to be adjusted, the delay margin to be adjusted is calculated according to a certain proportion, that is, the product of the margins is the calculated value, and then at least a part of the calculated value is adjusted.

In the embodiment of the invention, the margin difference is determined, and at least one part of the input end delay margin of all time sequence paths of the memory to be adjusted is adjusted to the output end delay margin by adopting the product of the preset adjustment proportion and the margin difference, so that the method is favorable for determining a proper adjustment amount according to specific conditions and further improving the rationality and effectiveness of delay adjustment.

Further, the preset adjustment ratio may be selected from 30% to 70%.

As a non-limiting example, the preset adjustment ratio may be set to 40% to 60%, for example, 50%, so that after adjustment, the ingress delay margin and the egress delay margin are equal, and the memory and the subsequently connected registers have enough time margin as possible.

Furthermore, the technical solution in the embodiments of the present invention may be implemented by using a clock buffer.

Specifically, the step of adjusting a part of the ingress delay margin to the egress delay margin of all timing paths of the memory to be adjusted according to the margin product may include: determining delay values of one or more clock buffers of the memory to be adjusted under various analysis conditions; determining the number of clock buffers of the memory to be adjusted which need to be adjusted under various analysis conditions according to the product of the margin and the delay values under various analysis conditions; determining the minimum value of the number of each clock buffer needing to be adjusted, and recording the minimum value as the minimum value; under various analysis conditions, the minimum number of clock buffers of the memory to be adjusted is reduced so as to adjust a part of the input end delay margin of all timing paths of the memory to be adjusted to the output end delay margin.

Specifically, the number of clock buffers to be used may be calculated under each analysis condition, for example, the margin difference is 500ps-0 to 500ps, and the margin product is 250ps when the preset adjustment ratio is 50%. Under the first analysis condition, the delay value of each clock buffer is 125ps, and then 2 clock buffers are needed; under the second analysis condition, if the delay value of each clock buffer is 50ps, 5 clock buffers are needed; under the third analysis condition, the delay value of each clock buffer is 25ps, and 10 clock buffers are required. The minimum value at this time, i.e., the minimum value among the numbers of the respective clock buffers to be adjusted, is 2. Thereby reducing (e.g., removing) the 2 clock buffers of the memory to be adjusted in each of the first through third analysis conditions.

In the embodiment of the invention, the number of one or more clock buffers of the memory to be adjusted is adjusted, and the minimum number of the clock buffers of the memory to be adjusted is reduced under various analysis conditions, so that a part of the input end delay margin of all timing paths of the memory to be adjusted is adjusted to the output end delay margin, namely, after the theoretical adjustment delay value is obtained through calculation, the clock delay adjustment is performed in a small range as much as possible, the influence on the performance of the memory under other analysis conditions is favorably reduced, the influence on the performance of a chip is further avoided, and the mode of reducing the number of the clock buffers is adopted, the adjustment cost is lower, and the adjustment efficiency is higher.

Further, the step of determining the number of clock buffers of the memory to be adjusted that need to be adjusted under various analysis conditions according to the product of the margin values and the delay values under various analysis conditions may include: under various analysis conditions, respectively calculating the ratio of the margin product to the delay value; and performing rounding-down processing on the obtained ratio to serve as the number of the clock buffers needing to be adjusted under the corresponding analysis condition.

In particular, if in the foregoing embodiment the product of the margins and the delay value of the clock buffer are not divisible, then rounding down may be used to reduce the number of clock buffers removed as much as possible.

Still taking the margin difference of 500ps-0 to 500ps, and the preset adjustment ratio of 50% as an example, the margin product is 250 ps. If under a certain analysis condition, the delay value of each clock buffer is 100ps, 2.5 clock buffers are needed, i.e. cannot be divided exactly, and at this time, rounding-down can be performed, i.e. the minimum value is 2.

It can be understood that, since only a fixed number of clock buffers can be added during back-end layout and routing, but the number cannot be changed according to the scene, if rounding-up is adopted, and as many clock buffers as possible are taken out more aggressively, timing violations may occur under a certain analysis condition.

In the embodiment of the present invention, under various analysis conditions, the ratio of the product of the margins and the delay value is respectively calculated and rounded down to serve as the number of clock buffers that need to be adjusted under corresponding analysis conditions, so that there is an opportunity to further reduce the amplitude of clock delay adjustment, which is helpful to further reduce the influence on the performance of the memory under other analysis conditions, and further avoid influencing the performance of the chip.

Further, the clock delay adjustment method of the memory further comprises the step of determining an actually adjusted delay value.

Specifically, the method for adjusting the clock delay of the memory may further include: and determining the actual adjustment delay values of the memory to be adjusted under various analysis conditions according to the product of the delay values of the one or more clock buffers of the memory to be adjusted under various analysis conditions and the minimum number.

Still taking the margin difference of 500ps-0 to 500ps, and the preset adjustment ratio of 50% as an example, the margin product is 250 ps. If the delay value of each clock buffer is 100ps under a certain analysis condition, it is determined to remove 2 clock buffers after rounding down. At this time, the actual adjustment delay value of the memory to be adjusted under the analysis condition may be determined to be 100ps × 2 to 200ps according to the delay value of the clock buffer being 100ps and the minimum number 2.

In the above embodiment, the actual adjusted delay value 200ps is less than the margin product 250 ps. I.e., a portion 200ps of the adjusted ingress delay margin is less than or equal to the margin product.

In the embodiment of the present invention, the actual adjustment delay values of the memory to be adjusted under various analysis conditions are determined according to the product of the delay values of the one or more clock buffers of the memory to be adjusted under various analysis conditions and the minimum number, and the actual adjustment condition may be determined on the basis of determining the theoretical adjustment delay values and reducing the amplitude of the clock delay adjustment.

Further, the clock delay adjusting method of the memory further comprises the step of determining a timing constraint file.

Specifically, the method for adjusting the clock delay of the memory may further include: under various analysis conditions, respectively determining a clock port of a starting point of a worst time sequence path of the memory to be adjusted; and determining a timing constraint file under various analysis conditions based on the actual adjustment delay values of the memory to be adjusted under various analysis conditions and the clock port.

Wherein the timing constraint file is generated during a design process of the chip. The timing constraint file may include timing constraint information, which is a file for characterizing timing information of the chip. And generating a gate-level netlist with timing information according to the timing constraint file, and performing gate-level simulation on the chip according to the gate-level netlist.

In the embodiment of the invention, the time sequence constraint file under various analysis conditions is determined based on the actual adjustment delay values of the memory to be adjusted under various analysis conditions and the clock port, and the optimization strategy can be changed and the comprehensive performance of the chip can be optimized by using the time sequence constraint file in the optimization process of the comprehensive tool.

In the embodiment of the invention, the memory to be adjusted is selected, and then a part of the input end delay allowance of all timing paths of the memory to be adjusted is adjusted to the output end delay allowance, so that the output end delay allowance meets the establishment time and has enough time allowance, the possibility of misreading of the next device behind the memory is reduced, the timing violation is effectively corrected, and the communication accuracy and the comprehensive performance of a chip are improved.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a clock delay adjustment apparatus of a memory according to an embodiment of the present invention. The clock delay adjusting apparatus may include:

a worst timing path determining module 41, configured to determine, for one or more memories, a timing path with a smallest outgoing delay margin of each memory under multiple analysis conditions, mark the timing path as a worst timing path of the memory, and determine an incoming delay margin of the worst timing path;

a to-be-adjusted memory determining module 42, configured to select a to-be-adjusted memory according to an outgoing end delay margin and an incoming end delay margin of the worst timing path;

and a delay margin adjusting module 43, configured to adjust a part of the ingress delay margin of all timing paths of the memory to be adjusted to the egress delay margin according to a preset adjustment ratio.

In the embodiment of the invention, the memory to be adjusted is selected, and then a part of the input end delay allowance of all the time sequence paths of the memory to be adjusted is adjusted to the output end delay allowance, so that the output end delay allowance meets the establishment time and has enough time allowance, thereby reducing the possibility of misreading of the next device behind the memory, effectively correcting the time sequence violation, improving the communication accuracy and further improving the comprehensive performance of the chip.

For the principle, specific implementation and beneficial effects of the clock delay adjustment apparatus of the memory, please refer to the related description of the clock delay adjustment method of the memory described above, and will not be described herein again.

Embodiments of the present invention also provide a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the above method. The storage medium may be a computer-readable storage medium, and may include, for example, a non-volatile (non-volatile) or non-transitory (non-transitory) memory, and may further include an optical disc, a mechanical hard disk, a solid state hard disk, and the like.

Specifically, in the embodiment of the present invention, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will also be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (enhanced SDRAM), SDRAM (SLDRAM), synchlink DRAM (SLDRAM), and direct bus RAM (DR RAM).

The embodiment of the invention also provides a terminal, which comprises a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor, and the processor executes the steps of the method when running the computer program. The terminal includes, but is not limited to, a mobile phone, a computer, a tablet computer and other terminal devices.

Specifically, a terminal in this embodiment may refer to various forms of User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a Mobile Station (MS), a remote station, a remote terminal, a mobile device, a user terminal, a terminal device (terminal device), a wireless communication device, a user agent, or a user equipment. The terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with a Wireless communication function, a computing device or other processing devices connected to a Wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a future 5G Network or a terminal device in a future evolved Public Land Mobile Network (PLMN), and the like, which is not limited in this embodiment.

In the embodiment of the present application, Clock skew (Clock skew) is involved, and due to different path delays from a Clock to each register, the arrival time of a signal at a Clock pin is different, and the arrival time of a Clock signal at different registers is called Clock skew, which is an important parameter for measuring the performance of a Clock Tree.

In the embodiments of the present application, effective skew (Useful skew) is involved, and generally, skew deteriorates timing (timing) results, but if reasonably used, skew may also play a role in timing recovery, and timing violations may be corrected by adjusting (borrow) time to the front or to the back for a more abundant timing path.

In the embodiments of the present application, the clock propagation delay (Latency) is referred to. Mainly refers to the delay time from the clock source to the clock input end of the timing component. It can be divided into two parts: clock source insertion delay (source latency) and clock network delay (network latency).

In the embodiment of the present application, referring to the setup time (setup time), the flip-flop must keep the data at the input of its data unchanged before the clock edge arrives; the setup time determines the maximum delay of the combinational logic between the flip-flops.

In the embodiment of the application, the hold time (hold time) is involved, and after the arrival of the clock edge, the data at the data input end of the flip-flop must be kept unchanged; the hold time determines the minimum delay of the combinational logic between the flip-flops.

In the embodiments of the present application, a delay margin (Slack) is referred to, and is generally used to indicate whether a design meets timing requirements. There is also a setup time delay margin and a hold time delay margin, if the value of the delay margin is positive, it indicates that the design can meet the setup/hold time requirements, otherwise it does not.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.