阅读说明：本技术 形成纳米孔的方法及生成的结构 (Method of forming nanopores and resulting structures ) 是由 威廉·J·杜兰德 约瑟夫·R·约翰逊 罗杰·奎恩 于 2019-07-01 设计创作，主要内容包括：提供了用于制造紧邻的良好控制的固态纳米孔及所述纳米孔的阵列的方法。在一个实施方式中,将多个井及一个或多个通道形成于基板中。井中的每一者均与通道相邻。每个井的侧壁的一部分均被暴露。暴露侧壁的该部分最接近相邻的该通道。每个井的暴露侧壁的该部分均被朝向相邻的通道侧向蚀刻。形成将所述井连接到相邻通道的纳米孔。(Methods for fabricating closely adjacent well-controlled solid-state nanopores and arrays of such nanopores are provided. In one embodiment, a plurality of wells and one or more channels are formed in a substrate. Each of the wells is adjacent to a channel. A portion of the sidewall of each well is exposed. The portion of the exposed sidewall is closest to the adjacent channel. The portion of the exposed sidewall of each well is etched laterally toward the adjacent channel. Forming a nanopore connecting the well to an adjacent channel.)

1. A method for forming a plurality of nanopores, comprising the steps of:

depositing a first layer on a substrate;

forming a plurality of wells and one or more channels in the first layer and the substrate, each of the plurality of wells adjacent to a channel of the one or more channels;

laterally etching a portion of the exposed sidewall to connect the plurality of wells to adjacent ones of the channels; and

forming a nanopore connecting each of the plurality of wells to adjacent ones of the channels.

2. The method of claim 1, further comprising the steps of: depositing a second layer over the first layer, the plurality of wells, and the one or more channels to coat each exposed face prior to exposing the portion of the sidewall of each of the plurality of wells.

3. The method of claim 2, further comprising the steps of: selectively etching the second layer from the portion of the exposed sidewall prior to laterally etching the portion of the exposed sidewall.

4. The method of claim 3, wherein the second layer is an oxide-containing layer, or

Wherein the step of selectively etching the second layer comprises liquid acid etching, or

Wherein the step of forming the nanopore comprises the steps of: a voltage is applied.

5. The method of claim 1, wherein the substrate comprises a crystalline structure, and wherein laterally etching the portion of the exposed sidewalls of the plurality of wells comprises an alkaline wet etch along the crystalline structure of the substrate.

6. The method of claim 1, wherein forming a plurality of wells and one or more channels in the first layer and the substrate comprises: forming a first well, a second well, and a channel in the first layer and the substrate, the channel disposed adjacent to the first well and the second well,

wherein the step of laterally etching the portion of exposed sidewalls to connect the plurality of wells to adjacent ones of the channels comprises the steps of: forming a first tunnel below the first layer, the first tunnel extending between the first well and the channel, and forming a second tunnel below the first layer, the second tunnel extending between the second well and the channel, and

wherein the step of forming a nanopore connecting each of the plurality of wells to adjacent ones of the channels comprises the steps of: forming a first nanopore connecting the first tunnel to the channel and a second nanopore connecting the second tunnel to the channel.

7. The method of claim 6, wherein the first nanopore is disposed less than 1 μ ι η from the second nanopore, and wherein the first nanopore is disposed substantially parallel to the second nanopore.

8. The method of claim 6, wherein the first nanopore is disposed at a substantially right angle relative to the second nanopore.

9. The method of claim 6, further comprising the steps of: depositing a second layer over the first layer, the first well, the second well, and the channel to coat each exposed surface before forming the first and second tunnels below the first layer.

10. The method of claim 9, further comprising the steps of: the second layer is selectively etched from a first portion of exposed sidewalls of the first well and a second portion of exposed sidewalls of the second well before forming the first and second tunnels under the first layer.

11. The method of claim 9, wherein the first and second tunnels are formed by a lateral etch, and wherein the lateral etch comprises an alkaline wet etch along a crystalline structure of the substrate.

12. An apparatus, comprising:

a first layer disposed on a substrate;

a first well disposed through the first layer within the substrate;

a second well disposed through the first layer within the substrate;

a channel disposed through the first layer within the substrate and adjacent to the first well and the second well;

a first laterally etched nanopore coupled to the first well and the channel; and

a second laterally etched nanopore coupled to the second well and the channel, the second nanopore disposed less than 1 μm from the first nanopore.

13. The substrate of claim 12, wherein the laterally etched first nanopore is coupled to the first well by a first angled conical tunnel and the laterally etched second nanopore is coupled to the second well by a second angled conical tunnel.

14. The substrate of claim 12, wherein the first well is disposed less than 1000nm from the second well.

15. The substrate of claim 12, wherein the second nanopore is disposed less than 1000nm from the first nanopore.

Technical Field

Aspects disclosed herein relate to methods of fabricating well-controlled solid state nanopores and arrays of well-controlled solid state nanopores in a substrate.

Background

Nanopores are widely used in applications such as deoxyribonucleic acid (DNA) and ribonucleic acid (RNA) sequencing. In one example, nanopore sequencing is performed using an electrical detection method that generally includes the steps of: delivering an unknown sample through the nanopore, the sample being immersed in a conductive fluid; and applying an electrical potential across the nanopore. The current caused by the conduction of ions through the nanopore is measured. The magnitude of the current density across the surface of the nanopore depends on the size of the nanopore and the composition of the sample (e.g., DNA or RNA) that is currently occupying the nanopore. Different nucleotides cause a characteristic change in current density across the surface of the nanopore. These changes in current are measured and used to sequence a DNA or RNA sample.

Various methods have been used for biological and macromolecular sequencing. Sequencing by synthesis, or second generation sequencing, is used to identify which bases have been attached to single stranded DNA. Third generation sequencing (which roughly includes the step of passing the entire DNA strand through a single well) is used to read the DNA directly. Some sequencing methods require that a DNA or RNA sample be minced and then recombined. In addition, some sequencing methods use biofilms and bio-wells, which have a shelf life and must be kept cool prior to use.

Solid-state nanopores, which are nano-sized pores formed on free-standing films (e.g., silicon-containing materials), have recently been used for sequencing. However, current solid-state nanopore fabrication methods (e.g., using a tunneling electron microscope, a focused ion beam, or an electron beam) cannot easily and inexpensively achieve the size and position control requirements necessary to fabricate nanopore arrays. Furthermore, current nanopore fabrication methods are time consuming and it may be difficult to fabricate a nanopore in close proximity to other nanopores.

Accordingly, there is a need in the art for improved methods of making well-controlled solid-state nanopores disposed in close proximity to one another.

Disclosure of Invention

In one aspect, a method for forming a plurality of nanopores includes the steps of: depositing a first layer on a substrate; and forming a plurality of wells and one or more channels in the first layer and the substrate. Each of the plurality of wells is adjacent to a channel. The method further comprises the steps of: laterally etching a portion of the exposed sidewall to connect the plurality of wells to adjacent ones of the channels; and forming a nanopore connecting each of the plurality of wells to adjacent ones of the channels.

In another aspect, a method for forming a plurality of nanopores includes the steps of: depositing a first layer on a substrate; and forming a first well, a second well, and a channel in the first layer and the substrate. The channel is disposed adjacent to the first well and the second well. The method further comprises the steps of: exposing a first portion of the sidewall in the first well and a second portion of the sidewall in the second well. The first portion of the exposed sidewall in the first well and the second portion of the exposed sidewall in the second well are adjacent to the channel. A first tunnel is formed below the first layer extending from the first well and the channel. A second tunnel is formed below the first layer extending from the second well and the channel. A first nanopore is formed connecting the first tunnel to the channel, and a second nanopore is formed connecting the second tunnel to the channel.

In yet another aspect, an apparatus comprises: a first well disposed within the substrate; a second well disposed within the substrate; and a channel disposed in the substrate and adjacent to the first well and the second well. The substrate further includes: a first nanopore coupled to the first well and the channel; and a second nanopore coupled to the second well and the channel. The second nanopore is disposed less than 1 μm from the first nanopore.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary aspects and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective aspects.

Fig. 1 is a process flow of a method for forming a plurality of nanopores according to the present disclosure.

Fig. 2A-2N depict top and cross-sectional views of a chip in which a plurality of nanopores are formed according to methods disclosed herein.

Fig. 3A-3F illustrate various embodiments of chips having various nanopore designs or layouts according to various embodiments.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one aspect may be beneficially incorporated in other aspects without further recitation.

Detailed Description

Methods for fabricating closely adjacent well-controlled solid-state nanopores and arrays of such nanopores are provided. In one embodiment, a plurality of wells and one or more channels are formed in a substrate. Each of the wells is adjacent to one of the channels. A portion of the sidewall of each well is exposed, the portion of the exposed sidewall being closest to the adjacent channel. The portion of the exposed sidewall of each well is etched laterally toward the adjacent channel. Nanopores are then formed connecting each well to adjacent channels. Each nanopore may be spaced apart from adjacent nanopores by a distance of less than 1 μm.

For example, the methods disclosed herein relate to solid state nanopore formation on a semiconductor chip. It is also contemplated that the disclosed methods may be used to form other microfluidic devices and pore-like structures on a variety of materials, including solid state and biological materials. For example, the methods disclosed herein also involve forming a pyramidal tunnel; however, other etch features and any combination thereof are also contemplated. For illustrative purposes, a silicon substrate is described; however, any suitable substrate material and dielectric material (e.g., glass) are also contemplated.

Fig. 1 is a process flow of a method 100 for forming a plurality of nanopores according to the present disclosure. Fig. 2A-2N depict top and cross-sectional views of a chip 200 in which a plurality of nanopores are formed according to the methods disclosed herein (e.g., at various stages of method 100). 2A-2N are shown in a particular sequence, it is also contemplated that the various stages of method 100 depicted in FIGS. 2A-2N may be performed in any suitable order. To facilitate a clearer understanding of the method 100, the method 100 of fig. 1 will be described and shown using various views of the chip 200 in fig. 2A-2N. Although the method 100 is described using fig. 2A-2N, other operations not shown in fig. 2A-2N may be included.

Prior to the method 100, a substrate 202 is provided. The substrate 202 is generally any suitable semiconductor substrate, such as a doped or undoped silicon (Si) substrate. The substrate 202 may have a thickness between 200 μm and 2000 μm. In one embodiment, the substrate 202 is Si with a crystal structure including <100> planes. In operation 110, a first layer 204 is deposited on the substrate 202, as shown in the cross-sectional view of fig. 2A. The first layer 204 may act as a hard mask. In at least one embodiment, the first layer 204 is a potassium hydroxide (KOH) etch-resistant barrier layer, such as silicon nitride (SiN). The first layer 204 may have a thickness between about 1nm and about 100 nm. In one embodiment, the first layer 204 has a thickness of about 50 nm. The first layer 204 is generally deposited by any suitable method, including but not limited to Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or Chemical Vapor Deposition (CVD).

In operation 120, a plurality of wells 206A-206B and one or more channels 208 are formed, as shown in FIGS. 2B-2C. Fig. 2B is a top view of chip 200, and fig. 2C is a cross-section through the line labeled 2C in fig. 2B. Each of the plurality of wells 206A-206B is disposed adjacent to one channel 208 of the one or more channels. In at least one embodiment, an even number of wells are formed on the chip 200. Although only two wells 206A-206B and one channel 208 are shown, any number of wells and channels may be utilized, as shown and described below in fig. 3A-3B. Forming at least two wells 206A-206B, or an even number of wells, allows for the pair-wise utilization of wells (and later the utilization of nanopores coupled to wells).

To form the wells 206A-206B and the channels 208 in operation 120, a first photoresist layer 210 is deposited on the first layer 204. A patterning process is then performed to form the wells 206A-206B and the vias 208. Generally, the patterning process includes the following steps: the first photoresist layer 210 is lithographed or patterned, and the first layer 204 and the substrate 202 are etched, such as by Reactive Ion Etching (RIE). The etch may be a directional etch. The first photoresist layer 210 is then removed.

The wells 206A-206B and channels 208 may be etched to a depth 213 between 10nm and 2 μm. In one embodiment, the wells 206A-206B and channels 208 are etched to a depth 213 of about 250 nm. The wells 206A-206B may be spaced apart from the channel 208 by a distance 212 of between 20nm and 500 nm. The channel 208 may have a width 214 of about 1nm to 200 nm. In one embodiment, the channel 208 may have a width 214 of less than 100 nm. Thus, the first well 206A may be spaced apart from the second well 206B by a distance of less than 1000 nm.

In operation 130, a second layer 216 (e.g., a material exhibiting a suitable degree of etch selectivity relative to the first layer 204, such as an oxide layer) is deposited or grown over the first layer 204, the plurality of wells 206A-206B, and the channels 208 to coat each exposed surface of the chip 200, as shown in FIGS. 2D-2E. Fig. 2D is a top view of chip 200, and fig. 2E is a cross-section through the line labeled 2E in fig. 2D. A second layer 216 is deposited in the conformal layer over each exposed surface of the chip 200. The second layer 216 may have a thickness between 1nm and 100 nm. In one aspect, the second layer 216 has a thickness between 5nm and 10 nm. In one embodiment, for example, by exposing the first layer 204 to oxygen or water (H)₂O) to oxidizeFirst layer 204 to form second layer 216. In another embodiment, the second layer 216 is deposited using ALD. In yet another embodiment, the second layer 216 is formed by depositing a metal or semiconductor layer, for example by ALD, CVD, or PVD, and then oxidizing the metal or semiconductor layer to form the second layer 216.

The second layer 216 may be a KOH etch resistant layer. In at least one embodiment, the second layer 216 comprises SiN. The second layer 216 may be alkali resistant. The second layer 216 generally comprises a material having a composition with respect to SiO₂But rather any suitable dielectric material with a low etch rate. Examples of suitable materials for the second layer 216 further include, but are not limited to, Al₂O₃、Y₂O₃And TiO₂. The etch rate of the second layer 216 is generally greater than about 10:1, such as about 100:1, for example about 1,000:1, as compared to the etch rate of SiN.

In operation 140, a portion of the sidewalls 222 of each of the wells 206A-206B is exposed, as shown in FIGS. 2F-2G. Fig. 2F is a top view of chip 200, and fig. 2G is a cross-section through the line labeled 2G in fig. 2F. The portion of the exposed sidewall 222 is adjacent to the channel 208 and is part of the substrate 202. In one embodiment, one or more portions of the sidewalls of the channel 208 are exposed. In such embodiments, a first portion of the sidewall of the channel 208 adjacent to the first well 206A is exposed, and a second portion of the sidewall of the channel 208 adjacent to the second well 206B is exposed. A first portion of the sidewall and a second portion of the sidewall of the channel 208 may be disposed directly opposite each other. The first portion of the sidewall and the second portion of the sidewall of the channel 208 may be disposed adjacent to each other.

To expose the portion of the sidewall 222, a second patterning process is performed. In the second patterning process, a planarization layer 218 is deposited to provide a planar surface for improving the photolithography process. A second photoresist layer 220 is then deposited over the planarization layer 218. The mask may be aligned with the portion of the sidewall 222 to be exposed. The second patterning process includes the steps of: the second photoresist layer 220 and the planarization layer 218 are lithographically or patterned. The second patterning process further includes the steps of: the second photoresist layer 220 and the planarization layer 218 are etched, such as by RIE or by a wet etch process, to expose the portions of the sidewalls 222 of the wells 206A-206B.

In operation 150, the second layer 216 is selectively etched from the portions of the exposed sidewalls 222 of the wells 206A-206B, as shown in FIGS. 2H-2I. Fig. 2H is a top view of chip 200, and fig. 2I is a cross-section through the line labeled 2I in fig. 2H. In one embodiment where portions of the sidewalls of the channels 208 are exposed in operation 140, the second layer 216 is selectively etched from the portions of the exposed sidewalls of the channels 208.

To remove the second layer 216 from the portions of the exposed sidewalls 222, a wet etchant is utilized in one embodiment. For example, a fluoride based etchant (e.g., dilute hydrofluoric acid (DHF)) may be used because the oxide is selective to fluoride etching. In another embodiment, the second layer 216 is removed from the portions of the exposed sidewalls 222 using an isotropic dry etchant. For example, the dry etchant may include fluorine-containing vapor or plasma. In one example, the fluorine-containing vapor or plasma includes fluorine ions and/or fluorine radicals. The selective etch may remove the second layer 216 while leaving the first layer 204 intact. The second layer 216 may be selectively removed from portions of the exposed sidewalls 222 while leaving the second layer 216 on the side surfaces of the wells 206A-206B, as shown in fig. 2I. The second photoresist layer 220 and the planarization layer 218 may then be removed. By removing second photoresist layer 220 and planarization layer 218, chip 200 has an alkali-resistant second layer 216 on unexposed portions of the sidewalls of wells 206A-206B and an exposed silicon crystal surface on portions of exposed sidewalls 222.

In operation 160, portions of the exposed sidewalls 222 are etched laterally toward the channel 208. The lateral etchant may include an alkaline liquid chemistry, such as KOH etchant, or by exposure to tetramethylammonium hydroxide (TMAH), as shown in fig. 2J and 2K. Fig. 2J is a top view of chip 200, and fig. 2K is a cross-section through the line labeled 2K in fig. 2J. In one embodiment, the lateral etchant includes an anisotropic etch. In another embodiment, the lateral etchant includes an isotropic etch. In one embodiment where portions of the sidewalls of the channels 208 are exposed in operation 140, the portions of the exposed sidewalls of the channels 208 are etched laterally toward the wells 206A-206B.

The lateral etching comprises the following steps: the substrate 202 is etched in parallel with the planar upper surface of the substrate 202. The lateral etch may be an anisotropic etch. Etching portions of the exposed sidewalls 222 laterally toward the channel 208 forms a tunnel 224 or path through the substrate 202 under the first layer 204. The tunnel 224 is pyramidal or frustoconical and is parallel to the flat upper surface of the first layer 204. The size of the tunnel 224 may vary depending on the size of the portion of the exposed sidewall 222. The tunnel 224 may be etched until only a thin film membrane (thin film membrane) of the second layer 216 remains between the tunnel 224 and the channel 208.

The lateral etching may be performed for a predetermined amount of time to etch the substrate 202 along crystal facets or lattices of the crystalline structure. The predetermined period of time is generally determined to reduce or eliminate lateral etching relative to the mask opening. In general, of the Si substrate 202<100>Temperature of the solution and KOH in H₂The concentration in O corresponds to the rate etch. For most situations, KOH will etch Si at a rate between about 0.4nm/s and about 20nm/s<100>And (4) a plane. The rate can be accelerated or decelerated by cooling or heating the solution. The portion of the exposed sidewall 222 may be exposed to the etchant at a temperature of 0 to 100 degrees celsius for 0.5 to 5 minutes. In one embodiment, a 30 weight percent aqueous KOH solution is heated to about 40 degrees and applied for about 1 minute.

In operation 170, a plurality of nanopores 226A-226B are formed to connect the tunnel 224 to the channel 208, as shown in FIGS. 2L-2N. Fig. 2L is a top view of chip 200, and fig. 2M is a cross-section through the line labeled 2M in fig. 2L. Fig. 2N depicts an embodiment of a chip 260 having wells 206A-206B disposed on the same side of channel 208, wherein nanopores 226A-226B are substantially parallel or coaxially aligned. The chip 260 of fig. 2N may be formed in accordance with the method 100 as described with respect to fig. 2A-2M.

The nanopores 226A-226B may be formed by applying a voltage to induce dielectric breakdown of the thin film of the second layer 216 remaining between the tunnel 224 and the channel 208, resulting in the formation of well-controlled, localized, and robust nanopores. Nanopores 226A-226B are formed at the tips of the pyramid-or frustum-shaped tunnels 224. One or more electrodes 240 may optionally be formed on the chip 200 to apply the voltage. The one or more electrodes 240 may be disposed on the second layer 216 within the wells 206A-206B and within the channel 208. The one or more electrodes 240 may then be removed after formation of the nanopores 226A-226B. In another embodiment, chip 200 includes electrodes configured to apply a voltage. A glass slide 228 may be deposited on and bonded to the second layer 216.

The applied voltage generally removes at least a portion of the second layer 216, such as by degrading a portion of the second layer 216, to form the nanopore 226-226B. The applied voltage generally includes a typical voltage that is greater than the breakdown voltage of the second layer 216. For example, the breakdown voltage of silicon oxide is typically between about 2 Million Volts (MV)/cm and about 6MV/cm, or between about 200 and 600 millivolts (mV)/nm of the material. In one aspect, the applied voltage is slightly less than the breakdown voltage of the second layer 216 and the current is applied for a longer time to slowly break down the remaining film. In another aspect, the applied voltage is greater than the breakdown voltage of the substrate material such that the nanopores 226A-226B explode through the substrate material. If nanopores 226A-226B are formed having a size greater than desired, an oxidation process may be performed to reduce the size of the nanopores 226A-226B. For example, the tips of the pyramidal or frustoconical tunnels 224 may be oxidized to reduce the size of the nanopores 226A-226B. In one embodiment, the second layer 216 is not deposited on or removed from a portion of the channel 208 disposed between the tunnels 224. In such embodiments, the lateral etching of operation 160 may be used to form the nanopores 226A-226B, and no voltage need be applied to form the nanopores 226A-226B.

Forming at least two wells 206A-206B and subsequently forming at least two nanopores 226A-226B allows the nanopores 226A-226B coupled to the wells 206A-206B to be utilized in pairs or as diplores to sequence macromolecules (e.g., proteins) and/or biopolymers (e.g., DNA). For example, the chip 200 may be filled with an electrolyte or conductive fluid that includes biopolymers and/or macromolecules. Single-stranded DNA or macromolecules may pass through nanopore 226A coupled to first well 206A and then through nanopore 226B coupled to second well 206B to determine the properties of or attach to the material of the biopolymer and/or macromolecule. The electrical properties include electrical signals that can vary based on the size and/or shape of the DNA base pairs. The nanopore 226A coupled to the first well 206A may control a collection rate at which the biopolymer and/or macromolecule may be attracted to the nanopore 226A, and the nanopore 226B coupled to the second well 206B may control a speed or rate at which the biopolymer and/or macromolecule passes through the nanopore 226B, or vice versa. In another embodiment, both nanopores 226A, 226B affect the rate at which biopolymers and/or macromolecules pass through the nanopores via application of electric fields having different magnitudes. Thus, utilizing dual nanopores allows the dual nanopores to be in fluid communication with each other, resulting in improved signal-to-noise ratios and higher capture rates of biopolymers and/or macromolecules while still maintaining control.

Because the nanopores 226A-226B have been formed according to the methods disclosed herein, the size and location of the nanopores 226A-226B are well controlled. The well-controlled size of the nanopores 226A-226B is generally a diameter suitable for sequencing a sample of a certain size. In one aspect, the size of the nanopores 226A-226B is about 100nm or less. In one aspect, the nanopores 226A-226B are between about 5nm x 5nm and about 50nm x 50 nm. In one embodiment, the nanopores 226A-226B have a diameter between about 5nm and 50 nm. In one embodiment, nanopores 226A-226B are about 20nm by 20 nm. In another aspect, the size of the nanopores 226A-226B is between about 1.5nm and about 1.8nm, such as about 1.6nm, which is approximately the size of single-stranded DNA. In another aspect, the size of the nanopores 226A-226B is between about 2nm and about 3nm, such as about 2.8nm, which is approximately the size of double-stranded DNA. The well-controlled locations of the nanopores 226A-226B are generally any location on the substrate that is suitable for the configuration of one or more nanopores. In one embodiment, nanopores 226A-226B are less than 1 μm apart from each other, such as less than 100nm apart from each other.

In one aspect, chip 200 includes an array of nanopores 226, as shown in FIGS. 3A-3F. The methods disclosed herein are generally used to control the position of each of the plurality of nanopores 226 such that a desired configuration of nanopore array is formed for sequencing or other processes. The method 100 is not limited to the operations described above and may include one or more of a variety of other operations.

Fig. 3A-3F illustrate various embodiments of chips 300, 350, respectively, having a plurality of nanopores exhibiting various designs or layouts, according to various embodiments. Chips 300 and 350 may be chip 200 of fig. 2A-2N. In addition, the channel 308, tunnel 324, wells 306A-306B, and nanopores 326A-326B of FIGS. 3A-3F may be the channel 208, tunnel 224, wells 206A-206B, and nanopores 226A-226B of FIGS. 2A-2N, respectively.

In fig. 3A-3B, chip 300 includes an array of well pairs in a right angle design. Chip 300 depicts three pairs of wells 306A-306B coupled to nanopores, where each well 306A-306B is coupled to a channel 308 by a tunnel 324. FIG. 3B shows a close-up of nanopores 326A-326B in the center of chip 300 of FIG. 3A. As shown in fig. 3B, nanopores 326A and 326B are disposed at a substantially right angle with respect to each other. In one embodiment, each of the three pairs of wells 306A-306B has distinct functions for sequencing biopolymers and/or macromolecules, such as providing different fluidic and electrical access (electrical access) to the biopolymers and/or macromolecules. For example, after the nanopores 326A-326B have been formed on the chip 300, a solution containing the sample is typically deposited in the first set of wells 306A-306B and a solution without the sample is deposited over the second set of wells 306A-306B.

Each channel 308 of chip 300 may narrow as channels 308 extend toward the center of chip 300. The channels 308 may have a width 330 of about 1 μm to 20 μm. In one embodiment, the channels 308 have a width 330 of about 10 μm. The tunnel 324 may have a length 332 of about 0.1 μm to 0.5 μm extending from one channel 308 to another channel 308. In one embodiment, the tunnel 324 has a length 332 of about 0.25 μm. In another embodiment, nanopores 326A-326B are less than 1 μm apart from each other, such as less than 100nm apart from each other. In FIGS. 3A-3B, the channel 308 has a width of up to 20 μm while still allowing the nanopores 326A-326B to be less than 1 μm apart from one another.

Because the nanopores 326A-326B are disposed at substantially right angles with respect to one another, the distance between the nanopores 326A and 326B is not dependent on the width 330 of the channel 308, as the nanopores 326A-326B are not separated by the channel 308. Having wider channels 308 also allows the tunnel 324 to be larger. Utilizing a chip 300 with closely spaced nanopores 326A-326B and larger tunnels 324 and channels 308 allows a larger amount of fluid to pass through the channels 308 and tunnels 324, resulting in less resistance encountered when sequencing biopolymers and/or macromolecules. In this manner, higher flow rates and enhanced electrical properties can be achieved, and larger biopolymers and/or macromolecules can be sequenced.

In fig. 3C-3D, according to one embodiment, chip 350 includes an array of well pairs in a parallel or coaxially aligned design. The chip 350 depicts three pairs of wells 306A-306B coupled to nanopores, wherein each well 306A-306B is coupled to a channel 308 by a tunnel 324. FIG. 3D depicts a close-up of the nanopores 326A-326B in the center of the chip 350 of FIG. 3C. As shown in fig. 3D, nanopores 326A and 326B are disposed substantially parallel or coaxially aligned with each other. In one embodiment, each of the three pairs of wells 306A-306B has distinct functions for sequencing biopolymers and/or macromolecules, such as providing different fluidic and electrical access to the biopolymers and/or macromolecules. For example, after the nanopores 326A-326B have been formed on the chip 300, a solution containing the sample is typically deposited in the first set of wells 306A-306B and a solution without the sample is deposited over the second set of wells 306A-306B.

In fig. 3E-3F, according to another embodiment, chip 370 includes an array of well pairs in an in-plane or coaxially aligned design. Chip 370 depicts three pairs of wells 306A-306B coupled to a nanopore, where each well 306A-306B is coupled to a channel 308 by a tunnel 324. FIG. 3F depicts a close-up of nanopores 326A-326B in the center of chip 370 of FIG. 3E. As shown in fig. 3F, nanopores 326A and 326B are disposed substantially in-plane or coaxially aligned with each other. The nanopores 326A and 326B are disposed near or substantially parallel to each other. The nanopores 326A and 326B may be spaced apart from one another by a distance 372. Like chip 300, the distance 372 that nanopores 326A-326B are spaced apart from each other is not dependent on the width of channel 308, as nanopores 326A-326B are not separated by channel 308. Thus, higher flow rates and enhanced electrical properties can be achieved, and larger biopolymers and/or macromolecules can be sequenced.

In one embodiment, each of the three pairs of wells 306A-306B has distinct functions for sequencing biopolymers and/or macromolecules, such as providing different fluidic and electrical access to biopolymers and/or macromolecules. For example, after the nanopores 326A-326B have been formed on the chip 300, a solution containing the sample is typically deposited in the first set of wells 306A-306B and a solution without the sample is deposited over the second set of wells 306A-306B.

The embodiments of fig. 3A-3F are merely three examples of chips having a dual nanopore design and are not limited to the embodiments described above. Any suitable dual nanopore layout or design is also contemplated.

Benefits of the present disclosure include the ability to quickly form well-controlled nanopores and nanopore arrays with closely formed nanopore pairs. The disclosed method generally provides nanopores through a thin film that are well-controlled in size and location. The method of making nanopores of well-controlled size provides improved signal-to-noise ratio and higher rates of biopolymer and/or macromolecule capture while maintaining high levels of control. Single-chain biopolymers and/or macromolecules can be captured with higher collection rates and can be transported through a nanopore with increased speed, which increases the change in current through the nanopore. Thus, improved DNA sequence reads are provided with well-controlled nanopore pairs.

While the foregoing is directed to aspects of the present disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.