阅读说明：本技术 半导体装置的形成方法 (Method for forming semiconductor device ) 是由 林大钧 潘国华 廖忠志 于 2020-05-14 设计创作，主要内容包括：在此提供一种半导体装置的形成方法。此方法包括在基板上的第一区域及第二区域内沉积半导体堆叠,其中半导体堆叠具有交替排列的第一类型的半导体材料层与第二类型的半导体层。此方法亦包括从第二区域移除半导体堆叠的一部分以形成沟槽,并且通过外延成长工艺将第二类型的半导体材料填充于沟槽中。此方法亦包括图案化位于第一区域内的半导体堆叠以形成纳米结构堆叠,图案化位于第二区域内的第二类型的半导体材料以形成鳍片结构,以及在纳米结构堆叠与鳍片结构两者上形成栅极结构。(A method of forming a semiconductor device is provided. The method includes depositing a semiconductor stack in a first region and a second region on a substrate, wherein the semiconductor stack has alternating layers of a first type of semiconductor material and a second type of semiconductor layer. The method also includes removing a portion of the semiconductor stack from the second region to form a trench, and filling the trench with a second type of semiconductor material by an epitaxial growth process. The method also includes patterning the semiconductor stack in the first region to form a nanostructure stack, patterning the second type of semiconductor material in the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.)

1. A method of forming a semiconductor device, comprising:

depositing a semiconductor stack in a first region and a second region on a substrate, wherein the semiconductor stack has a first type of semiconductor material layer and a second type of semiconductor layer arranged alternately;

removing a portion of the semiconductor stack from the second region to form a trench;

filling the second type of semiconductor material in the trench by an epitaxial growth process;

patterning the semiconductor stack in the first region to form a nanostructure stack;

patterning the second type of semiconductor material in the second region to form a fin structure; and

a gate structure is formed over both the nanostructure stack and the fin structure.

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a wrap-around gate structure and a method of fabricating the same.

Background

The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in the materials and design of integrated circuits have resulted in generations of integrated circuits, each of which has smaller and more complex circuits than the previous generation. In the development of integrated circuits, the functional density (i.e., the number of devices connected per chip area) has generally increased as the geometries (i.e., the minimum device sizes or line widths fabricated by the processes) have decreased. The size reduction process has the advantages of improving the production efficiency and reducing the related cost. However, as such size reductions have resulted in increased complexity in the structure and fabrication of integrated circuits (e.g., three-dimensional transistors), and similar developments in integrated circuit fabrication and manufacture are required to achieve these advances. For example, as device dimensions continue to shrink, device performance (e.g., device performance degradation associated with various defects) and the cost of manufacturing field effect transistors become more challenging. While approaches to addressing this challenge have generally been able to meet their intended purpose, they have not fully satisfied the needs of all aspects.

Disclosure of Invention

An embodiment of the present invention discloses a method for forming a semiconductor device, including: a semiconductor stack is deposited in a first region and a second region on a substrate, wherein the semiconductor stack has alternating layers of a first type of semiconductor material and a second type of semiconductor layer. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and filling the trench with the second type of semiconductor material by an epitaxial growth process. The method further includes patterning the semiconductor stack in the first region to form a nanostructure stack, patterning the second type of semiconductor material in the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

An embodiment of the present invention discloses a method for forming a semiconductor device, including: a stack of nanostructures is formed within a first region of a semiconductor substrate, wherein the nanostructures comprise a first semiconductor material. The method further includes forming a fin structure in a second region of the semiconductor substrate, wherein the fin structure has a second type of semiconductor material different from the first type of semiconductor material. The method further includes forming a gate structure over both the stack of nanostructures and the fin structure.

An embodiment of the present invention discloses a semiconductor device, including: a first structure having a stack of nanostructures, each of the nanostructures including a channel region, each of the nanostructures including a semiconductor material of a first type. The first structure includes a first interface layer surrounding each of the nanostructures, and a first dielectric layer surrounding the interface layer. The second structure is adjacent to the first structure. The second structure includes a fin structure including a channel region, the fin structure including a second type of semiconductor material, and the second type of semiconductor material being different than the first type of semiconductor material. The second structure includes a second interface layer surrounding the fin structure and a second dielectric layer surrounding the interface layer. The semiconductor device further includes a gate structure extending over both the first structure and the second structure.

Drawings

A full and enabling disclosure thereof is set forth in the following detailed description and is intended to be read in connection with the accompanying drawings. It should be noted that the drawings are not necessarily drawn to scale in accordance with common practice in the industry. In fact, the dimensions of the elements may be arbitrarily increased or reduced for clarity of illustration.

Fig. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, and 1J are cross-sectional views illustrating a process for forming a hybrid nanostructure and fin structure device according to an embodiment of the present invention.

Figure 2 is a top view schematic diagram of a hybrid nanostructure and fin structure device in accordance with one embodiment of the present invention.

Figure 3 is a flow diagram of an exemplary method for forming a hybrid nanostructure and fin structure device in accordance with one embodiment of the present invention.

Figure 4 is a flow diagram of an exemplary method for forming a hybrid nanostructure and fin structure device in accordance with one embodiment of the present invention.

Description of reference numerals:

101: first region

102: substrate (semiconductor substrate)

103: second region

104: layer of the second type (semiconductor material of the second type)

105: etching process

106: type one layer (semiconductor material of type one)

107: epitaxial growth process

108: groove

109: patterning process

110: semiconductor material (semiconductor layer)

111: deposition process

112: nanostructure stack

113: deposition process

114: fin structure

115: removing process

116: shallow trench isolation structure

117: removing process

118: dummy gate

119: process for the preparation of a coating

120: photoresist material

121: process for the preparation of a coating

122: dielectric layer

124: gate structure (replacement gate structure)

130: nano-structure

150: semiconductor stack

202: side wall structure

204: source/drain features

300: method of producing a composite material

302: process for the preparation of a coating

304: process for the preparation of a coating

306: process for the preparation of a coating

308: process for the preparation of a coating

310: process for the preparation of a coating

312: process for the preparation of a coating

400: method of producing a composite material

402: process for the preparation of a coating

404: process for the preparation of a coating

406: process for the preparation of a coating

Detailed Description

The following disclosure provides many different embodiments or examples for implementing different features (features) of the disclosure. The following disclosure describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the specification states a first element formed on or above a second element, that is, embodiments that may include the first element in direct contact with the second element, embodiments may include additional elements formed between the first and second elements, such that the first and second elements may not be in direct contact. In addition, the same reference numbers and/or designations may be reused for the different examples disclosed below. These iterations are for simplicity and clarity and are not intended to limit the particular relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "below," "lower," "above," "upper," and the like are used herein to facilitate describing one element or component's relationship to another element(s) or component(s) in the figures. These spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The present disclosure relates generally to semiconductor devices and their manufacture, and more particularly, to methods of manufacturing field-effect transistors (FETs), such as fin-like FETs (finfets), gate-all-around FETs (GAA FETs), and/or other field-effect transistors.

In some exemplary embodiments, the semiconductor fin may include a total of 3 to 10 alternating layers of semiconductor material in order to form a wrap-around gate device, although the disclosure is not limited to such an arrangement. In one embodiment, the first semiconductor material comprises silicon and the second semiconductor material comprises silicon germanium. One or both of the semiconductor materials may be doped with an appropriate dopant, e.g., a p-type dopant or an n-type dopant, to form the desired field effect transistor. The semiconductor material may be formed by an epitaxial process, such as, for example, a Molecular Beam Epitaxy (MBE) process, a chemical vapor deposition process, and/or other suitable epitaxial growth processes, respectively.

In many embodiments, the alternating layers of semiconductor material are configured to provide nanowire (nanowire) or nanosheet (nanoshiet) devices, such as, for example, wrap-around gate field effect transistors, the details of which are provided below. The purpose of introducing a wrap-around gate field effect transistor is to improve gate control by increasing gate-channel coupling (ate-channel coupling), reducing OFF-state current (OFF-state current), and reducing short-channel effects (short-channel effects). Multi-gate devices, such as wrap-around gate field effect transistors, typically include a gate structure that extends around its channel region (either horizontally or vertically) to provide access to the channel region from all sides. Wrap-around gate field effect transistors are generally compatible with Complementary Metal Oxide Semiconductor (CMOS) processes, allowing for a significant reduction in size while maintaining gate control and mitigating short channel effects. Of course, the present disclosure is not limited to forming a wrap-around gate field effect transistor, but other three-dimensional field effect transistors, such as a finfet, can be provided.

In a wrap-around gate device, a channel stack is formed by depositing alternating and selectively etchable layers of material. For example, a first type of semiconductor material may be epitaxially grown in the space formed between the two active regions. Then, a second type of semiconductor material may be epitaxially grown. The process continues by forming alternating layers of first and second semiconductor materials. A first etching process (e.g., a dry etching process) is then used to cut the channel stack and expose each layer of the channel stack. A second etch process (e.g., a wet etch process) may then be used to remove the first semiconductor material while leaving the second semiconductor material substantially intact. The remaining second semiconductor material may thus form a stack of nanowires or nanoplates extending between the two active regions.

In accordance with the principles described herein, a device or circuit may include a hybrid structure, and such a hybrid structure includes both a wrap-around gate structure and a finfet structure. For example, an n-type wrap-around gate structure may be fabricated adjacent to a p-type finfet structure in a single set of processes. Specifically, two different structures may be formed by depositing a semiconductor stack within a first region (e.g., an n-type region) and a second region (e.g., a p-type region) on a substrate. The semiconductor stack has alternating layers of a first type of semiconductor material (e.g., silicon) and a second type of semiconductor material (e.g., silicon germanium). Then, a portion of the semiconductor stack is removed from the second region to form a trench. An epitaxial growth process is then used to fill the second type of semiconductor material in the trench. The semiconductor stack is then patterned to form a nanostructure stack. The second type of semiconductor material within the second region is patterned in the same or another separate patterning process to form the fin structure. The fin structure may then be temporarily covered while the first type of material is removed from the nanostructure stack. A gate structure is then formed over both the nanostructure stack and the fin structure.

Fig. 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, and 1J are cross-sectional views illustrating a process for forming a hybrid nanostructure and fin structure device according to an embodiment of the present invention. Fig. 1A shows a semiconductor substrate 102 and a semiconductor stack 150. The semiconductor substrate 102 may be a silicon substrate. The semiconductor substrate may be a portion of a silicon wafer. Other semiconductor materials are also contemplated. The active region 104 may be a semiconductor that is doped to produce desired characteristics for the source/drain regions of the transistor. Substrate 102 may include an elemental semiconductor, such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; alloy semiconductors such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), indium gallium arsenide phosphide (GaInAsP), and/or other suitable materials. The substrate 102 may be a single layer of material having a uniform composition. In addition, the substrate 102 may include multiple layers of materials having similar or different compositions suitable for integrated circuit device fabrication. In one embodiment, the substrate 102 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another embodiment, the substrate 102 may include conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof.

The substrate 102 is divided into a first region 101 and a second region 103. In one embodiment, the first region 101 is an n-type region. The n-type region is a region where an n-type semiconductor device is to be formed. In one embodiment, the second region 103 is a p-type region. The p-type region is a region where a p-type structure is to be formed.

The semiconductor stack 150 includes a plurality of semiconductor layers in which first-type layers 106 made of a first-type semiconductor material are alternately arranged with second-type layers 104 made of a second-type semiconductor material. In one embodiment, the first type of semiconductor material is silicon and the second type of semiconductor material is silicon germanium. Other semiconductor materials are also contemplated. The first type layer 106 and the second type layer 104 may be formed using various processes including an epitaxial growth process. Other processes are also contemplated.

Fig. 1B illustrates a patterning process 105, removing a portion of the semiconductor stack 150 to form the trench 108. The removed portion is located within the second region 103. The trench 108 extends all the way through the semiconductor stack 150 and partially into the substrate 102. For example, the process of forming the trench 108 may be an etching process. In one embodiment, the etching process is a dry etching process. In some embodiments, a photolithographic (photolithographic) process may be used to form the trench. In particular, a photoresist material may be deposited on the semiconductor stack 150. The photoresist may then be exposed to a light source through a mask. The mask may then be developed to expose the areas where trenches 108 are to be formed. The unexposed areas may then be protected from the etching process 105.

Fig. 1C illustrates an epitaxial growth process 107 to fill the semiconductor material 110 in the trench 108. The semiconductor material 110 may be the same semiconductor material used to form the second type layer 104. The semiconductor material 110 may be, for example, silicon germanium. In some embodiments, the semiconductor material 110 may be subjected to biaxial stress (biaxial stress) due to crystal structural differences (crystalline differences) between the semiconductor layer 110 and the underlying substrate 102.

Fig. 1D illustrates a patterning process 109 to pattern the semiconductor stack 150 in the first region 101 and the semiconductor material 110 in the second region. The patterning process 109 may include one or more etching processes, for example, a dry etching process. In one embodiment, both regions 101, 103 are patterned in the same photolithography process. In other words, the mask used for the photolithography process is for both regions 101, 103. However, in some embodiments, the first region 101 and the second region 103 are patterned using separate processes. In other words, the first mask may be used to directly pattern the first region 101 (and other similar regions of the substrate). Also, a different second mask may be used to pattern the second region 103 (and other similar regions of the substrate). In some embodiments, double patterning techniques including multiple masks, spacers, and mandrel layers (mangrel layers) may be used to pattern the second region 103.

The patterning process 109 may form the nanostructure stack 112 in the first region 101 and the fin structure 114 in the second region 103. The nanostructure stack may be an elongated element extending in a direction perpendicular to the views shown in fig. 1A-1J. Similarly, the fin structures 114 may be elongated elements extending in a direction perpendicular to the views shown in fig. 1A-1J.

Fig. 1E illustrates the deposition of a Shallow Trench Isolation (STI) structure 116. The function of the shallow trench isolation structure is to electrically isolate different components from each other. In particular, the fin structures 114 may be isolated from each other and also from the nanostructure stack 112. The shallow trench isolation 116 may be a dielectric material, such as silicon nitride or silicon dioxide. The shallow trench isolation structure 116 may be formed using various deposition techniques. The shallow trench isolation layer may be formed using a deposition process 111.

Fig. 1F illustrates the formation of a dummy gate 118. Dummy gate 118 may be a temporary structure that is later replaced with a real gate. For example, the dummy gate 118 may be made of polysilicon. A layer of polysilicon (or other dummy gate material) may be deposited on the workpiece (work) using a deposition process 113 to form the dummy gate. The polysilicon layer may then be patterned to form dummy gates 118. After the dummy gate is formed, sidewall spacers are formed along sidewalls of the dummy gate. After forming the sidewalls, source/drain regions may be formed within the nanostructure stack 112 and the fin structure 114. Since fig. 1A-1J show cross-sections taken through the gate device, these figures illustrate the channel rather than the source/drain regions. A schematic top view showing the source/drain regions is shown in fig. 2 and will be described below.

In addition, an interlayer dielectric layer (ILD) may be deposited onto the workpiece to cover the nanostructure stack 112 and the portion of the fin structure 114 not covered by the dummy gate 118. After forming the sidewalls and source/drain regions, the dummy gate 118 is removed, exposing portions of the nanostructure stack 112 and fin structure 114.

Fig. 1G illustrates a removal process 115 to remove the second type of semiconductor material 104 from the nanostructure stack 112. The removal process 115 may be an isotropic etch process, such as a wet etch process. The fin structures 114 in the second region 103 may be covered prior to performing the removal process 115. In one embodiment, the fin structures 114 are covered by a photoresist material 120. The photoresist material may protect the fin structures 114 from the removal process 115. The removal process 115 may comprise a selective etch that selectively removes the second type semiconductor material 104 without substantially removing the first type semiconductor material 106. The wet etching process may use an acid-based etchant (acid-based etchant), such as: sulfuric acid (H)₂SO₄) Perchloric acid (HClO)₄) Hydriodic acid (HI), hydrobromic acid (HBr), nitric acid (HNO)₃) Hydrochloric acid (HCl), acetic acid (CH)₃COOH), citric acid (C)₆H₈O₇) Potassium periodate (KIO)₄) Tartaric acid (C)₄H₆O₆) Benzoic acid (C)₆H₅COOH), tetrafluoroboric acid (HBF)₄) Carbonic acid (H)₂CO₃) Hydrogen Cyanide (HCN), nitrous acid (HNO)₂) Hydrofluoric acid (HF) or phosphoric acid (H)₃PO₄). In some embodiments, an alkali-based etchant (alkali-based etchant) may be used. Such etchants may include, but are not limited to: ammonium hydroxide (NH)₄OH) and potassium hydroxide (KOH).

Thus, the layer 106 remaining in the nanostructure stack 112 may form nanostructures, which may be used as channels in transistor devices. The nanostructures may be nanowires or nanoplatelets, depending on their shape. Such nanostructures may form wrap-around gate devices.

Fig. 1H illustrates a removal process 117 to remove the photoresist material 120 used to protect the fin structures 114. This is done after removing the second type layer 104 from the nanostructure stack 112. After this process, the nanostructures 106 in the first region 101 (i.e., NMOS region) have a different semiconductor material than the fin structures in the second region (i.e., PMOS region). The different materials allow for fine tuning of n-type metal oxide semiconductor (NMOS) devices and p-type metal oxide semiconductor (PMOS) devices to improve their electron mobility or hole mobility.

For example, the semiconductor layer 106 forming the nanostructure may have a crystal orientation (crystal orientation) in the [100] direction. In some embodiments, the first type of semiconductor material 106 has a crystallographic orientation of [100] at the top and bottom surfaces. This orientation improves electron mobility and thus improves the efficiency of the NMOS transistor. However, the fin structure 114 may have sidewalls in the [110] direction and a top surface in the [100] direction. This structure with sidewalls having different orientations improves hole mobility and thus efficiency of the PMOS transistor. Thus, by fabricating transistors as described herein, both PMOS and NMOS transistors can be co-optimized and can be fabricated in the same cmos process.

Fig. 1I illustrates a process 119 for forming a dielectric layer 122 around the nanostructures 130 and around the fin structures 114. In some embodiments, the dielectric layer 122 may include an interfacial layer (interfacial layer) and a high dielectric constant (high-k) dielectric layer. The interfacial layer enables better adhesion of the high-k dielectric layer to the semiconductor material of the nanostructures 130 and fin structures 114. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide (hafnium aluminum oxide), or hafnium silicon oxide (hafnium silicon oxide). Other materials may also be used. For example, other materials having a dielectric constant greater than 7 may be used.

In some embodiments, a p-type workfunction metal may be deposited over fin structures 114. In this case, the nanostructures 130 may be temporarily covered with a photoresist. A deposition process may then be used to apply the p-type workfunction metal. The function of such metals is to provide the p-type metal gate with the characteristics required for the desired function. Various examples of p-type workfunction metals may include, but are not limited to: tungsten carbon nitride (WCN), tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), Tungsten Sulfur Nitride (TSN), tungsten (W), cobalt (Co), molybdenum (Mo), and the like.

In addition, an n-type workfunction metal may be formed around the nanostructures 130 on top of the dielectric layer 122. n-type workfunction metals may include, but are not limited to: aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum carbide (TiAlC), silicon aluminum titanium carbide (TiAlSiC), silicon aluminum tantalum carbide (TaAlSiC), and hafnium carbide (HfC).

Fig. 1J illustrates a process 121 for forming a replacement gate structure 124 in the space where the dummy gate 118 was present. The replacement gate structure 124 may be a metal structure, such as tungsten, copper, or cobalt. Other conductive materials are also contemplated. Using the processes described herein, n-type wrap-around gate transistors are formed in the first region 101 and p-type finfet transistors are formed in the second region 103. Thus, a hybrid device may be realized in which the n-type transistors are wrap-around gate devices and the p-type transistors are finfet devices.

Figure 2 is a schematic top view of a hybrid nanostructure and fin structure device. According to the present embodiment, the top view schematically shows the gate structure 124 extending longitudinally along the first direction. The fin structures 114 and the nanostructures 130 extend along a second direction perpendicular to the first direction. Gate structure 124 is formed between two sidewall structures 202. As described above, the sidewall structures 202 may be formed along the sidewalls of the dummy gate 118, which are subsequently removed. Gate structures 124 are then formed in the spaces between sidewall structures 202.

Fig. 2 also shows source/drain features 204 located on either side of the gate structure. Source/drain features 204 may be formed while dummy gate 118 is still in place. Source/drain features may be formed by implanting dopants into the semiconductor material. Specifically, a p-type dopant is implanted into fin structures 114 and an n-type dopant is implanted into nanostructures 130. It should be noted that for illustrative purposes, fig. 2 does not show the interlayer dielectric layer, but only the nanostructures 130, the fin structures 114, and the source/drain features 204.

Fig. 3 is a flow diagram of an exemplary method 300 for forming a hybrid nanostructure and fin structure device. According to the present embodiment, the method 300 includes a process 302 for depositing a semiconductor stack (e.g., 150) having alternating layers of a first type of semiconductor material and a second type of semiconductor material in a first region and a second region on a substrate. In one embodiment, the first region (e.g., 101) is an n-type region. The n-type region is a region where an n-type semiconductor device is to be formed. In one embodiment, the second region (e.g., 103) is a p-type region where a p-type semiconductor device is to be formed. The semiconductor stack comprises a plurality of semiconductor layers in which first-type layers made of a first-type semiconductor material are alternately arranged by second-type layers made of a second-type semiconductor material. In one embodiment, the first type of semiconductor material is silicon and the second type of semiconductor material is silicon germanium. The first type layer and the second type layer may be formed using various processes including an epitaxial growth process. Other processes are also contemplated.

According to the present embodiment, the method 300 further comprises a process 304 for removing a portion of the semiconductor stack from the second region to form a trench (e.g., 108). The removed portion is located within the second region. The trench extends all the way through the semiconductor stack and partially into the substrate. For example, the process of forming the trench 108 may be an etching process. In one embodiment, the etching process is a dry etching process. In some embodiments, a photolithographic process is used to form the trenches. In particular, a photoresist material may be deposited over the semiconductor stack. The photoresist may then be exposed to a light source through a mask. The mask may then be developed to expose the areas where the trenches are to be formed. The unexposed areas can then be protected from the etching process.

According to this embodiment, the method 300 further comprises a process 306 of filling the second type of semiconductor material in the trench by an epitaxial growth process. The semiconductor material may be the same as the semiconductor material used to form the second type layer 104. The semiconductor material 110 may be, for example, silicon germanium. In some embodiments, the semiconductor material 110 may be placed under biaxial stress due to the difference in crystal structure between the semiconductor layer and the underlying substrate.

According to this embodiment, the method 300 further includes a process 308 for patterning the semiconductor stack in the first region to form a nanostructure stack. The patterning process may include one or more anisotropic etch processes, such as a dry etch process. In some embodiments, the nanostructure stack located within is directly patterned. In some embodiments, the second type of semiconductor material (e.g., 104) may be removed from the nanostructure stack while the remaining nanostructures (e.g., 130) remain.

According to this embodiment, the method 300 further includes a process 310 for patterning the second type of semiconductor material located in the second region to form the fin structure. The patterning process may include one or more anisotropic etch processes, such as a dry etch process. In some embodiments, a dual lithography imaging technique including multiple masks, spacers, and mandrel layers may be used to pattern the second region.

According to the present embodiment, the method 300 includes a process 312 for forming a gate structure on both the nanostructure stack and the fin structure. In some embodiments, forming the gate structure includes forming a plurality of sub-layers including an interfacial layer, a high-k dielectric layer, and a work function layer. For example, the interfacial layer can provide better adhesion of the high-k dielectric layer to the semiconductor material of the nanostructure and fin structures. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide (hafnium aluminum oxide), or hafnium silicon oxide (hafnium silicon oxide). Other materials may also be used. For example, other materials having a dielectric constant greater than 7 may be used. In some embodiments, a p-type workfunction metal may be deposited over the fin structures. In this case, the nanostructures may be temporarily covered with a photoresist. A deposition process may then be used to apply the p-type workfunction metal. The function of such metals is to provide the p-type metal gate with the characteristics required for the desired function. Various examples of p-type workfunction metals may include, but are not limited to: tungsten carbon nitride (WCN), tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), Tungsten Sulfur Nitride (TSN), tungsten (W), cobalt (Co), molybdenum (Mo), and the like. In addition, an n-type workfunction metal may be formed around the nanostructure on top of the dielectric layer. n-type workfunction metals may include, but are not limited to: aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum carbide (TiAlC), silicon aluminum titanium carbide (TiAlSiC), silicon aluminum tantalum carbide (TaAlSiC), and hafnium carbide (HfC).

Figure 4 is a flow diagram of an exemplary method for forming a hybrid nanostructure and fin structure device. According to this embodiment, the method 400 includes a process 402 for forming a stack of nanostructures within a first region of a semiconductor substrate, wherein the nanostructures include a first semiconductor material. The nanostructure stack may be formed by depositing layers of different types of semiconductor materials in an alternating arrangement. In other words, the semiconductor stack is formed by depositing alternating and selectively etchable layers of material. For example, a first type of semiconductor material may be epitaxially grown. Then, a second type of semiconductor material may be epitaxially grown. The process continues by forming alternating layers of first and second semiconductor materials. A first etching process (e.g., a dry etching process) is then used to pattern the semiconductor stack and form the nanostructure stack. A second etch process (e.g., a wet etch process) may then be used to remove the first semiconductor material while leaving the second semiconductor material substantially intact. The remaining second semiconductor material may thus form a stack of nanowires or nanoplatelets.

The method 400 further includes a process 404 for forming a fin structure within a second region of the semiconductor substrate, wherein the fin structure has a second type of semiconductor material different from the first type of semiconductor material. In some embodiments, the fin structure can be formed in the same cmos process as the nanostructure stack. For example, when forming the semiconductor stack and prior to patterning it, a trench (e.g., 108) may be formed within the semiconductor stack. The trench may extend all the way through the semiconductor stack and partially into the substrate. For example, the process of forming the trench may be an etching process. In one embodiment, the etching process is a dry etching process. In some embodiments, a photolithographic process is used to form the trenches. In particular, a photoresist material may be deposited over the semiconductor stack. The photoresist may then be exposed to a light source through a mask. The mask may then be developed to expose the areas where the trenches are to be formed. The unexposed areas can then be protected from the etching process. The trenches 108 may then be filled with a semiconductor material matching the first type of semiconductor material, which may be silicon germanium in one embodiment, by an epitaxial growth process. When the semiconductor stack is patterned to form a nanostructure stack, the filled trench may also be patterned to form a fin structure. This may be done in the same patterning process or in a different patterning process.

The method 400 further includes a process 406 for forming a gate structure over both the stack of nanostructures and the fin structure. This forms a hybrid device in which the NMOS transistor comprises a wraparound gate device and the PMOS transistor comprises a finfet device. In some embodiments, forming the gate structure includes forming a plurality of sub-layers including an interfacial layer, a high-k dielectric layer, and a work function layer. For example, the interfacial layer can provide better adhesion of the high-k dielectric layer to the semiconductor material of the nanostructure and fin structures. The high-k dielectric layer may include, for example, aluminum oxide, hafnium oxide, zirconium oxide, hafnium aluminum oxide (hafnium aluminum oxide), or hafnium silicon oxide (hafnium silicon oxide). Other materials may also be used. For example, other materials having a dielectric constant greater than 7 may be used. In some embodiments, a p-type workfunction metal may be deposited over the fin structures. In this case, the nanostructures may be temporarily covered with a photoresist. A deposition process may then be used to apply the p-type workfunction metal. The function of such metals is to provide the p-type metal gate with the characteristics required for the desired function. Various examples of p-type workfunction metals may include, but are not limited to: tungsten carbon nitride (WCN), tantalum nitride (TaN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), Tungsten Sulfur Nitride (TSN), tungsten (W), cobalt (Co), molybdenum (Mo), and the like. In addition, an n-type workfunction metal may be formed around the nanostructure on top of the dielectric layer. n-type workfunction metals may include, but are not limited to: aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum carbide (TiAlC), silicon aluminum titanium carbide (TiAlSiC), silicon aluminum tantalum carbide (TaAlSiC), and hafnium carbide (HfC).

According to one embodiment, a method of forming a semiconductor device includes depositing a semiconductor stack in a first region and a second region on a substrate, wherein the semiconductor stack has alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and filling the trench with the second type of semiconductor material by an epitaxial growth process. The method further includes patterning the semiconductor stack in the first region to form a nanostructure stack, patterning the second type of semiconductor material in the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.

In some embodiments, the method further comprises removing the first type of semiconductor material from the nanostructure stack prior to forming the gate structure.

In some embodiments, the method further comprises forming an interfacial layer around remaining nanostructures of the nanostructure stack after removing the first type of semiconductor material from the nanostructure stack.

In some embodiments, the method further comprises forming a dielectric layer on the interfacial layer.

In some embodiments, the method further comprises forming an interfacial layer and a dielectric layer on the fin structure prior to forming the gate structure.

In some embodiments, in the above method, wherein forming the gate structure comprises removing a previously formed dummy gate structure.

In some embodiments, in the above method, wherein the first type of semiconductor material comprises silicon.

In some embodiments, in the above method, wherein the substrate comprises silicon.

In some embodiments, in the above method, wherein the second type semiconductor material comprises silicon germanium.

In some embodiments, in the above method, wherein the sidewalls of the fin structures have a crystalline orientation in a [110] direction.

In some embodiments, in the above method, a top surface of the above nanostructure in which the above nanostructure stack has a crystal orientation in a [100] direction.

In some embodiments, in the method, the first region comprises an n-type metal oxide semiconductor (NMOS) region, and the second region comprises a p-type metal oxide semiconductor (PMOS) region.

According to one embodiment, a method of forming a semiconductor device includes forming a stack of nanostructures in a first region of a semiconductor substrate, wherein the nanostructures include a first semiconductor material. The method further includes forming a fin structure in a second region of the semiconductor substrate, wherein the fin structure has a second type of semiconductor material different from the first type of semiconductor material. The method further includes forming a gate structure over both the stack of nanostructures and the fin structure.

In some embodiments, in the method, the first type of semiconductor material comprises silicon, and the second type of semiconductor material comprises silicon germanium.

In some embodiments, in the method, a crystal orientation of the first type of semiconductor material at the top and bottom surfaces is [100], and a crystal orientation of sidewalls of the fin structures is [110 ].

In some embodiments, in the above method, wherein the second type semiconductor material comprises germanium.

In some embodiments, in the method, the first region is an NMOS region and the second region is a PMOS region.

A semiconductor device includes a first structure having a stack of nanostructures, each of the nanostructures including a channel region, each of the nanostructures including a first type of semiconductor material. The first structure includes a first interface layer surrounding each of the nanostructures, and a first dielectric layer surrounding the interface layer. The second structure is adjacent to the first structure. The second structure includes a fin structure including a channel region, the fin structure including a second type of semiconductor material, and the second type of semiconductor material being different than the first type of semiconductor material. The second structure includes a second interface layer surrounding the fin structure and a second dielectric layer surrounding the interface layer. The semiconductor device further includes a gate structure extending over both the first structure and the second structure.

In some embodiments, in the semiconductor device, the second type of semiconductor material includes at least one of: silicon germanium, gallium arsenide, or indium phosphide.

In some embodiments, in the semiconductor device, a crystal orientation of the first type of semiconductor material at the top and bottom surfaces is [100], and a crystal orientation of the sidewalls of the fin structures is [110 ].

The foregoing outlines features of various embodiments so that those skilled in the art may better understand the aspects of the present embodiments. It should be appreciated by those skilled in the art that other processes and structures can be readily devised or modified based on the embodiments of the present invention to achieve the same purposes and/or to achieve the same advantages as described herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention. Various changes, substitutions, or alterations may be made hereto without departing from the spirit and scope of the invention.

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.