Auxiliary channel and method for operating auxiliary channel
阅读说明：本技术 辅助信道和用于操作辅助信道的方法 (Auxiliary channel and method for operating auxiliary channel ) 是由 A·A·坎普 R·潘迪 Y·拉姆辛格 于 2020-09-15 设计创作，主要内容包括：本发明题为“辅助信道和用于操作辅助信道的方法”。本发明涉及辅助信道和用于操作辅助信道的方法。该辅助信道可以包括第一PMOS晶体管和第二PMOS晶体管,该第一PMOS晶体管连接在辅助信道的两个端子之间,该第二PMOS晶体管连接到第一PMOS的栅极端子并在第一端部处经由电阻器连接到两个端子中的一个端子。该辅助信道还可以包括连接到第一PMOS晶体管和第二PMOS晶体管两者的栅极端子的支持电路。(The invention provides a secondary channel and a method for operating the secondary channel. The invention relates to a secondary channel and a method for operating a secondary channel. The auxiliary channel may comprise a first PMOS transistor connected between two terminals of the auxiliary channel and a second PMOS transistor connected to the gate terminal of the first PMOS and at a first end to one of the two terminals via a resistor. The auxiliary channel may also include support circuitry connected to the gate terminals of both the first PMOS transistor and the second PMOS transistor.)
1. A supplemental channel, comprising:
a first set of I/O pads comprising a first I/O pad and a second I/O pad;
a second set of I/O pads comprising a third I/O pad and a fourth I/O pad;
a first switching device comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second I/O pad, the second terminal is connected to the fourth I/O pad;
a second switching device comprising a fourth terminal, a fifth terminal, and a sixth terminal; wherein the fourth terminal is connected to the second I/O pad, the fifth terminal is connected to the third terminal; and
a detection circuit, the detection circuit:
connected to the first switching device via the third terminal; and
is connected to the second switching device via the sixth terminal.
2. The supplemental channel of claim 1, further characterized by comprising a resistor connected between the second I/O pad and the fourth terminal.
3. The auxiliary channel of claim 1 wherein said circuit comprises a plurality of transistors, said plurality of transistors comprising:
a first transistor comprising a first gate terminal, wherein the first transistor is connected to the sixth terminal and configured to receive an enable signal at the first gate terminal; and
a second transistor comprising a second gate terminal, wherein the second transistor is connected to the sixth terminal and configured to receive the enable signal at the second gate terminal.
4. The supplemental channel of claim 3, wherein the circuit further comprises an inverter circuit comprising:
a third transistor and a fourth transistor connected in series;
an input terminal; and
an output terminal;
wherein the input terminal is connected to the second switching device and the output terminal is connected to the third terminal of the first switching device.
5. The auxiliary channel of claim 1 further characterized by comprising a charge pump comprising an input terminal and an output terminal, wherein the input terminal is connected to a supply voltage and the output terminal is connected to the circuit.
6. The auxiliary channel of claim 5 further characterized by comprising a level shifter connected to said output terminal of said charge pump, an enable signal and said circuit.
7. The supplemental channel of claim 1, further characterized by comprising:
a third switching device comprising a seventh terminal, an eighth terminal, and a ninth terminal; wherein the seventh terminal is connected to the second I/O pad and the eighth terminal is connected to the third I/O pad; and
a fourth switching device comprising a tenth terminal and an eleventh terminal, wherein the tenth terminal is connected to the second I/O pad and the eleventh terminal is connected to the ninth terminal of the third switching device.
8. A method for operating an auxiliary channel having an input pad, an output pad, a charge pump, and a plurality of switches, comprising:
operating the auxiliary channel in a normal mode, wherein:
the charge pump is turned on and the charge pump is turned off,
a first switch from the plurality of switches connected between the input pad and the output pad is on; and is
A second switch from the plurality of switches connected to the input pad and the first switch is open; and
operating the secondary channel in a high impedance mode, wherein:
the charge pump is turned off and the charge pump is turned off,
the first switch is open; and is
The second switch is on.
9. The method of claim 8, wherein the auxiliary channel further comprises circuitry connected to the first switch and the second switch and comprising:
a first transistor connected to the second switch, wherein the first transistor:
is off during the normal mode; and
is on during the high impedance mode.
10. The method of claim 9, wherein the circuit further comprises a second transistor and a third transistor, wherein:
the second transistor:
to the first transistor, the second switch and the third transistor; and is
Is off during the normal mode; and
is on during the high impedance mode; and is
The third transistor:
connected to the charge pump and the first switch;
is off during the normal mode; and
is on during the high impedance mode.
Technical Field
The present invention relates to a secondary channel (channel) and a method for operating a secondary channel.
Background
Many electrical systems utilize an interface to transfer data between a host device and a receiving device. In some applications, such as in Displayport (DP) applications, the interface may include an auxiliary channel to transmit device management and device control data, such as "handshaking" signals, between the DP transmitter and DP receiver.
Conventional systems require the charge pump to be in an on state to power down the auxiliary channel (creating a high impedance condition). However, this requirement increases the power consumed by the charge pump. In mobile applications where extended battery life is desired, the power consumed by the charge pump to power down the auxiliary channel reduces battery life.
Disclosure of Invention
The invention relates to a secondary channel and a method for operating a secondary channel.
The auxiliary channel may comprise a first PMOS transistor connected between two terminals of the auxiliary channel and a second PMOS transistor connected at a first end via a resistor to one of the two terminals and at a second end to a gate terminal of the first PMOS transistor. The auxiliary channel may also include support circuitry connected to the gate terminals of both the first PMOS transistor and the second PMOS transistor.
The technical problem addressed by the present invention is that conventional systems require the charge pump to be in an on state to power down the auxiliary channel (creating a high impedance condition), which increases the power consumed by the charge pump and the overall system.
According to a first aspect, a secondary channel comprises: a first set of I/O pads including a first I/O pad and a second I/O pad; a second set of I/O pads including a third I/O pad and a fourth I/O pad; a first switching device comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second I/O pad, the second terminal is connected to the fourth I/O pad; a second switching device including a fourth terminal, a fifth terminal, and a sixth terminal; wherein the fourth terminal is connected to the second I/O pad, the fifth terminal is connected to the third terminal; and a circuit that: to the first switching device via the third terminal; and to the second switching device via the sixth terminal.
In one embodiment, the auxiliary channel further comprises a resistor connected between the second I/O pad and the fourth terminal.
In one embodiment, a circuit includes a plurality of transistors including: a first transistor comprising a first gate terminal, wherein the first transistor is connected to the sixth terminal and configured to receive an enable signal at the first gate terminal; and a second transistor comprising a second gate terminal, wherein the second transistor is connected to the sixth terminal and configured to receive an enable signal at the second gate terminal.
In one embodiment, the circuit further comprises an inverter circuit comprising a third transistor and a fourth transistor connected in series. An input terminal; and an output terminal; wherein the input terminal is connected to the second switching device and the output terminal is connected to the third terminal of the first switching device.
In one embodiment, the auxiliary channel further comprises a charge pump comprising an input terminal and an output terminal, wherein the input terminal is connected to a supply voltage and the output terminal is connected to the circuit.
In one embodiment, the auxiliary channel further comprises a level shifter connected to the output terminal of the charge pump, an enable signal, and the circuit.
In one embodiment, the secondary channel further comprises: a third switching device including a seventh terminal, an eighth terminal, and a ninth terminal; wherein the seventh terminal is connected to the second I/O pad, the eighth terminal is connected to the third I/O pad; and a fourth switching device including a tenth terminal and an eleventh terminal, wherein the tenth terminal is connected to the second I/O pad, and the eleventh terminal is connected to the ninth terminal of the third switching device.
According to another aspect, a method for operating an auxiliary channel having an input pad, an output pad, a charge pump, and a plurality of switches, comprises: operating the auxiliary channel in a normal mode, wherein: the charge pump is ON, a first switch from the plurality of switches connected between the input pad and the output pad is ON; and a second switch from the plurality of switches connected to the input pad and the first switch is open; and operating the secondary channel in a high impedance mode, wherein: the charge pump is OFF; the first switch is open; and the second switch is on.
In one embodiment, the auxiliary channel further comprises circuitry connected to the first switch and the second switch and comprising: a first transistor connected to the second switch, wherein the first transistor: is off during the normal mode; and is on during the high impedance mode.
In one embodiment, the circuit further comprises a second transistor and a third transistor, wherein: the second transistor: to the first transistor, the second switch and the third transistor; and is off during the normal mode; and is on during the high impedance mode; and the third transistor: connected to the charge pump and the first switch; is off during the normal mode; and is on during the high impedance mode.
The technical effect achieved by the invention is to provide an auxiliary channel which can be powered down when the charge pump is switched off, which saves the power usage of the system.
Drawings
The present technology may be more fully understood with reference to the detailed description when considered in conjunction with the following exemplary figures. In the following drawings, like elements and steps in the various drawings are referred to by like reference numerals throughout.
FIG. 1 is a block diagram of a system in accordance with an exemplary embodiment of the present technique;
FIG. 2 is a simplified circuit diagram of an auxiliary channel in accordance with an exemplary embodiment of the present technique;
FIG. 3 is a simplified circuit diagram of the auxiliary channel in accordance with an exemplary embodiment of the present technique; and is
Fig. 4 is a timing diagram of the supplemental channel in accordance with an exemplary embodiment of the present technique.
Detailed Description
The present techniques may be described in terms of functional block components and various processing steps. Such functional blocks may be realized by any number of components configured to perform the specified functions and achieve the various results. For example, the present techniques may employ various level shifters, charge pumps, amplifiers, transistors, resistive elements, switching devices, receivers, transmitters, and the like, which may perform the various functions. Further, the present techniques may be implemented in connection with any number of electronic systems (such as automotive, aerospace, "smart devices," portable devices, and consumer electronics), and the systems described are merely exemplary applications of the present techniques.
The methods and apparatus for the supplemental channel in accordance with various aspects of the present technique may operate in conjunction with any suitable communication system. For example, referring to fig. 1, an exemplary system 100 may include a host device 105 (i.e., a source device), an auxiliary channel 115 (i.e., an interface), and a receiving device 110 (e.g., a computer monitor or display screen). Both host device 105 and receive device 110 may include a transmitter TX and a receiver RX.
According to an example embodiment, the host device 105 and the auxiliary channel 115 may be connected by a transmission line and a coupling capacitor. Similarly, the auxiliary channel 115 and the receiving device 110 may be connected by a transmission line and a coupling capacitor. Thus, the host device 105 and the receiving device 110 are connected to and communicate with each other via the auxiliary channel 115, the transmission line, and the coupling capacitor. The transmission line may include any suitable communication line, bus, link, wire, cable, etc. for transmitting data. In addition, various resistive devices (e.g., resistors) may be connected to the transmission line to provide a DC bias.
The auxiliary channel 115 may provide high speed communication (data transfer) over the channel 115 at various voltages, such as at high and low voltages. In one embodiment, auxiliary channel 115 may be configured to operate at 1.8 volts for a data rate of 1Mbps (megabits per second). In other embodiments, the auxiliary channel 115 may be configured to operate at any desired supply voltage level and at any data rate.
In various embodiments, the auxiliary channel 115 may be configured as a unidirectional channel or a bidirectional channel. For example, the auxiliary channel 115 may transmit data in one direction (e.g., from the host device 105 to the receive device 110), or may transmit data in both directions (e.g., from the host device 105 to the receive device 110 and from the receive device 110 to the host device 105). The auxiliary channel 115 may have any desired architecture, such as a differential architecture or a single-ended architecture.
In an exemplary embodiment, and referring to fig. 1-3, the auxiliary channel 115 may include a first pair of I/O pads, such as a first I/O pad AUXP and a second I/O pad AUXN, connected to the host device 105 to enable signal transmission between the host device 105 and the auxiliary channel 115. In addition, the auxiliary channel 115 may also include a second pair of I/O pads connected to the receiving device 110, such as a third I/O pad SBU1 and a fourth I/O pad SBU2, to enable signal transmission between the receiving device 110 and the auxiliary channel 115. The first I/O pad AUXP may receive a first input signal V, which may have a common mode voltage of about 0 voltsIN1The second I/O pad AUXN may receive a second input signal V that may have a common-mode voltage approximately equal to the display port voltage DPVIN2And the third and fourth I/O pads SBU1, SBU2 may generate the output signal VOUT。
In an exemplary embodiment, referring to fig. 2 and 3, the auxiliary channel 115 may operate as a Multiplexer (MUX) that may be turned on and off at desired times. For example, the auxiliary channel 115 may include a plurality of switching devices disposed between various I/O pads. In an example embodiment, the auxiliary channel 115 may include a first switch N1 connected between the first I/O pad AUXP and the third I/O pad SBU1, a second switch N2 connected between the first I/O pad AUXP and the fourth I/O pad SBU2, a third switch P1 connected between the second I/O pad AUXN and the fourth I/O pad SBU2, and a fourth switch P3 connected between the second I/O pad AUXN and the third I/O pad SBU 1. Each switching device N1, N2, P1, P3 may include any device and/or circuitry suitable for controlling current flow, such as a bipolar junction transistor, a metal oxide semiconductor transistor, or the like.
In an example embodiment, the first switch N1 may include an NMOS transistor, the second switch may include an NMOS transistor, the third switch P1 may include a PMOS transistor, and the fourth switch P3 may include a PMOS transistor. Each transistor may include three terminals, such as a gate terminal and two source/drain terminals.
Further, the auxiliary channel 115 may include a fifth switch P2 connected in series with a fifth resistor R5. The fifth switch P2 may include a PMOS transistor that includes a gate terminal and two source/drain terminals. A first end of the fifth resistor R5 may be connected to the second I/O pad AUXN, and a source/drain terminal of the fifth switch P2 may be connected to a gate terminal of the third switch P1.
Further, the auxiliary channel 115 may include a sixth switch P4 connected in series with a sixth resistor R6. The sixth switch P4 may include a PMOS transistor that includes a gate terminal and two source/drain terminals. A first end of the sixth resistor R6 may be connected to the second I/O pad AUXN, and a source/drain terminal of the sixth switch P4 may be connected to a gate terminal of the fourth switch P3.
According to various embodiments, a switching device (e.g., N1, N2, P1, P2, P3, P4) may be selectively controlled (i.e., turned on and off). In an exemplary embodiment, the auxiliary channel 115 may also include a voltage generator and support circuitry 200, such as a first support circuitry 200(1) and a second support circuitry 200(2), that operate together to provide control signals to the switching devices. For example, in the case where each switching device includes a transistor, a control signal may be applied to a gate terminal of a specific switching device to control an on/off operation.
The voltage generator may be configured to be dependent on a supply voltage VDDAnd the enable signal EN generates one or more voltage levels to control the operation of the support circuit 200 and/or the switches N1, N2, P1, P2, P3, P4. In an exemplary embodiment, the voltage generator may include a charge pump 230 and a level shifter 235. However, in other embodiments, the voltage generator may include circuitry adapted to generate the required voltages, signals, currents, etc. to control the operation of the auxiliary channel 115Any circuit and/or system of (a).
The charge pump 230 may be configured to convert and/or regulate the supply voltage VDDAnd based on the supply voltage VDDGenerating a charge pump voltage VCP. For example, the charge pump 230 may utilize switching techniques and capacitive energy storage elements to achieve the desired DC output voltage. The charge pump 230 may include a capacitor adapted to be based on a supply voltage VDDAny circuit and/or system that generates one or more DC output voltages. According to an example embodiment, the charge pump 230 may provide a DC output voltage to the level shifter 235 and the first and second support circuits 200(1), (2).
The level shifter 235 may be configured to transition a signal from one domain to another. The level shifter 235 may include digital logic circuits and/or various logic devices and logic gates. In an example embodiment, the level shifter 235 may be configured to receive the charge pump voltage V from the charge pump 230CPAnd generates a corresponding output VLS(i.e., level shifter output VLS). In an exemplary embodiment, the level shifted output VLSMay include a digital value. Further, the level shifter 235 may be connected to receive an enable signal EN, wherein the enable signal may be zero volts or a supply voltage VDD(i.e., EN ═ 0V or EN ═ VDD). The level shifter 235 may convert the digital value (V)LS) To the support circuit 200.
The first 200(1) and second 200(2) support circuits may be configured to ensure that the switches P1, P2, P3, and P4 operate as needed and/or define various undefined control signal voltages with an externally defined voltage high common mode potential and the operating supply voltage (e.g., 1.8V) to achieve low power-down current. In other words, the support circuit 200 ensures that the switches P1, P2, P3, and P4 enter a truly high impedance state to effectively power down the auxiliary channel 115. According to an exemplary embodiment, the first support circuit 200(1) may be connected to the third switch P1 and the fourth switch P2. Similarly, the second supporting circuit 200(2) may be connected to a fifth switch P3 and a sixth switch P4.
In an exemplary embodiment, each support circuit 200(1), 200(2) may include a pluralityTransistors, such as transistors M1, M2, M3, and M4, each of which includes a gate terminal and two source/drain terminals. In an example embodiment, the transistors M1, M2, and M4 may comprise NMOS transistors, while the transistor M3 may comprise a PMOS transistor. Each support circuit 200 may also include an inverter 300 and a buffer 305. The inverter 300 can be based on the supply voltage VDDAnd is operable to invert the enable signal EN. The buffer 305 may be based on the charge pump voltage VCPOperates and outputs V from the level shifterLSTo transistors M3 and M4.
The gates of transistors M1 and M2 may be connected to the output terminal of inverter 300. One source terminal/drain terminal of the transistor M1 may be connected to the gate terminal of the fourth switch P2, and the remaining source terminal/drain terminal of the transistor M1 may be connected to the ground potential. One source terminal/drain terminal of the transistor M2 may be connected to the output terminal of the buffer 305 and the gate terminals of the transistors M3 and M4, and the remaining source terminal/drain terminal of the transistor M2 may be connected to the ground potential.
Together, transistors M3 and M4 may form an inverter that includes an input and an output. For example, the transistors M3 and M4 may be connected in series with each other, and the gate terminals of the transistors M3 and M4 may be connected to each other. One source/drain terminal of transistor M3 may be connected to charge pump 230 and receive charge pump voltage VCP. One source/drain terminal of the transistor M4 may be connected to ground potential. The output terminals of the transistors M3 and M4 may be connected to the gate terminal of the third switch P1.
In alternative embodiments, any configuration suitable for defining internal control signals and/or ensuring that switches (such as P1, P2, P3, and P4) are in a truly high impedance state (open) may include any number of transistors, resistors, inverters, buffers, logic gates, and the like, for each support circuit 200.
In an exemplary embodiment, the system 100 may also include external resistors connected to the auxiliary channel 115, such as resistors R1, R2, R3, and R4. Resistors R1 and R2 may be connected to the auxiliary channel 115 to define a DC common mode voltage at the first I/O pad AUXP and the second I/O pad AUXN. In an exemplary embodiment, the resistors R1 and R2 may each have a resistance value in the range of 10 kilo-ohms to 105 kilo-ohms. The resistors R3 and R4 may be connected to the third and fourth I/O pads SBU1 and SBU2, and each may have a resistance value of 1 megaohm.
Auxiliary channel 115 may receive a displayport voltage DPV defined by a particular protocol and may range from 2.89V to 3.6V (or 3.3V +/-10%) and have an input differential signal swing ranging from 270mV to 1.4V (peak-to-peak). Accordingly, the potential at the first I/O pad AUXP may be in the range of 0V to 0.3V, and the potential at the second I/O pad AUXN may be in the range of 2.89V to 3.6V.
Referring to fig. 2, the auxiliary channel 115 may operate according to a forward path or a cross path. In forward path operation, switches N1, P1, and P2 are on (active), and switches N2, P3, and P4 are off (inactive). In cross-path operation, switches N1, P1, and P2 are off (inactive), and switches N2, P3, and P4 are on (active). When the DP channel is inverted, the cross path may be enabled by either host device 105 or receive device 110.
Further, referring to fig. 3 and 4, the supplemental channel 115 may operate in a normal mode or a high impedance mode (hit) (to power down the supplemental channel 115). During the normal mode, the charge pump 230 is on and may generate a charge pump voltage V of 3.6VCPThe third switch P1 is turned on, the fourth switch P2 is turned off, the transistors M1, M2 and M3 are turned off, and the second I/O pad AUXN may receive the input voltage V of 3.6VIN. Since the fourth switch P2 is open, it does not interfere with the normal mode function in the MUX function of the auxiliary channel 115.
During the high impedance mode (power down), the charge pump 230 is turned off, the third switch P1 is turned off, the fourth switch P2 is turned on, and the second I/O pad AUXN may receive the second input voltage V of about 3.6VIN2. In addition, the support circuit 200 operates to limit the internal control signal voltage of the auxiliary channel 115 and to ensure that the third switch P1 is open. For example, the charge pump voltage VCPWill have a common mode voltage of 3.6V, transistors M1, M2 and M3 will be on, and transistor M3 will beWith a common mode voltage of 3.6V, which turns on the fourth switch P2. Accordingly, the fourth transistor P2 can transfer the DC input common mode potential of the second I/O pad AUXN to the gate of the third switch P1, thereby bringing the third switch P1 into a true high impedance state.
Furthermore, since the charge pump 230 is off during power down, the charge pump 230 does not consume power down current. In battery powered applications, this may extend the life of the battery.
In cross-path operation, the fifth switch P3 and the sixth switch P4 may operate in the normal mode and the high impedance mode as described above in conjunction with the second support circuit 200 (2). Further, the second support circuit 200(2) may be the same as the first support circuit 200(1) and operate in the same manner as the first support circuit 200(1), as described above, to control the fifth switch P3 and the sixth switch P4 during cross-path operation.
In the foregoing description, the technology has been described with reference to specific exemplary embodiments. The particular embodiments shown and described are illustrative of the technology and its best mode and are not intended to otherwise limit the scope of the technology in any way. Indeed, for the sake of brevity, conventional manufacturing, connecting, fabrication, and other functional aspects of the methods and systems may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent example functional relationships and/or steps between the various elements. There may be many alternative or additional functional relationships or physical connections in a practical system.
The described techniques have been described with reference to specific exemplary embodiments. However, various modifications and changes may be made without departing from the scope of the present technology. The specification and figures are to be regarded in an illustrative rather than a restrictive manner, and all such modifications are intended to be included within the scope of present technology. Accordingly, the scope of the described technology should be determined by the general embodiments described and their legal equivalents, rather than by merely the specific examples described above. For example, the steps recited in any method or process embodiment may be performed in any order, unless explicitly stated otherwise, and are not limited to the exact order provided in the specific examples. Additionally, the components and/or elements recited in any apparatus embodiment may be assembled or otherwise operationally configured in a variety of permutations to produce substantially the same result as the present technique and are therefore not limited to the specific configuration set forth in the specific example.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, any benefit, advantage, solution to problem or any element that may cause any particular benefit, advantage, or solution to occur or to become more pronounced are not to be construed as a critical, required, or essential feature or element.
The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, composition, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, composition, or apparatus. Other combinations and/or modifications of the above-described structures, arrangements, applications, proportions, elements, materials or components used in the practice of the present technology, in addition to those not specifically recited, may be varied or otherwise particularly adapted to specific environments, manufacturing specifications, design parameters or other operating requirements without departing from the general principles thereof.
The present technology has been described above in connection with exemplary embodiments. However, changes and modifications may be made to the exemplary embodiments without departing from the scope of the present techniques. These and other changes or modifications are intended to be included within the scope of the present technology, as set forth in the following claims.
According to a first aspect, a secondary channel comprises: a first set of I/O pads including a first I/O pad and a second I/O pad; a second set of I/O pads including a third I/O pad and a fourth I/O pad; a first switching device comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal is connected to the second I/O pad, the second terminal is connected to the fourth I/O pad; a second switching device including a fourth terminal, a fifth terminal, and a sixth terminal; wherein the fourth terminal is connected to the second I/O pad, the fifth terminal is connected to the third terminal; and a circuit that: to the first switching device via the third terminal; and to the second switching device via the sixth terminal.
In one embodiment, the auxiliary channel further comprises a resistor connected between the second I/O pad and the fourth terminal.
In one embodiment, the circuit is configured to define an internal voltage of the auxiliary channel.
In one embodiment, a circuit includes a plurality of transistors including: a first transistor comprising a first gate terminal, wherein the first transistor is connected to the sixth terminal and configured to receive an enable signal at the first gate terminal; and a second transistor comprising a second gate terminal, wherein the second transistor is connected to the sixth terminal and configured to receive an enable signal at the second gate terminal.
In one embodiment, the circuit further comprises an inverter circuit comprising a third transistor and a fourth transistor connected in series. An input terminal; and an output terminal; wherein the input terminal is connected to the second switching device and the output terminal is connected to the third terminal of the first switching device.
In one embodiment, each of the first transistor and the second transistor comprises an NMOS transistor; and the third transistor comprises a PMOS transistor.
In one embodiment, each of the first transistor and the second transistor comprises a PMOS transistor;
in one embodiment, the auxiliary channel further comprises a charge pump comprising an input terminal and an output terminal, wherein the input terminal is connected to a supply voltage and the output terminal is connected to the circuit.
In one embodiment, the auxiliary channel further comprises a level shifter connected to the output terminal of the charge pump, an enable signal, and the circuit.
In one embodiment, the secondary channel further comprises: a third switching device including a seventh terminal, an eighth terminal, and a ninth terminal; wherein the seventh terminal is connected to the second I/O pad, the eighth terminal is connected to the third I/O pad; and a fourth switching device including a tenth terminal and an eleventh terminal, wherein the tenth terminal is connected to the second I/O pad, and the eleventh terminal is connected to the ninth terminal of the third switching device.
According to a third aspect, a method for operating an auxiliary channel having an input pad, an output pad, a charge pump, and a plurality of switches, comprises: operating the auxiliary channel in a normal mode, wherein: the charge pump is on, a first switch from the plurality of switches connected between the input pad and the output pad is on; and a second switch from the plurality of switches connected to the input pad and the first switch is open; and operating the secondary channel in a high impedance mode, wherein: the charge pump is off; the first switch is open; and the second switch is on.
In one embodiment, the auxiliary channel further comprises circuitry connected to the first switch and the second switch and comprising: a first transistor connected to the second switch, wherein the first transistor: is off during the normal mode; and on during the high impedance mode.
In one embodiment, the circuit further comprises a second transistor and a third transistor, wherein: the second transistor: to the first transistor, the second switch and the third transistor; and is off during the normal mode; and on during the high impedance mode. The third transistor: connected to the charge pump and the first switch; is off during the normal mode; and on during the high impedance mode.
According to a third aspect, a system comprises: a host device connected to a receiving device via a secondary channel, wherein the secondary channel comprises: a first set of I/O pads connected to the host device, the first set of I/O pads comprising: a first I/O pad and a second I/O pad; a second set of I/O pads connected to the receiving device, the second set of I/O pads comprising: a third I/O pad and a fourth I/O pad; a plurality of switching devices connected to at least one of the first I/O pad and the second I/O pad, wherein each switching device forming the plurality of switching devices is selectively operable to drive the auxiliary channel to a high impedance mode; and a plurality of support circuits connected to at least one of the switching devices from the plurality of switching devices and configured to define an internal voltage of the auxiliary channel when the auxiliary channel is in the high impedance mode.
In one embodiment, the plurality of switching devices comprises: a first switching device connected between the second I/O pad and the fourth I/O pad; a second switching device connected to the second I/O pad and the first switching device; a third switching device connected between the second I/O pad and the third I/O pad; and a fourth switching device connected to the second I/O pad and the third switching device.
In one implementation, each of the first, second, third, and fourth switching devices includes a PMOS transistor.
In one embodiment, the system further comprises: a first resistor connected between the second I/O pad and the second switching device; and a second resistor connected between the second I/O pad and the fourth switching device.
In one embodiment, the plurality of support circuits includes: a first circuit connected to the first switching device and the second switching device; and a second circuit connected to the third switching device and the fourth switching device.
In one embodiment, the first circuit comprises: a first NMOS transistor connected to the supply voltage and the second switching device; a second NMOS transistor connected to the supply voltage and the second switching device; and a third PMOS transistor connected in series with a fourth NMOS transistor, wherein the third and fourth transistors are connected to the second NMOS transistor and the first switching device; and the second circuit comprises: a fifth NMOS transistor connected to the supply voltage and the fourth switching device; a sixth NMOS transistor connected to the supply voltage and the fourth switching device; and a seventh PMOS transistor connected in series with an eighth NMOS transistor, wherein the seventh transistor and the eighth transistor are connected to a third switching device.
In one embodiment, the system further comprises a charge pump connected to the plurality of support circuits, wherein the charge pump is turned off during the high impedance mode.