阅读说明：本技术 一种应用于hevc的自适应矩阵乘法电路 (Adaptive matrix multiplication circuit applied to HEVC (high efficiency video coding) ) 是由 江宇恒 陈佳嘉 于 2020-12-07 设计创作，主要内容包括：本发明为一种应用于高效视频编码(HEVC)的自适应矩阵乘法电路。这种电路在可重构乘法器的基础上增加了方差模块,并使用此模块根据输入矩阵自适应的调整变换矩阵,达到在不降低视频压缩质量的同时降低硬件消耗的目的。(The invention relates to an adaptive matrix multiplication circuit applied to High Efficiency Video Coding (HEVC). The circuit is additionally provided with a variance module on the basis of a reconfigurable multiplier, and the variance module is used for adaptively adjusting a transformation matrix according to an input matrix, so that the aim of reducing hardware consumption while not reducing video compression quality is achieved.)

1. An adaptive matrix multiplication circuit applied to HEVC (high efficiency video coding), comprising: a set of reconfigurable multipliers, digital signature modules, control modules, multiplexers, wherein:

(1) the digital characteristic module calculates the digital characteristic of the input matrix, compares the digital characteristic with a set threshold value, and outputs different signals according to the comparison result;

(2) the output of the digital characteristic module is sent to the control end of the multiplexer, and the signal is used as a control signal to determine the output of the multiplexer;

(3) the input of the multiplexer is delivered to a control module, and the control module sends out control signals respectively representing the selection of different transformation matrixes;

(4) the reconfigurable multiplier performs subsequent operations on the input matrix and the transformation matrix selected by the controller.

2. The adaptive matrix multiplication circuit applied to HEVC according to claim 1, wherein the digital characteristic is variance.

3. The adaptive matrix multiplication circuit applied to HEVC according to claim 2, wherein the different transform matrices in step (3) include transform matrices that can ensure that video compression quality is not degraded and transform matrices that can effectively reduce hardware consumption.

4. The adaptive matrix multiplication circuit applied to HEVC according to claim 3, wherein the method for selecting different transformation matrices in step (3) comprises the following steps:

(1) quantizing the property of the transformation matrix d into a specific value eta (d), and simultaneously quantizing the hardware consumption corresponding to the matrix into a specific value FA _ total (d);

(2) and (d) weighting and averaging eta (d) and FA _ total (d) to obtain a parameter p (d) finally used for evaluating the current transformation matrix so as to realize the balance of hardware consumption and video quality, wherein weighting factors of the eta (d) and the FA _ total (d) are respectively different in value to obtain two groups of different transformation matrices, one transformation matrix can ensure that the video compression quality is not reduced, and the other transformation matrix can effectively reduce the hardware consumption.

5. The adaptive matrix multiplication circuit applied to HEVC according to claim 4, wherein when η (d) weighting factor is 0.8, FA _ total (d) weighting factor is 0.2, transformation matrix ensuring video compression quality not to be reduced is obtained; when the weighting factor of eta (d) is 0.2 and the weighting factor of FA _ total (d) is 0.8, the transformation matrix which can effectively reduce the hardware consumption is obtained.

Technical Field

The invention relates to hardware implementation of transformation matrix multiplication used by a transformation part in High Efficiency Video Coding (HEVC), and the hardware implementation ensures low consumption while not losing compression quality compared with the original method.

Background

Since the invention of video, it has become one of the effective means for transmitting information. Nowadays, as the network speed is faster and faster, the requirements on some performances of the video, such as definition and frame rate, are higher and higher. On the basis of the above, a new research direction, namely video coding, is derived. Since the data bandwidth occupied by the video signal after digitization is very high (above 20 MB/s), it is difficult for a computer to perform subsequent processing and storage on it without video encoding. Nowadays, HEVC is widely applied, and 720P, 1080P and even 4K switched when we watch video at ordinary times are all achievements brought by continuous perfection of this technology. Especially 4K, is becoming increasingly "hard" within the industry in recent years. Meanwhile, under the development of 5G at present, 4K ultra-clear video is expected to become the mainstream in the coming years.

HEVC is divided into encoding and decoding ends, and the encoding end mainly includes intra (inter) frame prediction, transformation, quantization, entropy coding, and other steps, as shown in fig. 2. The transformation part multiplies the input residual matrix with the transformation matrix to obtain a new coefficient matrix, and if the step is not processed, the hardware cost is greatly increased. Therefore, a hardware implementation method is designed, and under the condition that the video quality is not influenced, the hardware cost can be reduced.

In recent years, there are also many methods for optimizing the transformation process of HEVC, for example, in the document, "regenerative integral Cosine Transform for HEVC and Future Video Coding Standard," the self-recursion of discrete Cosine Transform is used to derive a high-order matrix from a low-order matrix, so that the consumption of the high-order matrix is greatly reduced; in the text of "Efficient Integer DCT architecture for HEVC", the symmetry of a transform matrix is used to adjust the hardware structure, and finally, the number of multiplications and additions required for multiplying the matrix is greatly reduced.

Disclosure of Invention

The purpose of the invention is as follows: the invention relates to an adaptive matrix multiplication circuit applied to HEVC. The circuit is additionally provided with a variance module on the basis of a reconfigurable multiplier, and the variance module is used for adaptively adjusting a transformation matrix according to an input matrix, so that the aim of reducing hardware consumption while not reducing video compression quality is achieved.

The technical scheme is as follows: in order to achieve the above object, the present invention selects the digital characteristics of the input matrix itself as a part of the circuit control signals, specifically:

an adaptive matrix multiplication circuit applied to HEVC, comprising: a set of reconfigurable multipliers, digital signature modules, control modules, multiplexers, wherein:

(1) the input matrix is sent to a digital characteristic module, the digital characteristic module calculates the variance of the input matrix, compares the variance with a set threshold value, and outputs a high level or a low level according to a comparison result;

(2) the output of the digital characteristic module is sent to the control end of the multiplexer, and the signal is used as a control signal to determine the output of the multiplexer;

(3) the input of the multiplexer is delivered to a control module, and the control module sends two groups of control signals con.bit.0 and con.bit.1 which respectively represent that different transformation matrixes are selected;

(4) the reconfigurable multiplier performs subsequent operations on the input matrix and the transformation matrix selected by the controller.

Preferably, the numerical characteristic is variance.

Preferably, the method for selecting different transformation matrices includes the following steps:

(1) in Hardware Efficient Integrated Circuit Transform for Efficient Image/Video Compression, the property of the transformation matrix d is quantized to a specific value eta (d), and the Hardware consumption corresponding to the matrix is also quantized to a value FA _ total (d); then, weighted average is carried out on the two values to obtain a parameter p (d) finally used for evaluating the current transformation matrix, so that balance of hardware consumption and video quality is realized;

(2) the invention respectively takes different values for the weighting factors of the two parameters eta (d) and FA _ total (d) to obtain two groups of different transformation matrixes.

Preferably, when the weighting factor of eta (d) is 0.8 and the weighting factor of FA _ total (d) is 0.2, a transformation matrix which ensures that the video compression quality is not reduced is obtained; when the weighting factor of eta (d) is 0.2 and the weighting factor of FA _ total (d) is 0.8, the transformation matrix which can effectively reduce the hardware consumption is obtained.

Has the advantages that: compared with the prior art, the invention has the following advantages:

1. hardware consumption is reduced while video compression quality is guaranteed not to be reduced.

2. A new idea is provided, namely: the property of the input matrix is taken into consideration, and the selection of the transformation matrix is determined by taking the property of the input matrix as a reference; the properties of the input matrix may also be taken into account in conjunction with other processes of HEVC.

The innovation points of the invention can be summarized as follows:

the reconfigurable multiplier is improved, a variance module is added on the original basis, and the module and the original control module are used for forming a total control module together. Finally, the aim of reducing hardware consumption while not reducing video compression quality is achieved.

Drawings

Fig. 1 is the adaptive matrix multiplication circuit applied to HEVC described above.

Fig. 2 is a flow chart of HEVC forward transform.

Detailed Description

For the input matrix, its frequency distribution after discrete cosine transform can be estimated by its variance: when the variance is small or even 0, the low-frequency component after transformation is more (the variance is 0 represents that only the direct-current component is contained); on the other hand, a larger variance indicates a larger amount of high-frequency components in the transformed result. In the quantization process after transformation, only the shift operation is needed if only the direct current or low frequency component exists; if there are many high frequency components, it is necessary to multiply the coefficient matrix obtained in the previous step by using a quantization matrix, which is undoubtedly more complicated.

Therefore, for the matrix with large variance, attention needs to be paid to simplification of the subsequent quantization process, according to the description of Core Transform Design in the High Efficiency Video Coding (HEVC) Standard: the unity of norm of the transform matrix can simplify the subsequent quantization process, so the invention is based on HarSelecting a transformation matrix from the dcware Efficient integral Discrete Cosine Transform for Efficient Image/Video Compression by applying a weighting factor (beta)₁，β₂) Two different sets of values are assigned, and the elements of the two sets of transformation matrices are selected.

The selected first group of elements enables a transformation matrix to have good norm uniformity, and the matrix can simplify the quantization process after transformation and ensure the compression quality of the video; and the other group of elements dominates the hardware implementation, and the second group of matrixes can effectively reduce the hardware consumption. The values of the two groups of transformation matrixes are realized through a reconfigurable multiplier, and then the values and the other modules form the self-adaptive matrix multiplication circuit of the invention together.

In the whole process: defining the two selected sets of transformation matrices as d₀、d₁When the difference between the original signal and the predicted signal is obtained to obtain a residual signal, the variance is calculated and the selected matrix is adaptively determined according to the requirement. Such as: d is selected because the variance is greater than the set threshold, which indicates that the signal norm of the current input is poor in uniformity, and the video compression quality needs to be guaranteed preferentially at the moment₀(ii) a If the calculated variance is smaller than the set threshold, the signal norm of the current input is better in uniformity, and the compression quality can be avoided, so that d is selected₁To reduce hardware consumption. Therefore, the whole video conversion process is realized, the video compression quality is ensured, and the hardware cost is reduced.

The following is further described with reference to the accompanying drawings:

fig. 1 is a diagram illustrating an adaptive matrix multiplication circuit applied to HEVC according to the present invention. The method comprises the following steps: a group of reconfigurable multipliers, a variance module, a control module and a multiplexer. Wherein:

(1) the input matrix is sent into a variance module, and judgment is carried out in the variance module after the variance is solved: if the result is larger than the threshold value, outputting a high level, and if the result is smaller than the threshold value, outputting a low level;

(2) the output of the variance module is sent to the control end of the multiplexer, and the signal is used as a control signal to determine the output of the multiplexer;

(3) the input of the multiplexer is delivered to the control module, and the control module sends two groups of control signals con.bit.0 and con.bit.1 which respectively represent that different transformation matrixes are selected;

(4) and the input matrix is sent into the reconfigurable multiplier to carry out subsequent operations such as multiplication and accumulation and the like on the matrix elements selected by the controller.

Through the steps, the matrix suitable for the current input is determined according to the property of the input matrix, so that the aim of reducing the hardware cost while not reducing the video compression quality is fulfilled.

The final PSNR obtained using the present invention and the original method in HEVC, respectively, run in HM is shown in table 1.

TABLE 1 comparison of the results of the present invention with HM16.14

	Y-PSRN	U-PSNR	V-PSNR	YUV-PSNR
					Primitive method	32.1973	36.4743	37.6552	33.1302
Improved method	32.1888	36.4987	37.6880	33.1274
					Degree of improvement	-0.02640％	0.06690％	0.08711％	-0.00845％

As can be seen from table 1, the present invention does not degrade the PSNR, i.e., the present invention can guarantee the compression performance of the video.

Then, simulating on FPGA to obtain the parameters area, power and delay. Software used in the FPGA hardware simulation experiment is ISE Design Suite 14.7 and Vivado 2017, and the selected equipment model is Virtex series xc7vx980 t.

The parameters of each order are shown in tables 2 and 3.

As can be seen from tables 2 and 3, the present invention is slightly inferior at the low order, and is advantageous only in delay; but the situation of the high order is different, and the three aspects of area, power and delay are completely superior to the original method in HEVC.

Table 24 and 8 th order experimental results

Table 316 and 32 th order test results

Therefore, it can be said that the improvement is completely effective, and it optimizes the hardware to ensure the video quality, and the hardware consumption is reduced significantly, and this advantage is more prominent at high level.