阅读说明：本技术 数据存储设备及其操作方法 (Data storage device and method of operating the same ) 是由 韩吉博 金敬范 洪志满 申娜拉 于 2020-06-09 设计创作，主要内容包括：本公开的实施例涉及数据存储设备及其操作方法。一种数据存储设备可以包括存储装置和控制器。该存储装置包括多个存储器单元。控制器被配置为将主机的逻辑地址映射在存储装置的第一物理地址上,以相对于存储装置执行数据交换。控制器包括地址错误管理部件。地址错误管理部件被配置为基于第一物理地址来生成第一校验器。地址错误管理部件将第一校验器和第一物理地址传输到存储装置。当基于从存储装置传输的地址错误校验信息来在第一物理地址中发生地址错误时,地址错误管理部件被配置为将逻辑地址重新映射在第二物理地址上。(Embodiments of the present disclosure relate to data storage devices and methods of operating the same. A data storage device may include a storage and a controller. The memory device includes a plurality of memory cells. The controller is configured to map a logical address of the host on a first physical address of the storage device to perform a data exchange with respect to the storage device. The controller includes an address error management component. The address error management component is configured to generate a first checker based on the first physical address. The address error management component transmits the first checker and the first physical address to the storage device. When an address error occurs in a first physical address based on address error check information transmitted from the storage device, the address error management section is configured to remap the logical address on a second physical address.)

1. A data storage device, comprising:

a storage device comprising a plurality of memory cells; and

a controller configured to map a logical address of a host device onto a first physical address of the storage apparatus to perform data exchange with respect to the storage apparatus,

wherein the controller includes an address error management component, an

Wherein the address error management section generates a first checker based on the first physical address, transmits the first checker to the storage device together with the first physical address, and remaps the logical address onto a second physical address when an address error occurs in the first physical address based on address error check information transmitted from the storage device.

2. The data storage device of claim 1, wherein the first physical address is transferred a plurality of bits over a plurality of cycles, an

Wherein the address error management component is configured to include the first checker in unused bits of the first physical address and configured to transmit the first checker along an address transmission cycle.

3. The data storage apparatus of claim 1, wherein the controller transmits a status read command to the storage device after transmitting a write command and the first physical address including the first checker to the storage device, and

wherein the address error check information is transmitted as a response signal to the status read command.

4. The data storage device of claim 3, wherein the response signal includes bits of status information, an

Wherein the address error check information is included in at least a portion of the status information.

5. The data storage device of claim 1, wherein the first physical address is transferred a plurality of bits over a plurality of cycles,

wherein the address error management component performs a first logical operation on address bits in the same bit location in each of the cycles, an

Wherein the address error management component sets a parity bit generated from the first logical operation to the first checker.

6. The data storage apparatus of claim 1, wherein the controller is configured to store the first physical address and the changed address as log information by transmitting the changed address to the storage device via the address error.

7. A data storage device, comprising:

a controller configured to map a logical address of a host device onto a first physical address of a storage apparatus in response to a command processing request of the host device, and configured to transmit a first checker generated based on the first physical address, thereby transmitting the first checker to the storage apparatus together with the first physical address; and

the storage device includes a plurality of memory cells and is configured to compare the first checker with a second checker to generate address error check information,

wherein the second checker is generated based on the first physical address, an

Wherein the controller remaps the logical address onto a second physical address when an address error occurs in the first physical address, the address error being determined based on the address error checking information transmitted from the storage device.

8. The data storage device of claim 7, wherein the first physical address is transferred a plurality of bits over a plurality of cycles, an

Wherein the controller is configured to include the first checker in unused bits of the first physical address and configured to transmit the first checker along an address transmission cycle.

9. The data storage apparatus of claim 7, wherein the controller transmits a status read command to the storage device after transmitting a write command and the first physical address including the first checker to the storage device, and

wherein the address error check information is transmitted as a response signal to the status read command.

10. The data storage device of claim 9, wherein the response signal includes a plurality of bits of status information, an

Wherein the address error check information is included in at least a portion of the status information.

11. The data storage device of claim 7, wherein the first verifier and the second verifier are generated in the same manner.

12. The data storage device of claim 11, wherein the first physical address is transferred a plurality of bits over a plurality of cycles,

wherein the controller and the memory device perform a first logical operation on address bits in the same bit location in each of the cycles, an

Wherein the controller and the storage device generate the first checker and the second checker from the first logical operation.

13. The data storage apparatus of claim 7, wherein the storage device transmits an address changed by the address error to the controller, an

Wherein the controller is configured to store the first physical address and the changed address as log information.

14. A method of operating a data storage apparatus, the data storage apparatus comprising storage means and a controller configured to map a logical address of a host device onto a first physical address of the storage means to perform a data exchange with respect to the storage means, the method comprising:

generating, by the controller, a first checker based on the first physical address;

including the first checker in the first physical address and transmitting, by the controller, the first physical address to the storage device with the first checker;

generating, by the storage device, a second checker based on the first physical address received from the controller;

transmitting, by the storage device, address error checking information to the controller, the address error checking information being generated by comparing the first checker with the second checker;

identifying, by the controller, whether an address error is generated, the address error being determined based on the address error checking information; and

remapping, by the controller, the logical address onto a second physical address when the address error is generated.

15. The method of claim 14, wherein the first physical address is transferred a plurality of bits over a plurality of cycles, an

Wherein the controller is configured to include the first checker in unused bits of the first physical address and configured to transmit the first checker along an address transmission cycle.

16. The method of claim 14, further comprising:

transmitting, by the controller, a status read command to the storage device; and

transmitting, by the memory device, the address error checking information as a response signal to the status read command.

17. The method of claim 16, wherein the response signal includes a plurality of bits of status information, an

Wherein the address error check information is included in at least a portion of the status information.

18. The method of claim 14, wherein the first physical address is transferred a plurality of bits over a plurality of cycles, an

Wherein generating, by the controller, the first verifier comprises: in each of said cycles, a first logical operation is performed on address bits in the same bit position, an

Wherein parity bits generated from the first logical operation are set to the first checker by the controller.

19. The method of claim 14, wherein the first physical address is transferred a plurality of bits over a plurality of cycles,

wherein generating, by the controller, the second verifier comprises: in each of said cycles, a first logical operation is performed on address bits in the same bit position, an

Wherein parity bits generated from the first logical operation are set to the second checker by the controller.

20. The method of claim 14, further comprising:

transmitting, by the storage device, an address changed by the address error to the controller; and

storing, by the controller, the first physical address and the changed address as log information.

Technical Field

Various embodiments may relate generally to a semiconductor device, and more particularly, to a data storage device and a method of operating the same.

Background

The data storage device may be connected to a host device to perform data input/output operations based on requests from the host device. The data storage device may include various storage media configured to store data. For example, the storage medium may include a non-volatile memory device such as a flash memory device.

Fine pattern processing that increases the degree of integration of the data storage device and the complexity of hardware and software in the electronic device may cause the line width to be narrowed, thereby reducing the reliability of the memory device. In order to ensure high reliability of the memory device to cope with an increase in the number of errors of the memory device, it may be necessary to accurately detect errors generated when the memory device is operated.

Disclosure of Invention

In an example embodiment of the present disclosure, a data storage apparatus may include a storage device and a controller. The memory device may include a plurality of memory cells. The controller may be configured to map a logical address of the host onto a first physical address of the storage device to perform a data exchange with respect to the storage device. The controller may include an address error management component. The address error management component may be configured to generate a first checker based on the first physical address. The address error management component may transmit the first checker and the first physical address to the storage device. When an address error occurs in a first physical address based on address error check information transmitted from the storage device, the address error management section may be configured to remap the logical address onto a second physical address.

In an example embodiment of the present disclosure, a data storage apparatus may include a controller and a storage device. The controller may be configured to map a logical address of the host onto a first physical address of the storage device in response to a command processing request of the host. The controller may be configured to transmit a first checker generated based on the first physical address, thereby transmitting the first checker to the storage device together with the first physical address. The memory device may include a plurality of memory cells. The storage device may be configured to compare the first checker with the second checker to generate address error checking information. A second checker is generated based on the first physical address. The controller remaps the logical address to the second physical address when an address error occurs in the first physical address, the address error being determined based on address error check information transmitted from the memory device.

In an example embodiment of the present disclosure, a data storage device may include a storage and a controller according to a method of operating the data storage device. The controller may be configured to map a logical address of the host onto a first physical address of the storage device to perform a data exchange with respect to the storage device. The controller may generate a first checker based on the first physical address. The controller may include a first checker in the first physical address. The controller may transmit the first checker to the storage device along with the first physical address. The storage device may generate a second checker based on the first physical address received from the controller. The storage device may transmit address error checking information to the controller, the address error checking information may be generated by comparing the first checker with the second checker. The controller may identify whether an address error is generated, the address error being determined based on the address error checking information. When an address error is generated, the controller may remap the logical address to a second physical address.

Drawings

The above and other aspects, features and advantages of the presently disclosed subject matter will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which

FIG. 1 is a diagram illustrating a data storage device according to an example embodiment;

FIG. 2 is a diagram illustrating a memory controller according to an example embodiment;

FIG. 3 is a diagram illustrating an address error management component in accordance with an illustrative embodiment;

FIG. 4 is a diagram illustrating a non-volatile storage device in a data storage device, according to an example embodiment;

FIG. 5 is a flowchart illustrating a method of operation of a data storage device according to an example embodiment;

fig. 6 and 7 are views illustrating an internal operation of a storage device according to an example embodiment; and

fig. 8 is a view illustrating an addressing concept according to an example embodiment.

Fig. 9 is a diagram illustrating a data storage system according to an embodiment.

Fig. 10 and 11 are diagrams illustrating a data processing system according to an embodiment.

Fig. 12 is a diagram illustrating a network system including a data storage device according to an embodiment.

Detailed Description

Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The figures are schematic diagrams of various embodiments (and intermediate structures). As such, variations from the configurations and shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, the described embodiments should not be construed as limited to the particular configurations and shapes illustrated herein but are to include deviations in configurations and shapes that do not depart from the spirit and scope of the invention as defined by the appended claims.

The present invention is described herein with reference to cross-sectional and/or plan views of desirable embodiments of the invention. However, the embodiments of the present invention should not be construed as limiting the inventive concept. Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the invention.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present disclosure.

Further, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

FIG. 1 is a diagram illustrating a data storage device according to an example embodiment.

Referring to fig. 1, the data storage device 10 may include a controller 110 and a storage 120.

The controller 110 may be configured to control the storage 120 based on a request from a host device. For example, the controller 110 may control the storage 120 to program data in the storage 120 based on a write request from a host device. The controller 110 may provide the data in the storage 120 to the host device based on a read request from the host device. The controller 110 may include an address error management component 20.

The storage 120 may be configured to store and/or output data based on a request of the controller 110. Storage 120 may include volatile memory devices or non-volatile memory devices. For example, the storage 120 may be configured using a memory device. For example, the memory device may be electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), spin transfer torque magnetic RAM (STT-MRAM), or the like. The memory device 120 may include a plurality of dies Die 0 through Die n, a plurality of chips, a plurality of packages, and the like. Further, the memory device 120 may be operated as a single level cell configured to store one bit of data in one memory cell; or as a multi-level cell configured to store multiple bits of data in one memory cell.

In an example embodiment, the memory device 120 may include a cell array 121 and an error checking circuit 123. The cell array 121 may include a plurality of nonvolatile memory cells.

The cell array 121 may include a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines.

The controller 110 may transmit commands CMD, such as program commands, erase commands, read commands, etc., to the memory device 120. The storage 120 may process an operation corresponding to a command received from the controller 110. The controller 110 may request Status information (Status Req) after transmitting the command. In an example embodiment, a Status information request (Status Req) may be transmitted using a Status read command. The storage 120 may transmit the Status information (Status) in response to the Status information request (Status Req) so that the controller 110 may identify whether the command CMD is normally executed.

In an example embodiment, the controller 110 may generate a first checker with respect to an address of a memory cell to perform an operation corresponding to a command when the command is transmitted. The controller 110 may include a first checker in the address. The controller 110 may then transmit the address to the storage device 120 along with the verifier.

Error checking circuitry 123 of storage device 120 may be configured to generate the second checker from the address received by the command. Error checking circuitry 123 may generate the second checker in substantially the same manner as the first checker.

Error checking circuitry 123 may identify whether the second checker generated by error checking circuitry 123 is equal to the first checker transmitted from controller 110. Error checking circuitry 123 may include the identified result in Status information (Status). Error checking circuitry 123 may then transmit Status information (Status) to controller 110 along with the identified result. In an example embodiment, the Status information (Status) may be transmitted as a plurality of bits. A specific bit position of the plurality of bits may be assigned to the error check bit.

When the second checker is different from the first checker, the memory device 120 may recognize generation of an address error. The memory device 120 may stop command processing with respect to the corresponding address. Memory device 120 may transmit Status information (Status) including a predetermined logic level of the address check bit to controller 110.

The controller 110 may identify whether an address error is generated at an address transmitted with the command based on Status information (Status) received from the storage 120. When an address error is generated, the controller 110 may be configured to change a previous address to a new address to execute the command. The controller 110 may control the storage 120 to access the changed new address and process the command.

In an example embodiment, after transmitting the Status information (Status), the storage 120 may transmit the received address including the error to the controller 110. The controller 110 may store a previous address transmitted to the storage 120 and an address changed due to an error provided from the storage 120 as the debug information.

Accordingly, when transmitting a command to the memory device 120, the controller 110 may transmit an address including the first checker to the memory device 120. The storage device 120 may identify whether the address is normally received based on the address received from the controller 110, and the first and second checkers are generated by the storage device 120.

Since the error check result may be transmitted to the controller 110 together with the Status information (Status) of the storage 120, the controller 110 may re-designate an address and may request processing of the command again when an address error occurs.

Further, since the storage device 120 may provide the controller 110 with an address changed by error generation, the controller 110 may store the address of the initial access request and the changed address as the debug information. Accordingly, an error of an input/output path in the storage 120 may be identified by debugging information from an external device such as a test apparatus.

Fig. 2 is a diagram illustrating a memory controller according to an example embodiment.

Referring to fig. 2, the controller 110 may include a processor 111, a host interface 113, a ROM1151, a RAM1153, a memory interface 117, and an address error management part 20.

The processor 111 may provide the host interface 113, the RAM1153, and the memory interface 117 with various control information required to perform a read operation or a write operation of data with respect to the storage device 120. In an example embodiment, processor 111 may be operated based on firmware provided for various operations of data storage device 10. The processor 111 may perform functions of a Flash Translation Layer (FTL) including various functions for managing the storage device 120; and a function of detecting and correcting an error read from the storage device 120.

The FTL may have functions for providing garbage collection, address mapping, wear leveling, etc., functions for managing characteristics of each of the memory blocks in the storage 120.

The host interface 113 may receive commands and clock signals from a host device according to the control of the processor 111. The host interface 113 may be connected to a host device through a communication channel that controls input/output of data.

In particular, the host interface 113 may provide a physical connection between the host device and the data storage device 10. The host interface 113 may interface with the data storage device 10, the data storage device 10 corresponding to the bus format of the host device. The bus format of the host device may include at least one of standard interface protocols such as secure digital, Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), personal computer international memory card association (PCMCIA), Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), small form factor interconnect (PCI), PCI Express (PCI-E), universal flash memory (UFS), and the like.

The ROM1151 may store program code, such as firmware or software, required to operate the controller 110. The ROM1151 may also store code data used by the program code.

The RAM1153 may store data required to operate the controller 110 and data generated by the controller 110.

Memory interface 117 may provide a communication channel through which signals may be transmitted between controller 110 and storage 120. The memory interface 117 may transfer data temporarily stored in the buffer memory to the storage device 120 according to the control of the memory. The memory may transfer data read from the storage 120 to the buffer memory to temporarily store the data.

The address error management part 20 may extract a physical address of the storage 120 corresponding to a logical address of a host device access request in response to a command processing request of the host device. The address error management section 20 may generate a first checker from the extracted physical address. The address error management component 20 may process the command using a first checker in the address. Then, the address error management section 20 may transmit the address to the storage device 120 together with the first checker.

Address error management component 20 may identify Status information (Status) received from storage 120. When an address error is generated, address error management component 20 may remap the logical address of the host device access request onto a physical address. The address error management component 20 may transmit a command to access the remapped physical address. Herein, the address error management component 20 may generate a first checker with respect to the remapped physical address. The first checker may be transmitted with the address.

The address changed by the address error may be transmitted to the controller 110 so that the address error management part 20 may store the address of the initial access request and the changed address as address error information.

FIG. 3 is a diagram illustrating an address error management component according to an example embodiment.

Referring to fig. 3, the address error management part 20 may include a checker generator 210, an error determiner 220, and an error recorder 230.

Checker generator 210 may extract a physical address corresponding to the logical address of the access request to process the command. Checker generator 210 may then generate a first checker relative to the extracted physical address.

In an example embodiment, the physical address may be transferred between the controller 110 and the memory device 120 through the input/output pad in a plurality of cycles. The physical address may be transmitted in multiple bits in each of the cycles. Checker generator 210 may perform an XOR operation on address bits in the same bit position in each of the cycles to generate odd or even parity bits. The checker generator 210 may use the parity bits as a first checker. However, the present invention is not limited thereto.

The error determiner 220 may determine whether an address error is generated based on Status information (Status) transmitted from the storage 120. In an example embodiment, the Status information (Status) may be transmitted as a plurality of bits. Specific bit positions of the plurality of bits may be assigned to the address error check bits. When the address error check bit of the Status information (Status) has a specific logic level, the error determiner 220 may generate an address error.

When an address error is generated based on the determination of the error determiner 220, the error recorder 230 may store an address of an initial access request to process a command and an address transmitted from the storage device 120 as address error information. For example, address error information may be stored in the RAM 1153. However, the present invention is not limited thereto. For example, the address error information may be stored in an additional storage space of the address error management section 20.

FIG. 4 is a diagram illustrating a non-volatile memory device in a data storage device, according to an example embodiment.

Referring to fig. 4, the nonvolatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read/write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

The memory cell array 310 may include memory cells MC located at positions where word lines WL1 WLm and bit lines BL1 BLn intersect.

The memory cell array 310 may include a two-dimensional memory cell array or a three-dimensional memory cell array. A three-dimensional memory cell array may have a structure stacked in a direction substantially perpendicular to a planar surface of a semiconductor substrate including NAND strings, in which at least one memory cell may be vertically located above another memory cell. Alternatively, the structure of the three-dimensional memory cell array may have a horizontal orientation with a high degree of integration.

The row decoder 320 may be connected to the memory cell array 310 through word lines WL1 WLm. The row decoder 320 may operate based on the output of the control logic 360. The row decoder 320 may decode an address provided from an external device. The row decoder 320 may select and drive word lines WL1 WLm based on the decoding result. For example, the row decoder 320 may provide word line voltages supplied from the voltage generator 350 to the word lines WL1 WLm.

The data read/write block 330 may be connected to the memory cell array 310 through bit lines BL 1-BLn. The data read/write block 330 may include read/write circuits RW 1-RWn corresponding to bit lines BL1-BLn, respectively. The data read/write block 330 may operate based on the output of the control logic 360. The data read/write block 330 may operate as a write driver or a sense amplifier based on the operating mode. For example, the data read/write block 330 may function as a write driver configured to store data supplied from an external device in the memory cell array 310 in a write mode. Further, the data read/write block 330 may function as a sense amplifier configured to read data from the memory cell array 310 in a read mode.

Column decoder 340 may operate based on the output of control logic 360. The column decoder 340 may decode an address provided from an external device. The column decoder 340 may connect the read/write circuits RW1 to RWn of the data read/write block 330 corresponding to the bit lines BL1 to BLn to data input/output lines or data input/output buffers, respectively, based on the decoding result.

The voltage generator 350 may generate a voltage for a background operation of the nonvolatile memory device 300. The voltage generated by the voltage generator 350 may be applied to the memory cells of the memory cell array 310. For example, a program voltage generated in a program operation may be applied to a word line of a memory cell to perform the program operation. Further, an erase voltage generated in the erase operation may be applied to the well region of the memory cell to perform the erase operation. A read voltage generated in a read operation may be applied to a word line of the memory cell to perform the read operation.

The control logic 360 may control all operations of the non-volatile memory device 300 based on control signals from an external device. For example, the control logic 360 may control read, write, and erase operations of the non-volatile memory device 300.

Control logic 360 may include error checking circuitry 361.

The error checking circuit 361 may receive an address for processing a command from the controller 110. The error checking circuit 361 may generate a second checker based on the transferred address. The address transmitted from the controller 110 may include a first checker. The error checking circuit 361 may compare the second checker with the first checker in the address to generate address error checking information. When the second checker is different from the first checker, that is, an address error may be generated, the error checking circuit 361 may notify the control logic 360 of the address error to stop the processing of the command. The error checking circuit 361 may set an address error checking bit of the Status information (Status) to a specific logic level. The error checking circuit 361 may then transmit the address error check bits to the controller 110. In an example embodiment, when an address error is generated, the error checking circuit 361 may transmit the received address (i.e., the address changed by the error) to the controller 110. For example, the address error may be generated by a bit flip. However, the present invention is not limited thereto.

FIG. 5 is a flowchart illustrating a method of operating a data storage device according to an example embodiment.

Referring to fig. 5, when the host device requests a command process REQ to the controller 110 of the data storage device 10, the controller 110 may map a logical address requested by the host device to the physical address of the storage apparatus 120 in step S101.

In step S103, the controller 110 may generate a first checker based on the mapped physical address. In an example embodiment, a physical address may transmit multiple bits in multiple cycles. The controller 110 may perform an exclusive-or operation on address bits in the same bit position based on the period to generate odd or even parity bits. The controller 110 may use the parity bits as the first checker without being limited to the above. The first checker may be included in the physical address.

In step S105, the controller 110 may transmit an address including the first checker to the storage device 120 to request command processing.

In step S107, the storage device 120 may generate a second checker in response to the command and the address received from the controller 110. The second verifier may be generated in substantially the same manner as the first verifier. The result of the comparison between the second checker and the first checker may be generated as an error check bit.

When controller 110 requests Status information from memory device 120, memory device 120 may transmit Status information (Status) including an error check bit to controller 110.

In step S109, the controller 110 may identify whether an address error is generated based on an error check bit of the Status information (Status).

When an address error is not generated, the controller 110 may stand by for subsequent operations. In contrast, when an address error is generated, the controller 110 may remap a new physical address to transmit the command to the storage device 120 in step S111.

When an address error is generated, the storage device 120 may transmit an address changed based on the address error to the controller 110 in step S113. The controller 110 may store the initial address and the changed address as an error log. The error log may be output to an external device, such as a test device.

Fig. 6 and 7 are views illustrating an internal operation of a storage device according to an example embodiment.

Fig. 6 illustrates a program operation. Referring to fig. 6, after a first program command 80h is issued from the controller 110 to the memory device 120 during a program operation, an address Add and data Din may be sequentially input. The address Add may include a row address and a column address. When the second program command 10h is input to perform a program operation, the ready/busy signal may be transmitted at a low level. The data latched in the page buffer may be written to the memory cell during a busy period tPROG in which a program operation may be performed in the memory device 120. When the ready/busy signal changes to a high level after the busy period in which the program operation is completed, the controller 110 may transmit the status read command 70 h. The memory device 120 may transmit Status information (Status) to the controller 110 in response to the Status read command 70h to identify whether the program operation is normally performed.

The first checker may be transmitted to the storage device 120 along with the address Add. The storage 120 may generate a second checker from the address Add. The storage device 120 may compare the second verifier with the first verifier.

The storage device 120 may transmit Status information (Status) and a comparison result between the first checker and the second checker to the controller 110 by transmitting a Status read command from the controller 110 to the storage device 120.

As described above, the controller 110 may identify error check bits in the status information. When an address error is generated, the controller 110 may remap the physical address to request command processing again. Further, the controller 110 may store the address of the initial access request and the changed address as an error log by transmitting the address changed by the error generation.

Fig. 7 illustrates an erase operation. Referring to fig. 7, after an erase program command 60h is issued from the controller 110 to the memory device 120 in an erase operation, an address Add and data Din may be sequentially input. Since the erase operation may be performed by a block unit, the address Add may include a row address. A second erase command D0h may be input to perform an erase operation. The ready/busy signal may change to a low level. The data written in the memory unit may be erased during a busy period tBERS in which an erase operation may be performed in the storage 120. After the erase operation is completed, the ready/busy signal may change to a high level. Then, the controller 110 may transmit the status read command 70 h. The storage device 120 may transmit Status information Status to the controller 110 in response to the Status read command 70h to identify whether the erase operation is normally performed.

The first checker may be transmitted to the storage device 120 along with the address Add. The storage 120 may generate a second checker based on the address Add. The storage device 120 may compare the second verifier with the first verifier. The storage 120 may transmit Status information (Status) and a comparison result between the first checker and the second checker to the controller 110.

As described above, the controller 110 may identify error check bits in the status information. When an address error is generated, the controller 110 may remap the new physical address to request command processing again. Further, the controller 110 may store the address of the initial access request and the changed address as an error log.

Fig. 8 is a view illustrating an addressing concept according to an example embodiment.

Addresses may be transferred through input/output pads IO [0:7] in multiple cycles.

Referring to FIG. 8, the physical addresses may include column addresses A [13:0] and row addresses A [39:14 ]. The row addresses may include word line addresses A [23:14], plane addresses A [25:24], block addresses A [36:26], and logical storage area (LUN) addresses A [39:37 ].

In fig. 8, the physical address may be output for six cycles (not limited to a specific cycle). The physical address signal transmitted in one cycle may be about 8 bits. The number of address cycles used to address memory device 120 and the number of address bits transferred in one cycle may vary based on the size of memory device 120.

The unused bits of the address signal may be transmitted along with parity information (i.e., the first checker). The first checker may be a one-bit signal, not limited to being within a particular bit.

When the program resumes operation after a pause, an address error may be generated due to a bit flip. When a bit flip is generated at only one bit of the address, the address of an undesired location may be accessed, and thus the reliability of the data storage device may be low.

According to an example embodiment, the controller 1120 may transmit the address to the storage device 120 together with the first checker for checking the address error. Memory device 120 may generate a second checker from the received address to generate address error check bits. Memory device 120 may transmit status information including error check bits in response to a status information read request following command processing. When an address error is generated, the controller 110 may remap the physical address to request command processing again. The controller 110 may record address error information used in debugging.

Fig. 9 is a diagram illustrating a data storage system 1000 according to an embodiment.

Referring to fig. 9, the data storage 1000 may include a host device 1100 and a data storage device 1200. In one embodiment, the data storage device 1200 may be configured as a Solid State Drive (SSD).

The data storage device 1200 may include a controller 1210, a plurality of non-volatile memory devices 1220-0 to 1220-n, a buffer memory device 1230, a power supply 1240, a signal connector 1101, and a power connector 1103.

The controller 1210 may control the general operation of the data storage device 1200. The controller 1210 may include a host interface unit, a control unit, a random access memory used as a working memory, an Error Correction Code (ECC) unit, and a memory interface unit. In one embodiment, the controller 1210 may be configured as the controller 110, as shown in fig. 1 and 2.

The host device 1100 may exchange signals with the data storage device 1200 through the signal connector 1101. The signals may include commands, addresses, data, and the like.

The controller 1210 may analyze and process signals received from the host device 1100. The controller 1210 may control the operation of the internal functional blocks based on firmware or software to drive the data storage device 1200.

The buffer memory device 1230 may temporarily store data to be stored in at least one of the non-volatile memory devices 1220-0 through 1220-n. Further, the buffer memory device 1230 may temporarily store data read from at least one of the non-volatile memory devices 1220-0 through 1220-n. The data temporarily stored in the buffer memory device 1230 can be transferred to the host device 1100 or at least one of the non-volatile memory devices 1220-0 to 1220-n based on the controller 1210.

The nonvolatile memory devices 1220-0 to 1220-n may be used as storage media for the data storage device 1200. The non-volatile memory devices 1220-0 through 1220-n may be coupled to the controller 1210 through a plurality of channels CH0 through CHn. One or more non-volatile memory devices may be coupled to a channel. The non-volatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

The power supply 1240 may provide power input to the controller 1210, the non-volatile memory devices 1220-0 through 1220-n, and the buffer memory device 1230 of the data storage device 1200 through the power connector 1103. Power supply 1240 may include an auxiliary power supply. The auxiliary power supply may provide power to allow normal termination of the data storage device 1200 in the event of a sudden power interruption. The auxiliary power supply may include a large-capacity capacitor sufficient to store the required charge.

The signal connector 1101 may be configured as one or more of various types of connectors according to an interface scheme between the host device 1100 and the data storage device 1200.

The power connector 1103 may be configured as one or more of various types of connectors depending on the power scheme of the host device 1100.

Fig. 10 is a diagram illustrating a data processing system 3000 according to an embodiment. Referring to fig. 10, data processing system 3000 may include a host device 3100 and a memory system 3200.

The host device 3100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal functional blocks that perform the functions of the host device.

Host device 3100 can include connection terminals 3110 such as sockets, slots, or connectors. The memory system 3200 may be mated with the connection terminal 3110.

The memory system 3200 may be configured in the form of a board, such as a printed circuit board. Memory system 3200 may be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory devices 3231 and 3232, a Power Management Integrated Circuit (PMIC)3240, and a connection terminal 3250.

The controller 3210 may control the general operation of the memory system 3200. The controller 3210 may be configured in the same manner as the controller 110 shown in fig. 1 and 2.

Buffer memory device 3220 may temporarily store data to be stored in non-volatile memory devices 3231 and 3232. Further, the buffer memory device 3220 may temporarily store data read from the non-volatile memory devices 3231 and 3232. Data temporarily stored in the buffer memory device 3220 may be transferred to the host device 3100 or the nonvolatile memory devices 3231 and 3232 based on the controller 3210.

Nonvolatile memory devices 3231 and 3232 can be used as storage media for memory system 3200.

The PMIC 3240 may supply power input through the connection terminal 3250 to the internal circuit of the memory system 3200. The PMIC 3240 may manage power of the memory system 3200 based on the controller 3210.

Connection terminal 3250 may be coupled to connection terminal 3110 of host device 3100. Through connection terminal 3250, signals such as commands, addresses, data, and the like, as well as power, may be transferred between host device 3100 and memory system 3200. The connection terminal 3250 may be configured to one or more of various types depending on an interface scheme between the host device 3100 and the memory system 3200. Connection terminal 3250 may be disposed on one side of memory system 3200 as shown.

Fig. 11 is a diagram illustrating a data processing system 4000 according to an embodiment. Referring to FIG. 11, data processing system 4000 may include a host device 4100 and a memory system 4200.

The host device 4100 may be configured in the form of a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal functional blocks that perform the functions of the host device.

The memory system 4200 may be configured in the form of a surface mount type package. Memory system 4200 may be mounted to host device 4100 by solder balls 4250. Memory system 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

The controller 4210 may control the general operation of the memory system 4200. The controller 4210 may be configured in the same manner as the controller 110, as shown in fig. 1 and 2.

The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230. Further, the buffer memory device 4220 may temporarily store data read from the nonvolatile memory device 4230. The data temporarily stored in the buffer memory device 4220 may be transmitted to the host device 4100 or the nonvolatile memory device 4230 based on the controller 4210.

The nonvolatile memory device 4230 may be used as a storage medium of the memory system 4200.

Fig. 12 is a diagram illustrating a network system 5000 including a data storage device according to an embodiment. Referring to fig. 12, the network system 5000 may include a server system 5300, and a plurality of client systems 5410, 5420, and 5430 coupled via a network 5500.

The server system 5300 may service data in response to requests from multiple client systems 5410-5430. For example, server system 5300 may store data provided by a plurality of client systems 5410 through 5430. In another embodiment, server system 5300 may provide data to multiple client systems 5410-5430.

The server system 5300 may include a host device 5100 and a memory system 5200. Memory system 5200 may be configured as memory system 10 shown in fig. 1, data storage apparatus 1200 shown in fig. 9, memory system 3200 shown in fig. 10, or memory system 4200 shown in fig. 11.

The above-described embodiments of the present invention are intended to be illustrative, but not limiting, of the invention. Various alternatives and equivalents are possible. The present invention is not limited by the embodiments described herein. Nor is the invention limited to any particular type of semiconductor device. Other additions, subtractions or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.