阅读说明：本技术 一种SoPC芯片内嵌FPGA的验证模块 (Verification module of embedded FPGA of SoPC chip ) 是由 田泽 王世中 郭蒙 王宣明 刘承禹 于 2020-12-24 设计创作，主要内容包括：本发明涉及一种SoPC芯片内嵌FPGA的验证模块,本发明包括FPGA模型、总线接口模型和配置模型,总线接口模型模拟双核CPU0、CPU1行为完成与FPGA模型的互连通信,配置模型模拟CPU1行为完成FPGA的在线配置。本发明提出了一种高层次建模方法来构建FPGA的外围验证环境,更好更快的解决功能验证问题。(The invention relates to a verification module of an embedded FPGA (field programmable gate array) of an SoPC (System on chip) chip, which comprises an FPGA model, a bus interface model and a configuration model, wherein the bus interface model simulates the behaviors of a dual-core CPU0 and a CPU1 to complete the interconnection communication with the FPGA model, and the configuration model simulates the behavior of a CPU1 to complete the on-line configuration of the FPGA. The invention provides a high-level modeling method for constructing a peripheral verification environment of an FPGA (field programmable gate array), so that the problem of functional verification is solved better and faster.)

1. The utility model provides a verification module of embedded FPGA of SoPC chip which characterized in that: the verification module comprises an FPGA model, a bus interface model and a configuration model, wherein the bus interface model simulates the behaviors of a dual-core CPU0 and a CPU1 to complete interconnection communication with the FPGA model, and the configuration model simulates the behavior of a CPU1 to complete the on-line configuration of the FPGA.

2. The validation module of embedded FPGA of SoPC chip of claim 1, characterized in that: the bus interface model comprises an interconnection interface, a driver, a monitor, a generator and a random time sequence generator, wherein the random time sequence generator is connected with the generator through the driver, the generator is connected with the interconnection interface, and the interconnection interface is accessed into the monitor; wherein:

the interconnection interface is connected with the FPGA model, the arbitration of the dual-core CPU0 and CPU1 bus interfaces and the arbitration of accessing the interconnection interface respectively is realized inside the FPGA model, and the interface supports various time sequences: single beat, burst operation, etc., constrained by a random timing generator to generate the timing pattern;

the driver completes the interaction of the random time sequence generator and the interconnection interface to form the task of generating various time sequences;

the generator is mainly used for arbitrating various random time sequences and transmitting the generated result to the driver;

the monitor is used for collecting data returned by the read operation interface.

3. The validation module of embedded FPGA of SoPC chip of claim 2, characterized in that: the interface time sequence period number in the interconnection interface can be programmed, and the interconnection interface comprises signals of a chip selection cs _ n, a read-write enabling signal rw, a read-write data bus, an address bus and a return ack response signal.

4. The validation module of embedded FPGA of SoPC chip of claim 2, characterized in that: the bus interface model can be realized by adopting SystemC, SystemVerilog or UVM.

5. The validation module of SoPC chip embedded FPGA according to any one of claims 1 to 4, characterized in that: the configuration model comprises a configuration interface, a configuration driver, a configuration generator and a configuration mode random generator, wherein the configuration mode random generator is connected with the configuration driver through the configuration generator, and the configuration driver is connected with the configuration interface; wherein:

the configuration interface is used for connecting the FPGA model and converting the CPU1 bus interface operation into the interface operation conforming to the configuration FPGA;

the configuration pattern random generator is used for generating constrained models in different patterns;

the configuration generator is used for transmitting the configuration mode of the configuration mode random generator to the configuration interface through the configuration driver.

6. The validation module of embedded FPGA of SoPC chip of claim 5, characterized in that: the configuration driver implements 6 configuration modes, a master-string slave-string mode, a master-parallel 8-bit mode, a slave-parallel 32-bit mode, and a JTAG scan chain mode.

7. The validation module of embedded FPGA of SoPC chip of claim 5, characterized in that: the configuration model can be realized by SystemC, SystemVerilog or UVM.

Technical Field

The invention relates to the field of integrated circuit design, in particular to a verification module of an embedded FPGA (field programmable gate array) of an SoPC (System on chip).

Background

The method is characterized in that a domestic FPGA is integrated on a multi-core SoC chip based on a domestic process, in the engineering, the domestic FPGA is in a research stage at present in China, an interconnection and configuration interface needs to be designed for the multi-core SoC chip integrated FPGA, the function verification based on the design is divided into verification based on an FPGA prototype platform and verification based on a virtual prototype platform, a domestic FPGA sample wafer and other FPGAs or chips are adopted to form a verification environment of configuration and a data path for performing the FPGA prototype verification, and the embedded FPGA virtual verification needs to construct a peripheral design model. And the problem of difficulty in virtual verification in embedded FPGA verification is solved.

Disclosure of Invention

The invention provides a verification method for an embedded FPGA of an SoPC chip to solve the technical problems in the background art, and solves the problem of difficult virtual verification in the embedded FPGA verification.

The technical solution of the invention is as follows: the invention provides a verification module of an embedded FPGA of a SoPC chip, which is characterized in that: the verification module comprises an FPGA model, a bus interface model and a configuration model, wherein the bus interface model simulates the behaviors of a dual-core CPU0 and a CPU1 to complete the interconnection communication with the FPGA model, and the configuration model simulates the behavior of a CPU1 to complete the on-line configuration of the FPGA.

Preferably, the bus interface model comprises an interconnection interface, a driver, a monitor, a generator and a random timing generator, wherein the random timing generator is connected with the generator through the driver, the generator is connected with the interconnection interface, and the interconnection interface is connected with the monitor; wherein:

the interconnection interface is connected with the FPGA model, the arbitration that the dual-core CPU0 and CPU1 bus interfaces and the respective access interconnection interface are realized inside, and the interface supports various time sequences: single beat (synchronous, asynchronous), burst (burst) operation, etc., constrained by a random timing generator to generate the timing pattern;

the driver completes the interaction between the random time sequence generator and the interconnection interface to form the task of generating various time sequences;

the generator is mainly used for arbitrating various random time sequences and transmitting the generated result to the driver;

the monitor is used for collecting data returned by the read operation interface and the like.

Preferably, the number of interface timing cycles in the interconnection interface is programmable, and the interface timing cycles include signals including a chip select cs _ n, a read/write enable signal rw, a read/write data bus, an address bus, and a return ack response signal.

Preferably, the bus interface model is implemented using SystemC, systemveilog, or UVM (universal verification methodology).

Preferably, the configuration model comprises a configuration interface, a configuration driver, a configuration generator and a configuration pattern random generator, wherein the configuration pattern random generator is connected with the configuration driver through the configuration generator, and the configuration driver is connected with the configuration interface; wherein:

the configuration interface is used for connecting the FPGA model and converting the CPU1 bus interface operation into the interface operation conforming to the configuration FPGA;

configuring a pattern random generator for generating constrained models in different patterns;

the configuration generator is used for transmitting the configuration mode of the configuration mode random generator to the configuration interface through the configuration driver.

Preferably, the configuration driver implements 6 configuration modes, Master Serial (Master Serial) slave string mode, Master parallel 8-bit mode, slave parallel 32-bit mode and JTAG scan chain mode.

Preferably, the configuration model can be implemented using SystemC, SystemVerilog, or UVM (Universal verification methodology).

The verification module of the SoPC chip embedded with the FPGA provides a high-level modeling method to construct a peripheral verification environment of the FPGA, and better and faster solves the problem of functional verification. Therefore, the invention has the following advantages:

1. an FPGA interface model is constructed by adopting a high-level modeling method and used for simulating FPGA interconnection interface design, and a specific interconnection circuit can be quickly realized based on the model.

2. The configuration model is constructed by adopting high-level modeling, and the problem that the system level verification of the FPGA integrated in the SoC chip is difficult is solved.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a block diagram of the architecture of the interface model of the present invention;

FIG. 3 is a block diagram of the configuration model of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail with reference to the accompanying drawings and specific embodiments.

Referring to fig. 1, the verification module according to the embodiment of the present invention includes a bus interface model, a configuration model, and an FPGA model, where the bus interface model simulates a dual core (CPU0, CPU1) to complete interconnection communication with the FPGA model, and the configuration model simulates a CPU1 bus interface operation to complete injection of configuration stream data of the FPGA model.

For an FPGA model integrated on a dual-core SoC, the third-party model is a bus interface model interacting with a CPU, as shown in fig. 1, where the bus interface model supports access of the CPU0 and the CPU1 in a simulation manner, clock domains of the CPU0 and the CPU1 are often different, in order to ensure that access of a CPU bus on one side of the FPGA is often used, the bus interface model often adopts a clock domain thereof, a time sequence of the clock domain interface is programmable, processing across the clock domain is often required for use on the other side, due to the fact that the FPGA is a volatile device, reconfiguration is often required when power is turned on, a special configuration process is required, and the configuration model simulates a configuration process of the FPGA.

Referring to fig. 2, the bus interface model of the present invention includes an interconnection interface, a driver, a monitor, an arbiter and a random timing generator, the random timing generator is connected with the generator through the driver, the generator is connected with the interconnection interface, the interconnection interface is connected to the monitor, wherein the interconnection interface is connected with an FPGA model, the inside realizes the splitting arbitration of the CPU0 and CPU1 bus interfaces, the interface supports the constraint generation of multiple timings by the random timing generator, each timing mode has single beat (synchronous, asynchronous) and burst (burst) operations, wherein the interface timing cycle number can be programmed, including the signal having chip select cs _ n, the read/write enable signal rw, the read/write data bus, the address bus, the return ack answer signal, etc., the driver completes the interaction of the random timing generator and the interconnection interface to form tasks of generating various timings, the monitor is used to collect the data returned by the read operation interface, etc., the generator is mainly used for arbitrating various random time sequences and transmitting the generated result to the driver.

The bus interface model can be implemented by using SystemC, systemveilog, or UVM (universal verification methodology).

Referring to fig. 3, the configuration model of the present invention includes a configuration interface, a configuration driver, a configuration generator and a configuration pattern random generator, wherein the configuration pattern random generator is connected to the configuration driver through the configuration generator, and the configuration driver is connected to the configuration interface; the configuration interface is connected with the FPGA model and simulates the operation of a bus interface of the CPU 1; the configuration mode random generator is used for generating constrained models in different modes, the configuration generator is used for transmitting the configuration modes of the configuration mode random generator to a configuration interface through a configuration driver, the configuration driver realizes 6 configuration modes, a Master string (Master Serial) slave string mode, a Master parallel 8-bit mode, a slave parallel 32-bit mode and a JTAG scan chain mode, each mode can call a certain sequence to load data into an FPGA according to the FPGA interface configuration time sequence, the FPGA type matching, the CRC checking correctness and the like are required to be detected in the process, and the configuration models can be realized by adopting SystemC, SystemVerilog or UVM (universal verification methodology).

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.