阅读说明：本技术 集成电路多情景时序收敛分析方法、装置、介质及设备 (Integrated circuit multi-scenario timing sequence convergence analysis method, device, medium and equipment ) 是由 葛颖峰 李孙华 徐祎喆 朱勇 于 2020-12-21 设计创作，主要内容包括：本发明公开了一种集成电路多情景时序收敛分析方法、装置、存储介质及设备,属于集成电路设计技术领域。该方法包括：利用集成电路的至少一种工作情景的提纲报告以及细节报告,并根据至少一种工作情景的提纲报告对集成电路设计的收敛情况进行分析判断；根据收敛情况的分析判断结果对至少一种工作情景的细节报告进行分析得到集成电路的修复意见；根据修复意见对集成电路进行修复；其中提纲报告包括产生时序违例的时序路径的相关信息。本发明的应用根据提纲报告以及细节报告对至少一种工作情景下的集成电路进行分析,根据分析结果给出修复意见,并对集成电路进行修复,在不依赖EDA工具的摘要报告的前提下,快速发现时序问题并解决时序问题。(The invention discloses a multi-scenario time sequence convergence analysis method, a multi-scenario time sequence convergence analysis device, a storage medium and integrated circuit equipment, and belongs to the technical field of integrated circuit design. The method comprises the following steps: analyzing and judging the convergence condition of the integrated circuit design by utilizing the outline report and the detail report of at least one working scene of the integrated circuit according to the outline report of at least one working scene; analyzing the detail report of at least one working scene according to the analysis and judgment result of the convergence condition to obtain the repair suggestion of the integrated circuit; repairing the integrated circuit according to the repair suggestion; wherein the synopsis report includes information about the timing path that produced the timing violation. The application of the invention analyzes the integrated circuit under at least one working scene according to the outline report and the detail report, gives a repair suggestion according to the analysis result, repairs the integrated circuit, and quickly finds the timing problem and solves the timing problem on the premise of not depending on the summary report of the EDA tool.)

1. An analysis method for integrated circuit multi-scenario timing closure, comprising:

analyzing and judging the convergence condition of the integrated circuit design by utilizing the outline report and the detail report of at least one working scene of the integrated circuit according to the outline report of the at least one working scene;

analyzing the detail report of the at least one working scene according to the analysis and judgment result of the convergence condition to obtain a repair opinion of the integrated circuit; and the number of the first and second groups,

repairing the integrated circuit with the EDA tool according to the repair opinion;

wherein the synopsis report includes information about a timing path that produced the timing violation.

2. The method as claimed in claim 1, wherein the analyzing the detail report of the at least one operation scenario according to the analysis result of the convergence situation to obtain the repair opinion of the integrated circuit comprises,

and when the analysis and judgment result of the convergence condition is non-convergence, analyzing the detail report of the at least one working scene to obtain a repair suggestion of the integrated circuit.

3. The method as claimed in claim 2, wherein the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit when the analysis result of the convergence condition is not convergence comprises,

analyzing the detail report of the at least one working scenario with the EDA tool to obtain an automatic repair opinion of the integrated circuit,

and/or manually analyzing the detail report of the at least one working scenario to obtain a manual repair opinion of the integrated circuit.

4. The method of claim 3, wherein the step of manually analyzing the detail report of the at least one operation scenario to obtain an opinion of manual repair of the integrated circuit comprises,

when the EDA tool cannot repair the integrated circuit by increasing or decreasing or adjusting devices, manually analyzing the detail report of the at least one working scene to obtain the manual repair opinion.

5. The method as claimed in claim 3, wherein the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the IC when the analysis result of the convergence condition is not convergence comprises,

and combining the automatic repair opinions and the manual repair opinions to obtain the repair opinions of the integrated circuit.

6. The method of integrated circuit multi-scenario timing closure analysis of claim 1, wherein the process of repairing the integrated circuit with the EDA tool according to the repair opinion comprises,

performing simulated repair on the integrated circuit by using the EDA tool according to the repair suggestion to obtain a simulated repair integrated circuit;

evaluating the repairing effect of the analog repairing circuit;

and when the evaluation result of the repairing effect of the simulation repairing circuit is effective, actually repairing the integrated circuit by utilizing the EDA tool according to the repairing suggestion.

7. The integrated circuit multi-scenario timing closure analysis method of claim 6, wherein the process of evaluating the repair effect of the analog repair circuit comprises,

analyzing and judging the design convergence condition of the analog integrated circuit;

when the analysis and judgment result of the design convergence condition of the analog integrated circuit is convergence, the evaluation result of the repair effect of the analog repair circuit is valid.

8. An apparatus for integrated circuit multi-scene timing closure analysis, comprising:

a module for analyzing and judging the convergence condition of the integrated circuit design by using the outline report and the detail report of at least one working scene of the integrated circuit according to the outline report of the at least one working scene;

a module for analyzing the detail report of the at least one working scenario according to the analysis and judgment result of the convergence condition to obtain a repair opinion of the integrated circuit; and the number of the first and second groups,

means for repairing the integrated circuit with the EDA tool according to the repair opinion;

wherein the synopsis report includes information about a timing path that produced the timing violation.

9. A computer-readable storage medium storing computer instructions, wherein the computer instructions are operable to perform the integrated circuit multi-scenario timing closure analysis method of any of claims 1-7.

10. A computer device comprising a processor and a memory, the memory having stored thereon computer instructions, wherein the processor operates the computer instructions to perform the integrated circuit multi-scenario timing closure analysis method of any of claims 1-7.

Technical Field

The present application relates to the field of integrated circuit design technologies, and in particular, to a method, an apparatus, a storage medium, and a device for integrated circuit multi-scenario timing convergence analysis.

Background

Since the chip is produced, it is often necessary to work in different environments, such as desert or ice and snow, to make the integrated circuit work. This results in the need for the integrated circuit to accommodate different temperature environments. Such as in a general office environment, or playing games, requires that the integrated circuit operate at different speeds, or in what is called different modes of operation. Moreover, it is more troublesome that each work scenario needs to be able to work in desert or ice and snow, and the number of work scenarios is the product of all work modes and all engineering environments, so that the work scenarios to be analyzed are many. For complex integrated circuit SOC designs below deep sub-micron, at least tens to hundreds of operating scenarios need to be analyzed, with each scenario analysis generating a large number of reports. The manual reading of these reports and the analysis is very labor intensive.

In the approving stage of chip design, the GDS file is output to a wafer factory for processing after checking whether the design of the whole chip can really meet the original design purpose of the user. This is the last pass and insurance for the entire chip design process. As is well known, chip design is a long-period high-risk technical field, and once an error occurs, not only a huge tape-out failure cost is faced, but also the whole product movement is delayed by half a year before being put on the market. This final inspection stage is particularly important. One of the most important, and often most workload, tasks is timing closure. The timing convergence is not completed at once, and a loop of checking, correcting, re-checking, and re-correcting is required. While the EDA tool will also generate a report of the corresponding summary nature for each scene, it is quite a bit more to look directly at detailed reports if simply looking at the summary provided by the EDA tool is actually not enough to obtain much critical information.

Although EDA tools can help us analyze the timing of the entire SOC chip under various operating scenarios. But analyzing these results is still a time consuming and laborious process. How to rapidly analyze and count the states of the integrated circuit in such multiple modes and scenarios, and finding out the problem and solving the timing problem very conveniently is a technical problem that needs to be solved.

Disclosure of Invention

The invention provides an integrated circuit multi-scenario timing sequence convergence analysis method, a device, a storage medium and equipment, which are used for analyzing an integrated circuit under at least one working scenario according to a synopsis report and a detail report, giving a repair suggestion according to an analysis result, repairing the integrated circuit, and rapidly finding a timing sequence problem and solving the timing sequence problem on the premise of not depending on the synopsis report of an EDA tool.

In order to solve the above problems, the present invention adopts a technical solution that: the method for analyzing the multi-scene timing convergence of the integrated circuit comprises the following steps: analyzing and judging the convergence condition of the integrated circuit design by utilizing the outline report and the detail report of at least one working scene of the integrated circuit according to the outline report of at least one working scene; analyzing the detail report of at least one working scene according to the analysis and judgment result of the convergence condition to obtain the repair suggestion of the integrated circuit; repairing the integrated circuit by using an EDA tool according to the repairing suggestion; wherein the synopsis report includes information about the timing path that produced the timing violation.

The invention adopts another technical scheme that: provided is an integrated circuit multi-scenario timing closure analysis device, which comprises: a module for analyzing and judging the convergence condition of the integrated circuit design by using the outline report and the detail report of at least one working scene of the integrated circuit and according to the outline report of at least one working scene; a module for analyzing the detail report of at least one working scene according to the analysis and judgment result of the convergence condition to obtain the repair suggestion of the integrated circuit; and means for repairing the integrated circuit with the EDA tool according to the repair opinions; wherein the synopsis report includes information about the timing path that produced the timing violation.

In another aspect of the present application, a computer-readable storage medium is provided, which stores computer instructions, wherein the computer instructions are operable to perform a method for integrated circuit multi-scenario timing closure analysis in an aspect.

The beneficial effect that this application technical scheme can reach is: the method analyzes the integrated circuit under at least one working scene according to the outline report and the detail report, gives repair opinions according to the analysis result, repairs the integrated circuit, and quickly finds and solves the timing sequence problem on the premise of not depending on the abstract report of the EDA tool.

Drawings

FIG. 1 is a diagram illustrating an embodiment of a multi-scenario timing closure analysis method of an integrated circuit according to the present invention;

FIG. 2 is a diagram of another embodiment of an apparatus for integrated circuit multi-scenario timing closure analysis according to the present invention.

Detailed Description

The following detailed description of the preferred embodiments of the present invention, taken in conjunction with the accompanying drawings, will make the advantages and features of the invention easier to understand by those skilled in the art, and thus will clearly and clearly define the scope of the invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Fig. 1 is a schematic diagram illustrating an embodiment of a multi-scenario timing closure analysis method of an integrated circuit according to the present invention.

In this embodiment, the method for analyzing multi-scenario timing convergence of an integrated circuit mainly includes: the process S101: analyzing and judging the convergence condition of the integrated circuit design by utilizing the outline report and the detail report of at least one working scene of the integrated circuit according to the outline report of at least one working scene; the process S102: analyzing the detail report of at least one working scene according to the analysis and judgment result of the convergence condition to obtain the repair suggestion of the integrated circuit; the process S103: repairing the integrated circuit by using an EDA tool according to the repair suggestion; wherein the synopsis report includes information about the timing path that produced the timing violation.

In the specific embodiment shown in fig. 1, the method for analyzing convergence of multiple scenarios and timing sequences of an integrated circuit according to the present application includes a process S101, which utilizes a synopsis report and a detail report of at least one operating scenario of the integrated circuit, and analyzes and determines a convergence condition of an integrated circuit design according to the synopsis report of at least one operating scenario. The process does not depend on the abstract report of the EDA tool, and the convergence condition of the integrated circuit design is analyzed and judged through the outline report so as to find the timing sequence problem quickly.

In a specific example of the present invention, the process of using the synopsis report and the detail report of the at least one operation scenario of the integrated circuit includes, according to the detail report of the at least one operation scenario of the integrated circuit, using the script to extract the required information in the detail report to generate the synopsis report, where the synopsis report includes the related information of the timing path that generated the timing violation.

In a specific example of the present invention, the above-mentioned process of extracting required information from the detail report to generate the synopsis report according to the detail report of at least one operation scenario of the integrated circuit includes, for example, in an integrated circuit, a device in a complete signal transmission path of a clock signal from the first register to the sixth register includes: the register comprises a first register, a first logic gate, a second register, a second logic gate, a third register, a fourth logic gate and a fourth register. For example, the clock signal passes through the sequential path from the second register to the third logic gate through the second logic gate and then to the third register, and when the outline report is generated, the outline report includes the logic of the second logic gate and the third logic gate; the number of logic devices in the timing path from the second register to the third register; a total number of device delays in a timing path from the second register to the third register; the total delay of the device-to-device connection lines from the second register to the third register; a clock type driving the second register and the third register; whether two clocks driven by the second register and the third register are balanced or not is judged; the front stage of the second register comprises whether a time sequence path from the first register to the second register has an optimization space; the later stage of the third register includes whether the timing path from the third register to the fourth register has more space for optimization.

In an embodiment of the present invention, the analyzing and determining the convergence of the integrated circuit design according to the outline report of at least one operation scenario includes, for example, a clock signal from one register, and a clock signal received by another register after passing through the combinational logic. The transfer speed of the clock signal cannot be too slow, and if it is too slow, the setup time (setup time) requirement of the clock signal cannot be met. The transfer speed of the clock signal cannot be too fast, and if it is too fast, the hold time (hold time) requirement of the clock signal cannot be met. The transfer time of the clock signal must be constrained to be within a particular time range. The specific value of this constraint depends on the state of the clock signal and the device requirements for setup time and hold time. Setting the clock period of the integrated circuit to be P and the clock to be an ideal square wave, sending the ideal square wave to a first register FF₁And to a second register FF₂There is no time difference in the clocks. The setup time requirement of the clock signal of the register is T_setupThe hold time requirement of the clock signal is T_hold. Clock signal slave FF₁Is passed to FF₂The time delay of (a) must satisfy:

T_hold≤Delay≤P-T_setup

in the embodiment shown in fig. 1, the method for analyzing multi-scenario timing closure of an integrated circuit according to the present application includes a process S102, where a detail report of at least one operation scenario is analyzed according to an analysis result of a closure condition to obtain a repair opinion of the integrated circuit. This process yields a repair opinion of the integrated circuit to facilitate further repair of the integrated circuit.

In an embodiment of the invention, the analyzing the detail report of the at least one operation scenario according to the analysis and determination result of the convergence condition to obtain the repair opinion of the integrated circuit includes considering that the integrated circuit does not need to be repaired when the analysis and determination result of the convergence condition is convergence, and generating a brief report for the integrated circuit by the EDA tool.

In an embodiment of the invention, the analyzing the detail report of the at least one operation scenario according to the analysis and determination result of the convergence condition to obtain the repair opinion of the integrated circuit includes analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit when the analysis and determination result of the convergence condition is non-convergence. This process yields a repair opinion of the integrated circuit to facilitate further repair of the integrated circuit.

In an embodiment of the invention, when the analysis result of the convergence condition is non-convergence, the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit includes analyzing the detail report of the at least one operation scenario by using an EDA tool to obtain an automatic repair opinion of the integrated circuit, and/or manually analyzing the detail report of the at least one operation scenario to obtain a manual repair opinion of the integrated circuit. The process obtains automatic repair opinions and/or manual repair opinions of the integrated circuit so as to further repair the integrated circuit.

In an embodiment of the invention, the step of manually analyzing the detail report of the at least one working scenario to obtain the manual repair opinion of the integrated circuit includes, when the EDA tool cannot repair the integrated circuit by increasing or decreasing or adjusting the device, manually analyzing the detail report of the at least one working scenario to obtain the manual repair opinion, and the process uses the condition that the EDA tool cannot judge whether to perform manual analysis by increasing or decreasing or adjusting the device, so as to avoid manual intervention analysis as much as possible.

In one embodiment of the present invention, the step of manually analyzing the detail report of the at least one operation scenario to obtain a manual repair suggestion when the EDA tool is unable to repair the integrated circuit by adding or dropping or adjusting the device comprises giving an automatic repair suggestion if the integrated circuit is found to have an optimization capability by replacing the device or adding or dropping the device, and giving a warning to require manual intervention analysis and giving a manual repair suggestion if the integrated circuit is found to have no possibility of repair by adding or dropping or adjusting the device.

In an embodiment of the invention, when the analysis result of the convergence status is non-convergence, the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit includes merging the automatic repair opinion and the manual repair opinion to obtain the repair opinion of the integrated circuit, which facilitates further repairing the integrated circuit.

In the embodiment shown in fig. 1, the method for analyzing multi-scenario timing closure of an integrated circuit of the present application includes a process S103 of repairing the integrated circuit by using an EDA tool according to the repair suggestion. The integrated circuit is repaired in the process, so that the integrated circuit reaches the design convergence requirement after being repaired.

In an embodiment of the invention, the repairing the integrated circuit by using the EDA tool according to the repair suggestion includes performing simulated repair on the integrated circuit by using the EDA tool according to the repair suggestion to obtain a simulated repaired integrated circuit; evaluating the repairing effect of the analog repairing circuit; and when the evaluation result of the repairing effect of the simulation repairing circuit is effective, actually repairing the integrated circuit by using the EDA tool according to the repairing suggestion. The process carries out simulation repair, repair effect evaluation and actual repair on the integrated circuit so as to further obtain an integrated circuit with actual design convergence.

In a specific embodiment of the present invention, the process of evaluating the repair effect of the analog repair circuit includes analyzing and judging the design convergence condition of the analog integrated circuit; and when the analysis and judgment result of the design convergence condition of the analog integrated circuit is convergence, the evaluation result of the repair effect of the analog repair circuit is effective. Whether the next restoration needs to be carried out or not is effectively judged according to the evaluation result in the process, so that the problem that the later-stage workload is increased due to the fact that the time sequence convergence requirement is not met after the initial restoration is solved.

FIG. 2 is a schematic diagram of another embodiment of an apparatus for integrated circuit multi-scenario timing closure analysis according to the present invention.

In this embodiment, the apparatus for analyzing timing convergence of multiple scenarios in an integrated circuit mainly comprises: a module for analyzing and judging the convergence condition of the integrated circuit design by using the outline report and the detail report of at least one working scene of the integrated circuit and according to the outline report of at least one working scene; a module for analyzing the detail report of at least one working scene according to the analysis and judgment result of the convergence condition to obtain the repair suggestion of the integrated circuit; and means for repairing the integrated circuit with the EDA tool according to the repair opinions; wherein the synopsis report includes information about the timing path that produced the timing violation.

In an embodiment of the invention, the module for analyzing the detail report of the at least one operation scenario according to the analysis and determination result of the convergence condition to obtain the repair opinion of the integrated circuit, includes that, when the analysis and determination result of the convergence condition is non-convergence, the detail report of the at least one operation scenario is analyzed to obtain the repair opinion of the integrated circuit. This process yields a repair opinion of the integrated circuit to facilitate further repair of the integrated circuit.

In an embodiment of the invention, when the analysis result of the convergence condition is non-convergence, the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit includes analyzing the detail report of the at least one operation scenario by using an EDA tool to obtain an automatic repair opinion of the integrated circuit, and/or manually analyzing the detail report of the at least one operation scenario to obtain a manual repair opinion of the integrated circuit. The process obtains automatic repair opinions and/or manual repair opinions of the integrated circuit so as to further repair the integrated circuit.

In an embodiment of the invention, the step of manually analyzing the detail report of the at least one working scenario to obtain the manual repair opinion of the integrated circuit includes, when the EDA tool cannot repair the integrated circuit by increasing or decreasing or adjusting the device, manually analyzing the detail report of the at least one working scenario to obtain the manual repair opinion, and the process uses the condition that the EDA tool cannot judge whether to perform manual analysis by increasing or decreasing or adjusting the device, so as to avoid manual intervention analysis as much as possible.

In an embodiment of the invention, the analyzing the detail report of the at least one operation scenario to obtain the repair opinion of the integrated circuit when the analysis result of the convergence condition is non-convergence further includes merging the automatic repair opinion and the manual repair opinion to obtain the repair opinion of the integrated circuit, so as to further repair the integrated circuit.

In an embodiment of the invention, the module for repairing the integrated circuit by using the EDA tool according to the repair suggestion includes performing simulated repair on the integrated circuit by using the EDA tool according to the repair suggestion to obtain a simulated repaired integrated circuit; evaluating the repairing effect of the analog repairing circuit; and when the evaluation result of the repairing effect of the simulation repairing circuit is effective, actually repairing the integrated circuit by using the EDA tool according to the repairing suggestion. The process carries out simulation repair, repair effect evaluation and actual repair on the integrated circuit so as to further obtain an integrated circuit with actual design convergence.

In a specific embodiment of the present invention, the process of evaluating the repair effect of the analog repair circuit includes analyzing and judging the design convergence condition of the analog integrated circuit; and when the analysis and judgment result of the design convergence condition of the analog integrated circuit is convergence, the evaluation result of the repair effect of the analog repair circuit is effective. Whether the next restoration needs to be carried out or not is effectively judged according to the evaluation result in the process, so that the problem that the later-stage workload is increased due to the fact that the time sequence convergence requirement is not met after the initial restoration is solved.

By applying the integrated circuit multi-scenario timing sequence convergence analysis device, the integrated circuit under at least one working scenario is analyzed according to the outline report and the detail report, the repair suggestion is given according to the analysis result, the integrated circuit is repaired, and the timing sequence problem is quickly found and solved on the premise of not depending on the summary report of an EDA tool.

The multi-scenario timing convergence analysis apparatus for an integrated circuit provided by the present invention can be used to implement the multi-scenario timing convergence analysis method for an integrated circuit described in any of the above embodiments, and the implementation principle and technical effect are similar, which are not described herein again.

In a specific embodiment of the present application, a computer-readable storage medium stores computer instructions, wherein the computer instructions are operable to perform the integrated circuit multi-scenario timing closure analysis method described in any of the embodiments. Wherein the storage medium may be directly in hardware, in a software module executed by a processor, or in a combination of the two.

A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.

The Processor may be a Central Processing Unit (CPU), other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one embodiment of the present application, a computer device includes a processor and a memory, the memory storing computer instructions, wherein: the processor operates the computer instructions to perform the integrated circuit multi-scenario timing closure analysis method described in any of the embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed system and method may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above embodiments are merely examples, which are not intended to limit the scope of the present disclosure, and all equivalent structural changes made by using the contents of the specification and the drawings, or any other related technical fields, are also included in the scope of the present disclosure.