阅读说明：本技术 一种基于阻变器件的全加器函数实现方法 (Full adder function implementation method based on resistive random access device ) 是由 刘钢 陈鑫辉 于 2021-03-16 设计创作，主要内容包括：本发明公开了一种基于阻变器件的全加器函数实现方法,该方法采用五个忆阻器,根据忆阻器的阻值设定忆阻器的两个阻态,定义忆阻器的初始化的逻辑参数、忆阻器的输入和输出以及读写操作后忆阻器的输出,并采用半导体参数分析测试仪中分别对忆阻器施加正向扫描电压和负向扫描电压获取忆阻器阻态转换的阈值电压,基于该阈值电压确定忆阻器的输入的脉宽50微秒的脉冲电压的幅值大小,然后根据要实现的全加器函数初始化各个忆阻器到相应阻态后,对忆阻器进行相应写操作,就能实现该二值一位全加器函数了；优点是简化操作方法,大幅减少器件数量,减少电路面积,降低电路功耗。(The invention discloses a full adder function realization method based on a resistance change device, which adopts five memristors, sets two resistance states of the memristors according to the resistance values of the memristors, defines initialized logic parameters of the memristors, input and output of the memristors after read-write operation, applies positive scanning voltage and negative scanning voltage to the memristors respectively in a semiconductor parameter analysis tester to obtain threshold voltage for resistance state conversion of the memristors, determines the amplitude of pulse voltage with 50 microsecond pulse width input by the memristors based on the threshold voltage, and then initializes each memristor to the corresponding resistance state according to the full adder function to be realized, and then performs corresponding write operation on the memristor to realize the binary one-bit full adder function; the method has the advantages of simplifying the operation method, greatly reducing the number of devices, reducing the circuit area and reducing the power consumption of the circuit.)

1. A full adder function implementation method based on a resistance change device is characterized by comprising the following steps:

(1) selecting a memristor with electroresistance conversion and non-volatility, wherein the memristor is provided with a bottom electrode layer, a resistance conversion layer and a top electrode layer which are sequentially arranged from bottom to top, the top electrode layer of the memristor is defined as a T1 end, the bottom electrode layer is a T2 end, two resistance states of the memristor are set according to the resistance value of the memristor and are respectively marked as a high resistance state HRS and a low resistance state LRS, the resistance value range of the high resistance state is 2000 omega-4000 omega, and the resistance value range of the low resistance state is 50 omega-200 omega;

(2) logic parameters defining initialization of the memristor, inputs and outputs of the memristor:

defining five memristors as M1, M2, M3, M4 and M5 respectively, wherein M1 is used as a single path independently, M2 and M3 are connected in parallel, M4 and M5 are connected in series, M2 and M3 are connected in parallel with M4 and M5, the logic value of the memristor is 0 when the memristor is initialized to a high-resistance state, and the logic value of the memristor is 1 when the memristor is initialized to a low-resistance state; the input of the memristor is defined as pulse voltage with the pulse width of 50 microseconds, the amplitude of the pulse voltage is 0 and V1 respectively, the potential at the end T1 of the memristor is recorded as VT1, and the potential at the end T2 of the memristor is recorded as VT 2; after the writing operation, when the current of the memristor is a low current value, the output of the memristor is logic 0, and when the current of the memristor is a high current value, the output of the memristor is logic 1;

(3) grounding a T2 end of the memristor, applying direct-current scanning voltage to a T1 end of the memristor by using a semiconductor parameter analysis tester, and measuring a current-voltage curve graph of the memristor resistance state change in real time, wherein the specific process is as follows:

3-1, after setting a limiting current with a value range of 100 uA-1 mA in a semiconductor parameter analysis tester, applying a forward scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the forward scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a high resistance state to a low resistance state is measured by the semiconductor parameter analysis tester and recorded as a curve 1;

3-2, after setting a limiting current with a value of 100mA in a semiconductor parameter analysis tester, applying a negative scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the negative scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a low resistance state to a high resistance state is measured by the semiconductor parameter analysis tester and is marked as a curve 2;

(4) repeating the step 3-1 to the step 3-2 for three hundred times, observing the 600 current-voltage curves through 300 curves 1 and 300 curves 2 of the semiconductor parameter analysis tester, and obtaining values of Vset and Vreset so as to determine the value of V1;

(5) the signal A can change the state of the memristor, the signal B and the signal Cin respectively write the memristor, finally, the current value of M1 is read to judge the Cout value, and the Sum of the current values of M2-M5 is read to judge the Sum value;

(6) let the full-adder function output corresponding to Cout0 be C0, the full-adder function output corresponding to Cout1 be C1, the full-adder function output corresponding to Cout2 be C2, and so on, let the full-adder function output corresponding to Cout7 be C7, correspond to eight outputs of carry in full-adder functions, let the full-adder function output corresponding to Sum0 be S0, let the full-adder function output corresponding to Sum1 be S1, let the full-adder function output corresponding to Sum2 be S2, and so on, let the full-adder function output corresponding to Sum7 be S7, and correspond to eight outputs of two-number addition in full-adder functions: initializing five memristors to corresponding resistance states according to a full adder function to be realized; and then, carrying out corresponding writing operation on the memristor, and finally applying a small voltage pulse to read current to realize a full adder function.

2. The method for realizing the full adder based on the resistive switching device according to claim 1, wherein the specific way for realizing the full adder function in the step (6) is as follows:

when the full adder function C0 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the logic value of the C0 output of the full adder is 0;

when the full adder function C1 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C1 is 0;

when the full adder function C2 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C2 is 0; when the full adder function C3 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C3 is 1;

when the full adder function C4 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C4 is 0;

when the full adder function C5 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is changed from a high resistance state to a low resistance state, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C5 is 1;

when the full adder function C6 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C6 is 1;

when the full adder function C7 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C7 is 1;

when the full adder function S0 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded, grounded to 0.3V and grounded respectively, at this time, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, the sum of the currents for reading M2-M5 is low current, and therefore the output logic value of the full adder S0 is 0;

when the full adder function S1 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, 0.3V and 0.3V respectively, the T2 end is grounded, 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, and the sum of currents for reading M2-M5 is high current, so that the output logic value of the full adder S1 is 1;

when the full adder function S2 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are high resistance states, high resistance states and high resistance states respectively; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state, and the sum of the currents for reading M2-M5 is a high current, so that the output logic value of the full adder S2 is 1;

when the full adder function S3 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S3 is 0;

when the full adder function S4 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded with 0.3V respectively, the T2 ends are grounded, grounded with 0.3V and grounded respectively, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded and grounded 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state, the sum of the currents for reading M2-M5 is high current, and therefore the output logic value of the full adder S4 is 1;

when the full adder function S5 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is grounded, connected with 0.3V, grounded and connected with 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S5 is 0;

when the full adder function S6 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S6 is 0;

when the full adder function S7 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state, a high resistance state and a high resistance state; and then the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and connected with 0.3V respectively, finally the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of the currents for reading M2-M5 is high current, so that the output logic value of the full adder S7 is 1.

Technical Field

The invention relates to a method for realizing a full adder function, in particular to a method for realizing a full adder function based on a resistance change device.

Background

The conventional CMOS full adder mainly includes an and gate, an or gate, an xor gate, and the like. The traditional CMOS full adder realizes addition operation, and is usually used as a computer arithmetic logic unit for executing logic operation, shifting and instruction calling. The memristor has the characteristics of small size, multiple resistance states, low power consumption, nonvolatility and the like. At present, the implementation mode of the full adder function is mainly based on a CMOS device, the number of adders is increased along with the increase of two addition numerical values, the defects of large delay and high power consumption of the adders are increasingly prominent, the CMOS transistor device is slowly improved, the size reduction speed is reduced, and the manufacturing process faces the physical limit. Therefore, the CMOS adder has the problems of large power consumption, large delay, large area and the like in the data processing process.

Disclosure of Invention

The invention aims to solve the technical problem of providing a full adder function implementation method based on a resistance change device.

The technical scheme adopted by the invention for solving the technical problems is as follows: a full adder function implementation method based on a resistance change device comprises the following steps:

(1) selecting a memristor with electroresistance conversion and non-volatility, wherein the memristor is provided with a bottom electrode layer, a resistance conversion layer and a top electrode layer which are sequentially arranged from bottom to top, the top electrode layer of the memristor is defined as a T1 end, the bottom electrode layer is a T2 end, two resistance states of the memristor are set according to the resistance value of the memristor and are respectively marked as a high resistance state HRS and a low resistance state LRS, the resistance value range of the high resistance state is 2000 omega-4000 omega, and the resistance value range of the low resistance state is 50 omega-200 omega;

(2) logic parameters defining initialization of the memristor, inputs and outputs of the memristor:

defining five memristors as M1, M2, M3, M4 and M5 respectively, wherein M1 is used as a single path independently, M2 and M3 are connected in parallel, M4 and M5 are connected in series, M2 and M3 are connected in parallel with M4 and M5, the logic value of the memristor is 0 when the memristor is initialized to a high-resistance state, and the logic value of the memristor is 1 when the memristor is initialized to a low-resistance state; the input of the memristor is defined as pulse voltage with the pulse width of 50 microseconds, the amplitude of the pulse voltage is 0 and V1 respectively, the potential at the end T1 of the memristor is recorded as VT1, and the potential at the end T2 of the memristor is recorded as VT 2; after the writing operation, when the current of the memristor is a low current value, the output of the memristor is logic 0, and when the current of the memristor is a high current value, the output of the memristor is logic 1;

(3) grounding a T2 end of the memristor, applying direct-current scanning voltage to a T1 end of the memristor by using a semiconductor parameter analysis tester, and measuring a current-voltage curve graph of the memristor resistance state change in real time, wherein the specific process is as follows:

3-1, after setting a limiting current with a value range of 100 uA-1 mA in a semiconductor parameter analysis tester, applying a forward scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the forward scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a high resistance state to a low resistance state is measured by the semiconductor parameter analysis tester and recorded as a curve 1;

3-2, after setting a limiting current with a value of 100mA in a semiconductor parameter analysis tester, applying a negative scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the negative scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a low resistance state to a high resistance state is measured by the semiconductor parameter analysis tester and is marked as a curve 2;

(4) repeating the step 3-1 to the step 3-2 for three hundred times, observing the 600 current-voltage curves through 300 curves 1 and 300 curves 2 of the semiconductor parameter analysis tester, and obtaining values of Vset and Vreset so as to determine the value of V1;

(5) the signal A can change the state of the memristor, the signal B and the signal Cin respectively write the memristor, finally, the current value of M1 is read to judge the Cout value, and the Sum of the current values of M2-M5 is read to judge the Sum value;

(6) let the full-adder function output corresponding to Cout0 be C0, the full-adder function output corresponding to Cout1 be C1, the full-adder function output corresponding to Cout2 be C2, and so on, let the full-adder function output corresponding to Cout7 be C7, correspond to eight outputs of carry in full-adder functions, let the full-adder function output corresponding to Sum0 be S0, let the full-adder function output corresponding to Sum1 be S1, let the full-adder function output corresponding to Sum2 be S2, and so on, let the full-adder function output corresponding to Sum7 be S7, and correspond to eight outputs of two-number addition in full-adder functions: initializing five memristors to corresponding resistance states according to a full adder function to be realized; and then, carrying out corresponding writing operation on the memristor, and finally applying a small voltage pulse to read current to realize a full adder function.

2. The method for realizing the full adder based on the resistive switching device according to claim 1, wherein the specific way for realizing the full adder function in the step (6) is as follows:

when the full adder function C0 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the logic value of the C0 output of the full adder is 0;

when the full adder function C1 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C1 is 0;

when the full adder function C2 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C2 is 0;

when the full adder function C3 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C3 is 1;

when the full adder function C4 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; then, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through a semiconductor parameter analysis tester, and passing the T2 end of M1 through a half

The conductor parameter analysis tester loads a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor, at the moment, the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and therefore the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C4 is 0;

when the full adder function C5 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is changed from a high resistance state to a low resistance state, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C5 is 1;

when the full adder function C6 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C6 is 1; when the full adder function C7 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; and finally, loading a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V at the T1 end of the memristor through a semiconductor parameter analysis tester, grounding the T2 end of the M1, and reading the current value of the M1 to be high current, so that the output logic value of the full adder C7 is 1.

When the full adder function S0 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded, grounded to 0.3V and grounded respectively, at this time, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, the sum of the currents for reading M2-M5 is low current, and therefore the output logic value of the full adder S0 is 0;

when the full adder function S1 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, 0.3V and 0.3V respectively, the T2 end is grounded, 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, and the sum of currents for reading M2-M5 is high current, so that the output logic value of the full adder S1 is 1;

when the full adder function S2 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are high resistance states, high resistance states and high resistance states respectively; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state, and the sum of the currents for reading M2-M5 is a high current, so that the output logic value of the full adder S2 is 1;

when the full adder function S3 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S3 is 0;

when the full adder function S4 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded with 0.3V respectively, the T2 ends are grounded, grounded with 0.3V and grounded respectively, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded and grounded 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state, the sum of the currents for reading M2-M5 is high current, and therefore the output logic value of the full adder S4 is 1;

when the full adder function S5 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is grounded, connected with 0.3V, grounded and connected with 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S5 is 0;

when the full adder function S6 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S6 is 0;

when the full adder function S7 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state, a high resistance state and a high resistance state; and then the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and connected with 0.3V respectively, finally the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of the currents for reading M2-M5 is high current, so that the output logic value of the full adder S7 is 1.

Compared with the prior art, the method has the advantages that the three-value single variable function can be realized by selecting the memristor with electroresistance conversion and non-volatility, setting two resistance states of the memristor according to the resistance value of the memristor, defining the initialized logic parameters of the memristor, the input and output of the memristor and the output of the memristor after writing operation, applying positive scanning voltage and negative scanning voltage to the memristor respectively in a semiconductor parameter analysis tester to obtain the voltage for resistance state conversion of the memristor, determining the amplitude of pulse voltage of 50 microseconds of the input pulse width of the memristor and constant direct current voltage based on the voltage, initializing the memristor to the corresponding resistance according to the designed full adder function realization method, applying a signal A to change the resistance state of the memristor, performing writing operation on signals B and C, and finally reading the current value, wherein the method only needs five memristors to be matched with the semiconductor parameter analysis tester, the full adder function can be realized, the number of devices is greatly reduced, the circuit structure is optimized, the operation method is simplified, the circuit area can be reduced, and the power consumption of the circuit is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a memristor of a full adder function implementation method based on a resistive device.

Fig. 2 is a current-voltage curve diagram of a memristor of the resistive device-based full-adder function implementation method.

Fig. 3 shows a resistance state transition situation of a memristor of the resistive device-based full adder function implementation method after applying different forward scanning voltages in different resistance states.

Fig. 4 shows a resistance state transition situation of a memristor of the resistive device-based full adder function implementation method after applying different negative scanning voltages in different resistance states.

Fig. 5 is an operation method diagram for realizing a full adder function by the method for realizing a full adder function based on a resistive switching device.

Fig. 6 is a circuit structure diagram of a full adder function implemented by the method for implementing a full adder function based on a resistive switching device according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

Example (b): a full adder function implementation method based on a resistance change device comprises the following steps:

(1) selecting a memristor with electroresistance conversion, nonvolatile property and multi-resistance state characteristics, wherein the memristor is provided with a bottom electrode layer, a resistance conversion layer and a top electrode layer which are sequentially arranged from bottom to top as shown in FIG. 1, the top electrode layer of the memristor is defined as a T1 end, the bottom electrode layer is a T2 end, two resistance states of the memristor are set according to the resistance value of the memristor and are respectively marked as a high resistance state HRS (high resistance state), H for short, and a low resistance state LRS (low resistance state), L for short, wherein the resistance value range of the high resistance state is 2000-4000 omega, and the resistance value range of the low resistance state is 50-200 omega; the change situation of the resistance state of the memristor of the resistive device-based full adder function implementation method after applying different positive scanning voltages under different resistance states is shown in FIG. 3, and the change situation of the resistance state of the memristor of the resistive device-based full adder function implementation method after applying different negative scanning voltages under different resistance states is shown in FIG. 4;

(2) logic parameters defining initialization of the memristor, inputs and outputs of the memristor: defining the logic value of the memristor to be 0 when the memristor is initialized to be in a high resistance state, and defining the logic value of the memristor to be 2 when the memristor is initialized to be in a low resistance state; the input of the memristor is defined as pulse voltage with the pulse width of 50 microseconds, the amplitude of the pulse voltage is 0 and V1 respectively, the potential at the end T1 of the memristor is recorded as VT1, and the potential at the end T2 of the memristor is recorded as VT 2; after the writing operation, the output of the memristor is logic 0 when the resistance state of the memristor is a high resistance state, the output of the memristor is logic 1 when the resistance state of the memristor is an intermediate resistance state, and the output of the memristor is logic 2 when the resistance state of the memristor is a low resistance state;

(3) grounding a T2 end of the memristor, applying direct-current scanning voltage to a T1 end of the memristor by using a semiconductor parameter analysis tester, and measuring a current-voltage curve graph of the memristor resistance state change in real time, wherein the specific process is as follows:

3-1, after setting a limiting current with a value range of 100 uA-1 mA in a semiconductor parameter analysis tester, applying a forward scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the forward scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a high resistance state to a low resistance state is measured by the semiconductor parameter analysis tester and recorded as a curve 1;

3-2, after setting a limiting current with a value of 100mA in a semiconductor parameter analysis tester, applying a negative scanning voltage to a T1 end of the memristor by using the semiconductor parameter analysis tester, wherein the negative scanning voltage range is 0-0.3V, and a current-voltage curve of the memristor converted from a low resistance state to a high resistance state is measured by the semiconductor parameter analysis tester and is marked as a curve 2;

(4) repeating the step 3-1 to the step 3-2 three hundred times, observing the 600 current-voltage curves through 300 curves 1 and 300 curves 2 of the semiconductor parameter analysis tester, and obtaining values of Vset and Vreset, wherein because the Set process (process of applying positive scanning voltage) and the Reset process (process of applying negative scanning voltage) curves have better symmetry, the threshold voltage value when the high resistance state is converted to the low resistance state in the Set process or the threshold voltage value when the low resistance state is converted to the high resistance state in the Reset process is counted, and V1 is determined; in this example, the value of V1 is 0.3V;

(5) the signal A can change the state of the memristor, the signal B and the signal Cin respectively write the memristor, finally, the current value of M1 is read to judge the Cout value, and the Sum of the current values of M2-M5 is read to judge the Sum value;

(6) let the full-adder function output corresponding to Cout0 be C0, the full-adder function output corresponding to Cout1 be C1, the full-adder function output corresponding to Cout2 be C2, and so on, let the full-adder function output corresponding to Cout7 be C7, correspond to eight outputs of carry in full-adder functions, let the full-adder function output corresponding to Sum0 be S0, let the full-adder function output corresponding to Sum1 be S1, let the full-adder function output corresponding to Sum2 be S2, and so on, let the full-adder function output corresponding to Sum7 be S7, and correspond to eight outputs of two-number addition in full-adder functions: initializing five memristors to corresponding resistance states according to a full adder function to be realized; and then, carrying out corresponding writing operation on the memristor, and finally applying a small voltage pulse to read current to realize a full adder function.

In this embodiment, a specific way of implementing the full adder function in step (6) is as follows:

(5) taking a three-value univariate function corresponding to F0 as F0, a three-value univariate function corresponding to F1 as F1, a three-value univariate function corresponding to F2 as F2, and so on, taking a three-value univariate function corresponding to F25 as F25, and a three-value univariate function corresponding to F26 as F26, respectively implementing 17 three-value univariate functions of F0, F1, F2, F5, F9, F18, F4, F12, F13, F14, F22, F21, F8, F17, F24, F25, and F26 by two steps: firstly, initializing a memristor to a corresponding resistance state according to a three-value univariate function to be realized; then, writing operation is carried out on the memristor, and the three-value univariate function is achieved; taking the three-value univariate function corresponding to F3 as F3, the three-value univariate function corresponding to F1 as F1, the three-value univariate function corresponding to F2 as F2, and so on, taking the three-value univariate function corresponding to F25 as F25, the three-value univariate function corresponding to F26 as F26, and respectively adopting three steps to realize 10 three-value univariate functions of F3, F10, F11, F19, F20, F23, F6, F7, F15 and F16: firstly, initializing a memristor to a corresponding resistance state according to a three-value univariate function to be realized; and then, writing the memristor twice to realize the three-value univariate function.

In this embodiment, the specific way of implementing 17 three-valued univariate functions by two steps of operations in step (5) is as follows:

when the full adder function C0 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the logic value of the C0 output of the full adder is 0;

when the full adder function C1 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C1 is 0;

when the full adder function C2 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C2 is 0;

when the full adder function C3 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C3 is 1;

when the full adder function C4 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 0; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be low current, so that the output logic value of the full adder C4 is 0;

when the full adder function C5 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V to the memristor through a semiconductor parameter analysis tester at the T1 end of M1, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V to the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0.3V at the moment, the resistance value of the memristor is changed from a low resistance state to a high resistance state, and the output logic value of the memristor is 0; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is changed from a high resistance state to a low resistance state, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C5 is 1;

when the full adder function C6 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C6 is 1;

when the full adder function C7 is realized, firstly, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V is loaded on a memristor by a T1 end of M1 through a semiconductor parameter analysis tester, a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V is loaded on the memristor by a T2 end through the semiconductor parameter analysis tester, and the initialization is in a low-resistance state; then loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the T2 end of the memristor through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT 2-0V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0.3V on the memristor by the T1 end of M1 through the semiconductor parameter analysis tester, loading a pulse voltage with the pulse width not less than 50 microseconds and the amplitude of 0V on the memristor by the T2 end of M1 through the semiconductor parameter analysis tester, wherein the actual bearing voltage of the memristor is VT1-VT2 which is 0.3V, the resistance value of the memristor is kept unchanged, and the output logic value of the memristor is 1; finally, a pulse voltage with the pulse width not less than 100 microseconds and the amplitude of 0V is loaded at the T1 end of the memristor through a semiconductor parameter analysis tester, the T2 end of the M1 is grounded, and the current value of the M1 is read to be high current, so that the output logic value of the full adder C7 is 1;

when the full adder function S0 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded, grounded to 0.3V and grounded respectively, at this time, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, the sum of the currents for reading M2-M5 is low current, and therefore the output logic value of the full adder S0 is 0;

when the full adder function S1 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, and the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, 0.3V and 0.3V respectively, the T2 end is grounded, 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state, and the sum of currents for reading M2-M5 is high current, so that the output logic value of the full adder S1 is 1;

when the full adder function S2 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, the T2 end is respectively grounded, grounded and grounded, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are high resistance states, high resistance states and high resistance states respectively; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a low resistance state, and the sum of the currents for reading M2-M5 is a high current, so that the output logic value of the full adder S2 is 1;

when the full adder function S3 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; t1 ends of M2, M3, M4 and M5 are respectively grounded, grounded and grounded, a T2 end is respectively grounded, grounded and grounded 0.3V, and resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and grounded respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S3 is 0;

when the full adder function S4 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded with 0.3V respectively, the T2 ends are grounded, grounded with 0.3V and grounded respectively, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is grounded, grounded and grounded 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state, the sum of the currents for reading M2-M5 is high current, and therefore the output logic value of the full adder S4 is 1;

when the full adder function S5 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded to 0.3V respectively, the T2 ends are grounded to 0.3V, 0.3V and grounded respectively, and at the moment, the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is grounded, connected with 0.3V, grounded and connected with 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S5 is 0;

when the full adder function S6 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and ground, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are grounded, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a low resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, grounded and grounded respectively, the T2 end is connected with 0.3V, grounded and 0.3V respectively, finally, the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a high resistance state and a high resistance state, and the sum of currents for reading M2-M5 is low current, so that the output logic value of the full adder S6 is 0;

when the full adder function S7 is realized, respectively initializing M2, M3, M4 and M5 into a high resistance state, a low resistance state and a low resistance state; the T1 ends of M2, M3, M4 and M5 are respectively connected with 0.3V, ground and ground, the T2 end is respectively connected with ground, 0.3V and 0.3V, and the resistance states of M2, M3, M4 and M5 are respectively a low resistance state, a high resistance state and a high resistance state; then, the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and connected with 0.3V respectively, the T2 ends are connected with 0.3V, connected with 0.3V and connected with 0.3V respectively, and the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state, a high resistance state and a high resistance state; and then the T1 ends of M2, M3, M4 and M5 are grounded, connected with 0.3V and grounded respectively, the T2 end is connected with 0.3V, grounded and connected with 0.3V respectively, finally the resistance states of M2, M3, M4 and M5 are respectively a high resistance state, a low resistance state and a high resistance state, and the sum of the currents for reading M2-M5 is high current, so that the output logic value of the full adder S7 is 1.