阅读说明：本技术 一种具有多指栅极高电子迁移率晶体管器件 (High electron mobility transistor device with multi-finger grid ) 是由 贺利军 赵勃阳 何承运 谢治杨 张金沙 戚飞 张楠 陈伟中 于 2020-12-04 设计创作，主要内容包括：本发明涉及一种具有多指栅极高电子迁移率晶体管器件,属于半导体射频器件技术领域。该InP高电子迁移率晶体管器件结构包括金属源极、金属漏极、金属多指形栅极、金属背栅、In_(0.53)Ga_(0.47)As盖帽层、In_(0.52)Al_(0.48)As肖特基势垒层、In_(0.52)Al_(0.48)As间隔层、In_(0.7)Ga_(0.3)As沟道层、In_(0.52)Al_(0.48)As缓冲层、InP衬底。该器件结构特点在于：使用了多指形栅和背栅作为栅极,并在In_(0.52)Al_(0.48)As肖特基势垒层和In_(0.7)Ga_(0.3)As沟道层引入了两层δ掺杂,减小了栅极的寄生参数,并减弱因缩小栅极尺寸而引起的短沟道效应。本发明在保证器件的正向导通性能不改变的前提下,通过减小栅极寄生参数和引入δ掺杂,能够有效地提高器件的截止频率和最大振荡频率。(The invention relates to a high electron mobility transistor device with a multi-finger grid electrode, and belongs to the technical field of semiconductor radio frequency devices. The InP high electron mobility transistor device structure comprises a metal source electrode, a metal drain electrode, a metal multi-finger-shaped grid electrode, a metal back gate and In 0.53 Ga 0.47 As cap layer, In 0.52 Al 0.48 As Schottky barrier layer and In 0.52 Al 0.48 As spacer layer, In 0.7 Ga 0.3 As channel layer and In 0.52 Al 0.48 As buffer layer, InP substrate. The device is characterized in that: using multi-finger gate and back gate as gate, and In 0.52 Al 0.48 As Schottky barrier layer and In 0.7 Ga 0.3 The As channel layer introduces two layers of delta doping, reduces the parasitic parameters of the grid and weakens the short channel effect caused by reducing the size of the grid. The invention ensures the forward conduction performance of the device not to be changedOn the premise of reducing the grid parasitic parameters and introducing delta doping, the cut-off frequency and the maximum oscillation frequency of the device can be effectively improved.)

1. A hemt device having a multi-finger gate, wherein: comprises a metal source (1), a metal drain (3), a metal multi-finger grid (2), a metal back grid (11), In_0.53Ga_0.47As cap layers (4) and (5), In_0.52Al_0.48As Schottky barrier layer (6), In_0.52Al_0.48As spacer layer (7), In_0.7Ga_0.3As channel layer (8), In_0.52Al_0.48An As buffer layer (9) and an InP substrate layer (10);

the metal back grid (11) is positioned on the lower surface of the InP substrate layer (10), and the InP substrate layer (10) is doped in an n-type low concentration mode; in_0.52Al_0.48An As buffer layer (9) is arranged on the upper surface of the InP substrate layer (10) and In_0.52Al_0.48The As buffer layer is doped in n type with low concentration; in_0.7Ga_0.3An As channel layer (8) is located In_0.52Al_0.48The delta doping is positioned on the upper surface of the As buffer layer (9)_0.7Ga_0.3The position, 1nm away from the upper surface, in the As channel layer (8) is 1nm thick and is doped with n-type high concentration; in_0.52Al_0.48As spacer layer (7) is located In_0.7Ga_0.3An As channel layer (8) upper surface; in_0.52Al_0.48An As Schottky barrier layer (6) is located In_0.52Al_0.48The delta doping is positioned on the upper surface of the As spacing layer (7)_0.52Al_0.48The position 4nm away from the upper surface in the As Schottky barrier layer (6) is 2nm thick and is doped with n-type low concentration; the metal multi-finger grid (2) is positioned In_0.52Al_0.48In the middle of the upper surface of the As Schottky barrier layer (6)_0.53Ga_0.47As cap layers (4) and (5) are respectively positioned In_0.52Al_0.48Two sides of the upper surface of the As Schottky barrier layer; the metal source (1) is positioned at the left side In_0.53Ga_0.47The upper surface of the As cap layer (4) and the metal drain electrode (3) are positioned at the right side In_0.53Ga_0.47And the As cap layer (5) is arranged on the upper surface.

2. The hemt of claim 1, wherein: the number of finger grids of the multi-finger grid is N, and N is more than or equal to 2.

3. The hemt of claim 1, wherein: the gate length of a single finger gate is In_0.53Ga_0.47Arbitrary value of the As cap layer (4) and (5) spacing.

4. The hemt of claim 1, wherein: the distance between adjacent finger gates is In_0.53Ga_0.47Arbitrary value of the As cap layer (4) and (5) spacing.

5. The hemt of claim 1, wherein: the metal source electrode (1), the metal drain electrode (3), the metal multi-finger-shaped grid electrode (2) and the metal back grid electrode (11) are made of one or more of Au, Al, Cr, Ti, W, Ni, Pt and Pb.

6. The hemt of claim 1, wherein: the metal source electrode (1), the metal drain electrode (3) and the metal multi-finger-shaped grid electrode (2) are covered by a passivation layer.

7. The hemt of claim 1, wherein: in_0.53Ga_0.47As cap layers (4) and (5), In_0.52Al_0.48As Schottky barrier layer (6), In_0.52Al_0.48As spacer layer (7) and In_0.7Ga_0.3The background doping of the As channel layer (8) is n-type low-concentration doping with the doping concentration of 5 multiplied by 10⁵cm^-3。

8. The hemt of claim 1, wherein: gate and drainThe doping right below is n-type high-concentration doping with the doping concentration of 1 × 10²⁰cm^-3。

9. The hemt of claim 1, wherein: in_0.53Ga_0.47As cap layers (4) and (5), In_0.52Al_0.48As Schottky barrier layer (6), In_0.52Al_0.48As spacer layer (7), In_0.7Ga_0.3An As channel layer (8) and In_0.52Al_0.48The As buffer layer (9) is made of one or more of GaN, AlN, AlGaN, InGaN, InAlN and other multi-component semiconductor materials.

10. The hemt of claim 1, wherein: the InP substrate layer (10) is made of one or more of sapphire, Si, SiC, AlN, GaN and AlGaN.

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a transistor device with a multi-finger grid electrode and high electron mobility.

Background

Semiconductor materials widely used today for radio frequency semiconductor devices are mainly silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP). Compared with the first generation semiconductor silicon (Si), the III-V group compound semiconductor material has higher electron mobility and is more suitable for being used as a high-speed device, and a High Electron Mobility Transistor (HEMT) made of the III-V group compound semiconductor material has wider research prospect. Semiconductor materials used for the high electron mobility transistor are mainly gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP). Indium phosphide (InP) materials have higher average electron velocity and breakdown voltage than gallium arsenide (GaAs) and gallium nitride (GaN), and InP hemt devices are more suitable as rf devices due to their high electron mobility, low noise, and high gain.

In recent years, with the development of new-generation communication systems, electronic power systems, and various consumer electronics fields, there is an increasing demand for microwave and millimeter wave devices. InP-based High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs) have shown great advantages in the microwave and millimeter wave fields. Both devices are excellent choices for operating under terahertz conditions. It is known that in a Field Effect Transistor (FET), short channel effects play a crucial role in high frequency characteristics. In order to increase the frequency response characteristics of transistors, it is common practice to reduce the minimum feature size and reduce the parasitic parameters of the transistors. At present, the cutoff frequency of InP-based hemts is higher than 1THz, but the structures of the InP-based hemts need to be improved to obtain higher-band devices.

Disclosure of Invention

Accordingly, the present invention is directed to a multi-finger gate hemt device structure.

In order to achieve the purpose, the invention provides the following technical scheme:

a high electron mobility transistor device with multi-finger grid electrode comprises a metal source electrode 1, a metal drain electrode 3, a metal multi-finger grid electrode 2, a metal back grid electrode 11 and In_0.53Ga_0.47As cap layers 4 and 5, In_0.52Al_0.48As Schottky barrier layer 6, In_0.52Al_0.48As spacer 7, In_0.7Ga_0.3As channel layer 8, In_0.52Al_0.48An As buffer layer 9 and an InP substrate layer 10;

the metal back grid 11 is positioned on the lower surface of the InP substrate layer 10, and the InP substrate layer 10 is doped in an n-type low concentration mode; in_0.52Al_0.48An As buffer layer 9 on the upper surface of the InP substrate layer 10_0.52Al_0.48The As buffer layer is doped in n type with low concentration; in_0.7Ga_0.3As channel layer 8 is In_0.52Al_0.48As buffer layer 9 upper surface, delta doping In_0.7Ga_0.3The As channel layer 8 is doped with n-type high-concentration dopant at a position 1nm away from the upper surface and with a thickness of 1 nm; in_0.52Al_0.48As spacer layer 7 is located In_0.7Ga_0.3An As channel layer 8 upper surface; in_0.52Al_0.48An As Schottky barrier layer 6 is located In_0.52Al_0.48The upper surface of the As spacer layer 7 is doped with delta In_0.52Al_0.48The As Schottky barrier layer 6 is doped with n-type low-concentration dopant at a position 4nm away from the upper surface and with a thickness of 2 nm; the metal multi-finger grid 2 is positioned In_0.52Al_0.48Middle position of upper surface of As Schottky barrier layer 6, In_0.53Ga_0.47As cap layers 4 and 5 are respectively located In_0.52Al_0.48Two sides of the upper surface of the As Schottky barrier layer; metal source 1 on left side In_0.53Ga_0.47An As cap layer 4, a metal drain 3In at the right side_0.53Ga_0.47And the As cap layer 5 is arranged on the upper surface.

Furthermore, the number of the finger grids of the multi-finger grid is N, and N is more than or equal to 2.

Further, the gate length of the single finger gate is In_0.53Ga_0.47Any value of the spacing of As cap layers 4 and 5.

Further, the distance between adjacent finger gates is In_0.53Ga_0.47Any value of the spacing of As cap layers 4 and 5.

Further, the metal source electrode 1, the metal drain electrode 3, the metal multi-finger-shaped grid electrode 2 and the metal back grid electrode 11 are made of one or more of Au Al, Cr, Ti, W, Ni, Pt and Pb.

Further, the metal source electrode 1, the metal drain electrode 3 and the metal multi-finger gate electrode 2 are covered by a passivation layer.

Further, In_0.53Ga_0.47As cap layers 4 and 5, In_0.52Al_0.48As Schottky barrier layer 6, In_0.52Al_0.48As spacer 7 and In_0.7Ga_0.3The As channel layer 8 is doped with n-type low-concentration dopant with the doping concentration of 5 × 10⁵cm^-3。

Further, the doping right under the grid and the drain is n-type high-concentration doping with the doping concentration of 1 multiplied by 10²⁰cm^-3。

Further, In_0.53Ga_0.47As cap layers 4 and 5, In_0.52Al_0.48As Schottky barrier layer 6, In_0.52Al_0.48As spacer 7, In_0.7Ga_0.3As channel layer 8 and In_0.52Al_0.48The As buffer layer 9 is made of one or more of GaN, AlN, AlGaN, InGaN, InAlN and other multi-component semiconductor materials.

The InP substrate layer 10 is further made of one or more of sapphire, Si, SiC, AlN, GaN and AlGaN.

The invention has the beneficial effects that: the invention uses a multi-finger gate and a back gate as the gate, and In_0.52Al_0.48As Schottky barrier layer and In_0.7Ga_0.3Two layers of delta doping are introduced into the As channel layer to reduceThe parasitic parameters of the gate are reduced, and short channel effects caused by the reduction of the size of the gate are reduced. On the premise of ensuring that the forward conduction performance of the device is not changed, the frequency response characteristic of the device can be effectively improved by reducing the parasitic parameters of the grid and introducing delta doping.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a high-cutoff frequency multi-finger gate InP HEMT device structure provided by the present invention;

FIG. 2 is a prior art T-gate InP HEMT device structure;

FIG. 3 is a conventional InP HEMT device structure using prior art techniques;

FIG. 4 is a conventional GaAs HEMT device structure using the prior art;

FIG. 5 shows the relationship between an InP HEMT device and a conventional GaAs HEMT device in V_GS＝0V，V_DSCut-off frequency at 2V vs;

FIG. 6 shows the relationship between an InP HEMT device and a conventional GaAs HEMT device in V_GS＝0V，V_DSMaximum oscillation frequency contrast graph when being 2V;

FIG. 7 shows an InP HEMT device, a conventional InP HEMT device and a conventional GaAs HEMT device according to the present inventionParasitic parameter C of transistor device_GSComparing the images;

fig. 8 is a schematic diagram of a main process flow of an InP hemt device according to the present invention.

Reference numerals: metal source 1, metal multi-finger grid 2, metal drain 3, In_0.53Ga_0.47As cap layer 4, cap layer 5, In_0.52Al_0.48As Schottky barrier layer 6, In_0.52Al_0.48As spacer 7, In_0.7Ga_0.3As channel layer 8, In_0.52Al_0.48As buffer layer 9, InP substrate layer 10, metal back grid 11.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

As shown In FIG. 1, the invention relates to a high-cut-off frequency multi-finger gate InP HEMT device structure, which comprises a metal source 1, a metal drain 3, a metal multi-finger gate 2, a metal back gate 11, In_0.53Ga_0.47As cap layers 4 and 5, In_0.52Al_0.48As Schottky barrier layer 6, In_0.52Al_0.48As spacer 7, In_0.7Ga_0.3As channel layer 8, In_0.52Al_0.48As buffer layer 9, InP substrate layer 10.

The metal back grid 11 is positioned on the lower surface of the InP substrate 10 layer, the width of the metal back grid is 1.5 μm, and the thickness of the metal back grid is 6 nm.

The InP substrate 10 is located In_0.52Al_0.48The lower surface of the As buffer layer 9 and the upper surface of the metal back gate 11 have a width of 1.5 μm and a thickness of 500nm, and the InP substrate 10 is doped with n-type dopant at a concentration of 5 × 10³cm^-3。

In_0.52Al_0.48As buffer layer 9 at In_0.7Ga_0.3The lower surface of the As channel layer 8 and the upper surface of the InP substrate 10 were 1.5 μm In width and 284nm In thickness, and aligned with In_0.52Al_0.48The As buffer layer 9 is doped with n-type low concentration of 5 × 10⁵cm^-3。

In_0.7Ga_0.3As channel layer 8 is In_0.52Al_0.48Lower surface of As spacer layer 7 and In_0.52Al_0.48The As buffer layer 9 has an upper surface with a width of 1.5 μm and a thickness of 10nm for In_0.7Ga_0.3The As channel layer 8 is doped with n-type low concentration of 5 × 10⁵cm^-3. n-type high-concentration delta doped upper surface is positioned In_0.7Ga_0.3Within the As channel layer 8, a distance In_0.7Ga_0.3The As channel layer 8 has a thickness of 1nm at a position of 1nm on the upper surface thereof and a doping concentration of 5 × 10¹⁸cm^-3。

In_0.52Al_0.48As spacer layer 7 is located In_0.52Al_0.48Lower surface of As Schottky barrier layer 6 and In_0.7Ga_0.3An upper surface of the As channel layer 8, having a width of 1.5 μm and a thickness of 10nm, and facing In_0.52Al_0.48The As spacing layer 7 is doped with n-type low concentration, the doping concentration is 5 multiplied by 10⁵cm^-3。

In_0.52Al_0.48An As Schottky barrier layer 6 is located In_0.52Al_0.48Upper surface of As spacer layer 7, In_0.53Ga_0.47As capping layers 4, 5 and under the metal gate 3. The upper surface of the N-type low-concentration delta doping is positioned In_0.52Al_0.48Within the As Schottky barrier layer 6, a distance In_0.52Al_0.48The As Schottky barrier layer 6 has a thickness of 2nm at 4nm on its upper surface and a doping concentration of 1 × 10¹³cm^-3。

In_0.53Ga_0.47As cap layer 4 In_0.52Al_0.48The upper surface of the As Schottky barrier layer 6, which is located immediately to the left of the device, has a width of 400nm and a thickness of 25nm, and faces In_0.53Ga_0.47The As cap layer 4 is doped with n-type low concentration with the doping concentration of 5 multiplied by 10⁵cm^-3。

In_0.53Ga_0.47As cap 5 In_0.52Al_0.48The upper surface of the As Schottky barrier layer 6, immediately to the right of the device, had a width of 800nm and a thickness of 25nm, and was aligned with In_0.53Ga_0.47The As cap layer 5 is doped with n-type low concentration with the doping concentration of 5 multiplied by 10⁵cm^-3。

Metal source 1 is In_0.53Ga_0.47The upper surface of the As cap layer 4 is only arranged at the left side of the device, the width is 200nm, the thickness is 10nm, and the material is metal Au.

The metal drain electrode 3 is located In_0.53Ga_0.47The upper surface of the As cap layer 5, just to the right of the device,the width is 200nm, the thickness is 10nm, and the material is metal Au.

The metal multi-finger grid 2 is positioned In_0.52Al_0.48The upper surface of the As Schottky barrier layer 6, the left side surface of the left finger grid of the metal multi-finger grid 2 is 500nm away from the left side surface of the device, the width is 25nm, and the height is 25 nm; the left surface of the right finger grid is positioned 550nm away from the left surface of the device, the width is 25nm, and the height is 25 nm; the parallel part is positioned at the center of the upper surfaces of the two finger gates, and has the width of 125nm and the thickness of 100 nm. The metal multi-finger-shaped grid 2 is made of metal Au.

FIG. 5 shows T at 300K at room temperature, at V_GS＝0V、V_DSAt 2V, the current gain (H) of the prior art T-gate InP hemt device structure (the structure is shown in fig. 2), the conventional InP hemt device (the structure is shown in fig. 3), the conventional GaAs hemt device (the structure is shown in fig. 4), and the high-off frequency multi-finger-gate InP hemt device structure (the structure is shown in fig. 1) provided by the present invention are used₂₁) Comparing the graphs, the frequency when the current gain is reduced to 0 in the graph is the cut-off frequency of the device. The comparison graph of the data result obtained by the Silvaco simulation and drawn by the Origin tool is shown in FIG. 4, and it can be seen that: at V_GS＝0V、V_DSThe current gain of the conventional InP hemt device is at most 112.5dB at 2V, and the cutoff frequency is 190.7 GHz; the maximum current gain of the traditional GaAs high electron mobility transistor device is 61.3dB, and the cutoff frequency is 46.3 GHz; the current gain using the prior art T-gate InP hemt device is 127.5dB maximum with a cutoff frequency of 3.399 THz; the current gain of the high-cutoff frequency multi-finger-shaped gate InP high-electron-mobility transistor device provided by the invention is 4.279THz at the maximum cut-off frequency of 147.1 dB. Therefore, the current gain of the high-cutoff frequency multi-finger-shaped grid InP high-electron-mobility transistor device provided by the invention is 30% higher than that of the traditional InP high-electron-mobility transistor device, 140% higher than that of the traditional GaAs high-electron-mobility transistor device, and 15% higher than that of the T-shaped grid InP high-electron-mobility transistor device in the prior art(ii) a The cutoff frequency of the InP high-electron-mobility transistor device provided by the invention is 22.43 times higher than that of the traditional InP high-electron-mobility transistor device, 92.41 times higher than that of the traditional GaAs high-electron-mobility transistor device, and 1.26 times higher than that of the InP high-electron-mobility transistor device with the T-shaped grid electrode in the prior art. It can be seen that the novel InP hemt device provided by the present invention has better current gain and cutoff frequency and T-gate InP hemt devices than conventional InP hemt devices and conventional GaAs hemt devices.

FIG. 6 shows T at 300K at room temperature, at V_GS＝0V、V_DSWhen the Maximum Stable Gain (MSG) of the T-gate InP hemt device structure of the prior art (the structure is shown in fig. 2), the conventional InP hemt device (the structure is shown in fig. 3), the conventional GaAs hemt device (the structure is shown in fig. 4), and the high-cutoff frequency multi-finger-gate InP hemt device structure provided by the present invention (the structure is shown in fig. 1) are compared at 2V, and the frequency when the maximum stable gain is reduced to 0 in the graph is the maximum oscillation frequency. The data results from the Silvaco simulation are plotted by Origin tool as a comparison chart as shown in FIG. 5. It can be seen that: at V_GS＝0V、V_DSWhen the voltage is 2V, the maximum stable gain of the traditional InP high-electron-mobility transistor device is 63.71dB at most, and the maximum oscillation frequency is 1.56 THz; the maximum stable gain of the traditional GaAs high electron mobility transistor device is 53.96dB, and the maximum oscillation frequency is 309 GHz; the maximum stable gain of the prior art T-gate InP hemt device was 68.06dB, and the maximum oscillation frequency was 39.1 THz; the maximum stable gain of the high-cutoff frequency multi-finger-shaped gate InP high-electron-mobility transistor device is 80.91dB, and the maximum oscillation frequency is 39.1 THz. Therefore, the maximum stable gain of the high-cutoff frequency multi-finger-shaped grid InP high-electron-mobility transistor device provided by the invention is 27% higher than that of the traditional InP high-electron-mobility transistor device, 50% higher than that of the traditional GaAs high-electron-mobility transistor device and higher than that of the prior artThe T-shaped grid InP high electron mobility transistor device is 19% higher; the maximum oscillation frequency of the high-cutoff frequency multi-finger-shaped gate InP high-electron-mobility transistor device provided by the invention is 25.06 times higher than that of the traditional InP high-electron-mobility transistor device, 126.5 times higher than that of the traditional GaAs high-electron-mobility transistor device, and is as high as that of the T-shaped gate InP high-electron-mobility transistor device in the prior art. It can be seen that the novel InP hemt device provided by the present invention has better maximum stable gain and maximum oscillation frequency than conventional InP hemts and conventional GaAs hemts, and has better maximum stable gain than T-gate InP hemts.

FIG. 7 shows T at 300K at room temperature, at V_GS＝0V、V_DSAt 2V, a prior art T-gate InP hemt device structure (fig. 2), a conventional InP hemt device (fig. 3), a conventional GaAs hemt device (fig. 4), and a high-off frequency multi-finger InP hemt device structure (fig. 1) C are used_GS-V characteristic comparison plot, C_GSThe smaller the frequency response characteristics of the device, the better. The data results from the Silvaco simulation are plotted by Origin tool as a comparison chart as shown in FIG. 6. It can be seen that at V_GS＝0V、V_DSWhen 2V, the parasitic capacitance of all three devices is V_GSWhen the voltage is higher than the threshold voltage, the voltage begins to increase and finally tends to be flat. Stray capacitance C of conventional InP HEMT device smoothing_GSIs 3.45X 10^-16F/mum parasitic capacitance C of conventional GaAs HEMT device_GSIs 1.09X 10^-15F/mum parasitic capacitance C of the prior art T-gate InP HEMT device_GSIs 3.20X 10^-16F/mum, parasitic capacitance C of flat-time multi-finger grid InP high electron mobility transistor device with high cut-off frequency provided by the invention_GSIs 2.71X 10^-16F/. mu.m. Thereby the device is provided withIt can be seen that the parasitic capacitance C of the conventional InP HEMT device is flat_GSIs 27 percent larger than that of a novel InP high electron mobility transistor device, and has moderate parasitic capacitance C of a traditional GaAs high electron mobility transistor device_GSParasitic capacitance C302% larger than the new InP HEMT device, which is moderate using the prior art T-gate InP HEMT device_GS18% larger than the new InP hemt device. Therefore, compared with the traditional InP high-electron-mobility transistor device and the traditional GaAs high-electron-mobility transistor device, the novel InP high-electron-mobility transistor device provided by the invention has lower parasitic capacitance and better frequency response characteristic.

A schematic diagram of a hemt device with a multi-finger gate according to the present invention is shown in fig. 8, and the main process flow is illustrated in fig. 1. Growing a layer of In on InP substrate by molecular beam epitaxy_0.52Al_0.48As, In by molecular beam epitaxy_0.52Al_0.48As growing an In layer_0.7Ga_0.3As, followed by In_0.7Ga_0.3Epitaxially growing an In layer on As_0.52Al_0.48As, finally In_0.52Al_0.48Growing an In layer on As_0.53Ga_0.47As. And then depositing a layer of Au on the back surface of the InP substrate to be used as a back grid. Then In_0.53Ga_0.47Au metal is deposited on As, and the middle is etched by photolithography to form a source electrode and a drain electrode. Depositing a layer of Si by CVD₃N₄Over the device and etched to be planar. Then etching on Si by photolithography₃N₄Opening two 50-nanometer apertures, depositing Au, etching to form multi-finger grid, and further reducing parasitic parameters of the device by using Si₃N₄And (4) stripping.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.