阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 西胁达也 于 2020-01-19 设计创作，主要内容包括：实施方式提供能够减小导通电阻的半导体装置。半导体装置具有第1电极、第1导电型的第1半导体区域、第2导电型的第2半导体区域、第1导电型的第3半导体区域、第1绝缘部、第2电极、栅极电极、第2绝缘部以及第3电极。第2电极设置在第1绝缘部中,具有在第2方向上与第1半导体区域对置的部分。栅极电极设置在第1绝缘部中,在第2方向上隔着栅极绝缘层而与第2半导体区域对置,与第2电极电分离。第2绝缘部与第1绝缘部相连。第2绝缘部的第1方向上的长度比第1半导体区域与第2电极之间的第1绝缘部的厚度长。第2绝缘部的第2方向上的长度比第1绝缘部的厚度的2倍短。第3电极与第2半导体区域、第3半导体区域以及第2电极电连接。(Embodiments provide a semiconductor device capable of reducing on-resistance. The semiconductor device includes a 1 st electrode, a 1 st semiconductor region of a 1 st conductivity type, a 2 nd semiconductor region of a 2 nd conductivity type, a 3 rd semiconductor region of a 1 st conductivity type, a 1 st insulating portion, a 2 nd electrode, a gate electrode, a 2 nd insulating portion, and a 3 rd electrode. The 2 nd electrode is provided in the 1 st insulating portion and has a portion facing the 1 st semiconductor region in the 2 nd direction. The gate electrode is provided in the 1 st insulating portion, faces the 2 nd semiconductor region with the gate insulating layer therebetween in the 2 nd direction, and is electrically separated from the 2 nd electrode. The 2 nd insulating part is connected with the 1 st insulating part. The length of the 2 nd insulating portion in the 1 st direction is longer than the thickness of the 1 st insulating portion between the 1 st semiconductor region and the 2 nd electrode. The length of the 2 nd insulating part in the 2 nd direction is shorter than 2 times the thickness of the 1 st insulating part. The 3 rd electrode is electrically connected to the 2 nd semiconductor region, the 3 rd semiconductor region, and the 2 nd electrode.)

1. A semiconductor device, comprising:

a 1 st electrode;

a 1 st semiconductor region of a 1 st conductivity type provided on the 1 st electrode and electrically connected to the 1 st electrode;

a 2 nd semiconductor region of a 2 nd conductivity type provided above the 1 st semiconductor region;

a 3 rd semiconductor region of the 1 st conductivity type selectively provided above the 2 nd semiconductor region;

a 1 st insulating portion arranged in parallel with a part of the 1 st semiconductor region, the 2 nd semiconductor region, and the 3 rd semiconductor region in a 2 nd direction perpendicular to a 1 st direction from the 1 st electrode toward the 1 st semiconductor region;

a 2 nd electrode provided in the 1 st insulating portion and having a portion facing the 1 st semiconductor region in the 2 nd direction;

a gate electrode provided in the 1 st insulating portion, facing the 2 nd semiconductor region with a gate insulating layer therebetween in the 2 nd direction, and electrically separated from the 2 nd electrode;

a 2 nd insulating portion connected to the 1 st insulating portion, a length of the 2 nd insulating portion in the 1 st direction being longer than a thickness of the 1 st insulating portion between the 1 st semiconductor region and the 2 nd electrode, and a length of the 2 nd direction being shorter than 2 times the thickness of the 1 st insulating portion; and

and a 3 rd electrode provided on the 2 nd semiconductor region and the 3 rd semiconductor region and electrically connected to the 2 nd semiconductor region, the 3 rd semiconductor region, and the 2 nd electrode.

2. The semiconductor device according to claim 1,

a 4 th semiconductor region of the 1 st conductivity type provided between the 1 st electrode and the 1 st semiconductor region;

an impurity concentration of the 1 st conductivity type in the 4 th semiconductor region is higher than an impurity concentration of the 1 st conductivity type in the 1 st semiconductor region;

a lower end of the 2 nd insulating portion is separated from the 4 th semiconductor region in the 1 st direction.

3. The semiconductor device according to claim 1 or 2,

the length of the 2 nd insulating portion in the 2 nd direction is shorter as it goes downward.

4. The semiconductor device according to claim 1 or 2,

a plurality of the 1 st insulating portion, the 2 nd insulating portion, the gate electrode, and the 2 nd electrode are each provided in the 2 nd direction;

the 1 st semiconductor region includes:

a 1 st portion located between the 1 st insulating portions adjacent to each other in the 2 nd direction; and

a 2 nd portion located between the 2 nd insulating portions adjacent to each other in the 2 nd direction;

the length of the 2 nd portion in the 2 nd direction is longer than the length of the 1 st portion in the 2 nd direction.

5. The semiconductor device according to claim 4,

a plurality of the 1 st insulating portion, the 2 nd insulating portion, the gate electrode, and the 2 nd electrode are provided in a 3 rd direction perpendicular to the 1 st direction and intersecting the 2 nd direction;

the length of the 2 nd insulating portion in the 3 rd direction is shorter than 2 times the thickness of the 1 st insulating portion.

6. The semiconductor device according to claim 5,

the 1 st semiconductor region includes:

a 3 rd portion located between the 1 st insulating portions adjacent to each other in the 3 rd direction; and

a 4 th portion located between the 2 nd insulating portions adjacent to each other in the 3 rd direction;

the 4 th portion has a length in the 3 rd direction longer than a length in the 3 rd direction of the 3 rd portion.

7. The semiconductor device according to claim 1 or 2,

the 2 nd insulating portion is provided with a gap.

8. The semiconductor device according to claim 1 or 2,

the 1 st insulating portion and the 2 nd insulating portion include silicon oxide.

9. The semiconductor device according to claim 1 or 2,

a ratio of the length of the 2 nd insulating portion in the 1 st direction to the length of the 2 nd electrode in the 1 st direction is 0.5 to 2.0.

10. The semiconductor device according to claim 1 or 2,

a ratio of the length of the 2 nd insulating portion in the 2 nd direction to the length of the 2 nd electrode in the 2 nd direction is 0.5 to 2.0.

11. The semiconductor device according to claim 1 or 2,

a ratio of a distance in the 1 st direction between the 1 st electrode and the 2 nd insulating portion to a distance in the 1 st direction between the 1 st electrode and the 2 nd semiconductor region is 0.1 to 0.5.

Technical Field

Embodiments of the present invention relate to a semiconductor device.

Background

Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used for power conversion and the like. It is desirable that the on-resistance of the semiconductor device is low.

Disclosure of Invention

Embodiments of the invention provide a semiconductor device capable of reducing on-resistance.

The semiconductor device of the embodiment has a 1 st electrode, a 1 st semiconductor region of a 1 st conductivity type, a 2 nd semiconductor region of a 2 nd conductivity type, a 3 rd semiconductor region of a 1 st conductivity type, a 1 st insulating portion, a 2 nd electrode, a gate electrode, a 2 nd insulating portion, and a 3 rd electrode. The 1 st semiconductor region is provided above the 1 st electrode and electrically connected to the 1 st electrode. The 2 nd semiconductor region is provided above the 1 st semiconductor region. The 3 rd semiconductor region is selectively provided above the 2 nd semiconductor region. The 1 st insulating portion is arranged in parallel with a part of the 1 st semiconductor region, the 2 nd semiconductor region, and the 3 rd semiconductor region in a 2 nd direction perpendicular to a 1 st direction from the 1 st electrode toward the 1 st semiconductor region. The 2 nd electrode is provided in the 1 st insulating portion and has a portion facing the 1 st semiconductor region in the 2 nd direction. The gate electrode is provided in the 1 st insulating portion, faces the 2 nd semiconductor region with a gate insulating layer therebetween in the 2 nd direction, and is electrically separated from the 2 nd electrode. The 2 nd insulating part is connected to the 1 st insulating part. The length of the 2 nd insulating portion in the 1 st direction is longer than the thickness of the 1 st insulating portion between the 1 st semiconductor region and the 2 nd electrode. The length of the 2 nd insulating portion in the 2 nd direction is shorter than 2 times the thickness of the 1 st insulating portion. The 3 rd electrode is provided above the 2 nd semiconductor region and the 3 rd semiconductor region, and is electrically connected to the 2 nd semiconductor region, the 3 rd semiconductor region, and the 2 nd electrode.

Drawings

Fig. 1 is a plan view showing a semiconductor device according to embodiment 1.

Fig. 2 is a perspective sectional view including section II-II of fig. 1.

Fig. 3 is an enlarged cross-sectional view of the field plate electrode of fig. 2.

Fig. 4(a) to 8(b) are sectional views showing steps of manufacturing the semiconductor device according to embodiment 1.

Fig. 9 is a perspective cross-sectional view showing a part of a semiconductor device according to modification 1 of embodiment 1.

Fig. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to modification 2 of embodiment 1.

Fig. 11 is a plan view showing the semiconductor device according to embodiment 2.

Fig. 12 is a plan view showing a portion XII of fig. 11.

FIG. 13 is a cross-sectional view XIII-XIII in FIG. 12.

FIG. 14 is a cross-sectional view XIV-XIV of FIG. 12.

Fig. 15 is a sectional view XV-XV of fig. 12.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings.

The drawings are schematic or conceptual, and the relationship between the thickness and the width of each portion, the ratio of the sizes of the portions, and the like are not necessarily the same as those in reality. Even in the case of representing the same portion, the sizes or ratios of each other are represented differently according to the drawings.

In the present specification and the drawings, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

In the following description and drawings, n⁺、n^－And p⁺And p denotes the relative level of each impurity concentration. That is, a mark with "+" indicates that the impurity concentration is relatively high compared to a mark without either of "+" and "-", with "-".The mark of (a) indicates that the impurity concentration is relatively low compared to a mark without any of "+" and "-". When both the p-type impurity and the n-type impurity are contained in the respective regions, these marks indicate the relative high or low of the net impurity concentration after these impurities compensate each other.

In the embodiments described below, the p-type and n-type of each semiconductor region may be inverted.

(embodiment 1)

Fig. 1 is a plan view showing a semiconductor device according to embodiment 1.

Fig. 2 is a perspective sectional view including section II-II of fig. 1.

The semiconductor device according to embodiment 1 is, for example, a MOSFET. As shown in fig. 1 and 2, the semiconductor device 100 of embodiment 1 includes n^－Drift region 1 (1 st semiconductor region) of type (1 st conductivity type), base region 2 (2 nd semiconductor region) of p-type (2 nd conductivity type), n⁺Type source region 3 (3 rd semiconductor region), n⁺Type drain region 4, p⁺A type contact region 5, a gate electrode 10, a drain electrode 11 (1 st electrode), an FP electrode 12 (2 nd electrode), a source electrode 13 (3 rd electrode), a gate pad 14, a 1 st insulating portion 21, a 2 nd insulating portion 22, and a connection portion 31.

In the following description of the respective embodiments, the 1 st direction D1, the 2 nd direction D2, and the 3 rd direction D3 are used. Will be directed from the drain electrode 11 towards n^－The direction of the type drift region 1 is set to the 1 st direction D1. A direction perpendicular to the 1 st direction D1 is set as a 2 nd direction D2. A direction perpendicular to the 1 st direction D1 and intersecting the 2 nd direction D2 is set as the 3 rd direction D3. For convenience of explanation, the direction from the drain electrode 11 to n will be described^－The direction of the type drift region 1 is referred to as "up", and the opposite direction thereof is referred to as "down". These directions are based on the drain electrode 11 and n^－The relative positional relationship of the drift region 1 is independent of the direction of gravity.

As shown in fig. 1, a source electrode 13 and a gate pad 14 are provided on the upper surface of the semiconductor device 100. The source electrode 13 and the gate pad 14 are electrically separated from each other. In fig. 1, a dot frame is given to the gate electrode 10 provided below the source electrode 13. As shown in fig. 1, a plurality of gate electrodes 10 are provided in the 2 nd direction D2, and each gate electrode 10 extends in the 3 rd direction D3. In this example, the 3 rd direction D3 is perpendicular with respect to the 2 nd direction D2.

As shown in fig. 2, a drain electrode 11 is provided on the lower surface of the semiconductor device 100. On the drain electrode 11, with n interposed⁺The drain region 4 is provided with n^－And a drift region 1. n is^－Drift region 1 via n⁺The drain region 4 is electrically connected to the drain electrode 11. The p-type substrate region 2 is arranged at n^－Over the drift region 1. n is⁺Type source region 3 and p⁺A type contact region 5 is selectively disposed over the p-type substrate region 2.

The 1 st insulating part 21 is aligned with the n in the 2 nd direction D2^－Part of drift region 1, p-type base region 2, and n⁺The source regions 3 are arranged side by side. The gate electrode 10 and the FP electrode 12 are provided in the 1 st insulating portion 21. FP electrode 12 is connected to n in the 2 nd direction D2^－The drift regions 1 face each other. The gate electrode 10 is disposed over the FP electrode 12. The gate electrode 10 faces the p-type base region 2 in the 2 nd direction D2 with the gate insulating layer 10a as a part of the 1 st insulating portion 21 interposed therebetween. In the semiconductor device 100, the gate electrode 10 is further connected to n through the gate insulating layer 10a^－Part of drift region 1 and n⁺A part of the source region 3 faces each other. A part of the 1 st insulating portion 21 is provided between the gate electrode 10 and the FP electrode 12. Thereby, the gate electrode 10 and the FP electrode 12 are electrically separated from each other.

The 2 nd insulating part 22 is disposed under the 1 st insulating part 21 and connected to the 1 st insulating part 21. The FP electrode 12 is provided only in the 1 st insulating portion 21. That is, the FP electrode 12 is not provided in the 2 nd insulating portion 22.

A source electrode 13 is provided at n⁺Type source region 3, p⁺N on the type contact region 5 and the gate electrode 10⁺Type source region 3, p⁺The type contact region 5 and the FP electrode 12 are electrically connected. In a semiconductor device 100, a p-type substrate region 2 is provided with a p-type⁺Type contact region 5 and two n⁺Type source region3。p⁺The type contact region 5 is located at the ratio n⁺The source region 3 is located at a lower position. A part of the connecting portion 31 is located at n in the 2 nd direction D2⁺The source regions 3 are positioned between each other. n is⁺Type source region 3 and p⁺The type contact region 5 is electrically connected to the source electrode 13 via the connection portion 31. p-type substrate region 2 via p⁺The type contact region 5 and the connection portion 31 are electrically connected to the source electrode 13. The gate electrode 10 is electrically separated from the source electrode 13 and electrically connected to the gate pad 14.

For example, p-type substrate region 2, n⁺Type source region 3, p⁺The plurality of type contact regions 5, the gate electrode 10, the FP electrode 12, the 1 st insulating portion 21, and the 2 nd insulating portion 22 are provided in the 2 nd direction D2, and extend in the 3 rd direction D3. Further, n is^－The drift region 1 has a 1 st portion 1a and a 2 nd portion 1 b. The 1 st portions 1a are located between the 1 st insulating parts 21 adjacent in the 2 nd direction D2. The 2 nd portions 1b are located between the 2 nd insulating parts 22 adjacent in the 2 nd direction D2. The plurality of 1 st portions 1a and the plurality of 1 st insulating parts 21 are alternately arranged in the 2 nd direction D2. The plurality of 2 nd portions 1b and the plurality of 2 nd insulating parts 22 are alternately arranged in the 2 nd direction D2.

Fig. 3 is an enlarged cross-sectional view of the vicinity of the FP electrode 12 in fig. 2.

As shown in FIG. 3, the length L1 of the 2 nd insulating part 22 in the 1 st direction D1 is larger than n^－The thickness T1 of the 1 st insulating portion 21 between the type drift region 1 and the FP electrode 12 is long. Further, the length L2 of the 2 nd insulating portion 22 in the 2 nd direction D2 is shorter than 2 times the thickness T1. When the length L2 varies in the 1 st direction D1, the length of the longest portion in the 2 nd direction D2 is used as the length L2.

The boundary between the 1 st insulating portion 21 and the 2 nd insulating portion 22 can be determined as follows, for example.

The 1 st insulating portion 21 has a pair of side surfaces S1 and a pair of curved surfaces S2. The 2 nd insulating portion 22 has a pair of side surfaces S3. The side S1 is along the 1 st direction D1. That is, the inclination of the side surface S1 with respect to the 1 st direction D1 is smaller than the inclination of the side surface S1 with respect to the 2 nd direction D2. The upper end of the curved surface S2 is connected to the side surface S1 along the 1 st direction D1. The lower end of the curved surface S2 is connected to the side surface S3 along the 2 nd direction D2. That is, the inclination of the curved surface S2 with respect to the 1 st direction D1 is larger toward the lower side. On the other hand, the upper end of the side surface S3 has a smaller inclination with respect to the 1 st direction D1 than the upper end of the side surface S3 has with respect to the 2 nd direction D2. Thus, between the curved surface S2 and the side surface S3, there is a point P where the inclination with respect to the 1 st direction D1 is smaller than the inclination with respect to the 2 nd direction D2. Points P are respectively determined between the pair of curved surfaces S2 and the pair of side surfaces S3. A surface obtained by connecting these points P may be defined as a boundary between the 1 st insulating portion 21 and the 2 nd insulating portion 22. The length L1 of the 2 nd insulating portion 22 can be obtained with the boundary as a reference.

If the length L2 of the 2 nd insulating part 22 is shorter than 2 times the thickness T1, the length L2 is shorter than the length L3 in the 1 st direction D1 of the 1 st insulating part 21. Thus, with respect to n^－The drift region 1, as shown in fig. 2, has a length L4 in the 2 nd direction D2 of the 2 nd part 1b longer than a length L5 in the 2 nd direction D2 of the 1 st part 1 a. When the lengths L4 and L5 each change in the 1 st direction D1, the length of the longest portion in the 2 nd direction D2 is used as the length L4 and the length L5, respectively.

The operation of the semiconductor device 100 will be described.

In a state where a positive voltage is applied to the drain electrode 11 with respect to the source electrode 13, a voltage equal to or higher than a threshold value is applied to the gate electrode 10. Thereby, a channel (inversion layer) is formed in the p-type base region 2, and the semiconductor device 100 is turned on. Electrons flow from the source electrode 13 to the drain electrode 11 through the channel. Then, if the voltage applied to gate electrode 10 becomes lower than the threshold value, the channel in p-type base region 2 disappears, and semiconductor device 100 is turned off.

If the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 with respect to the source electrode 13 increases. Depletion layer from the 1 st insulating portion 21 and n by the increase of the positive voltage^－The interface of drift region 1 faces n^－The type drift region 1 is extended. The expansion of the depletion layer can improve the withstand voltage of the semiconductor device 100. Alternatively, n can be increased while maintaining the withstand voltage of the semiconductor device 100^－Drift of typeThe n-type impurity concentration in the region 1 reduces the on-resistance of the semiconductor device 100.

An example of a material of each component of the semiconductor device 100 will be described.

n^－Drift region 1, p-type base region 2, n⁺Type source region 3, n⁺Type drain region 4 and p⁺The type contact region 5 comprises silicon, silicon carbide, gallium nitride or gallium arsenide as semiconductor material. In the case of using silicon as a semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. As the p-type impurity, boron can be used.

The gate electrode 10 and the FP electrode 12 include a conductive material such as polysilicon. Impurities may also be added to the conductive material.

The 1 st insulating portion 21 and the 2 nd insulating portion 22 each contain an oxide-based insulating material such as silicon oxide.

The drain electrode 11, the source electrode 13, and the gate pad 14 include a metal such as aluminum or copper.

The connection portion 31 includes metal such as tungsten.

An example of a method for manufacturing the semiconductor device 100 according to embodiment 1 will be described.

Fig. 4 to 8 are process sectional views showing the manufacturing process of the semiconductor device according to embodiment 1. Fig. 4 to 8 show the manufacturing process in the cross section parallel to the 1 st direction D1 and the 2 nd direction D2.

Preparing to have n⁺Type semiconductor layers 4s and n^－The semiconductor substrate Sub of the type semiconductor layer 1 s. At n^－An insulating layer IL1 is formed over the type semiconductor layer 1s, and the insulating layer IL1 is patterned by photolithography. N is removed using the insulating layer IL1 as a mask^－Part of the type semiconductor layer 1s is formed with an opening OP1 as shown in fig. 4 (a). The opening OP1 is formed in plurality in the 2 nd direction D2, and each opening OP1 extends in the 3 rd direction D3.

By thermal oxidation, a plurality of insulating layers IL2 are formed along the inner surfaces of the plurality of openings OP1, respectively. Anisotropic etching by Reactive Ion Etching (RIE) or the like leaves the insulating layer IL2 disposed on the side of the opening OP1, and removes the bottom disposed on the opening OP1Insulating layer IL2 of section. Thus, as shown in FIG. 4(b), n^－The type semiconductor layer 1s is exposed at the bottom of the opening OP 1.

N exposed at the bottom of the opening OP1 is removed using the insulating layers IL1 and IL2 as masks^－The type semiconductor layer 1 s. Thereby, as shown in fig. 5(a), an opening OP2 is formed at the bottom of the opening OP 1. The width (dimension in the 2 nd direction D2) W2 of the opening OP2 is narrower than the width W1 of the opening OP 1. Further, the width W2 of the opening OP2 is shorter than 2 times the thickness T2 of the insulating layer IL3 formed later.

The insulating layers IL1 and IL2 are removed. Thus, n covered with insulating layers IL1 and IL2^－The surface of the type semiconductor layer 1s is exposed. By thermal oxidation, as shown in FIG. 5(b), along n^－An insulating layer IL3 is formed on the surface of the type semiconductor layer 1 s. The insulating layer IL3 may be formed by Chemical Vapor Deposition (CVD). As described above, the width W2 of the opening OP2 is shorter than 2 times the thickness T2 of the insulating layer IL 3. Therefore, the opening OP2 is buried by the insulating layer IL3 formed along the 2 nd direction D2 from both side faces of the opening OP 2. The thickness T2 of the insulating layer IL3 corresponds to the thickness T1 of the 1 st insulating portion 21 shown in fig. 3, and is substantially the same as the thickness T1.

A conductive layer burying the plurality of openings OP1 is formed over the insulating layer IL 3. For example, the conductive layer includes polycrystalline silicon added with impurities. The top surface of the conductive layer is retreated, and FP electrodes 12 are formed inside the respective openings OP 1. As shown in fig. 6(a), an insulating layer IL4 covering the plurality of FP electrodes 12 is formed over the insulating layer IL 3.

The upper surfaces of the insulating layers IL3 and IL4 are receded. Thus, n^－A part of the surface of the type semiconductor layer 1s and the surface of the p-type base region 2 are exposed. By thermal oxidation, as shown in FIG. 6(b), along the exposed n^－Insulating layer IL5 is formed on the surface of type semiconductor layer 1s and p-type substrate region 2.

A conductive layer burying the plurality of openings OP1 is formed over the insulating layer IL 5. For example, the conductive layer includes polycrystalline silicon added with impurities. The upper surface of the conductive layer is retreated, and the gate electrode 10 is formed inside each opening OP 1. At n^－Ion implantation of p-type impurities into the surface of the semiconductor layer 1s to form a p-type semiconductor layerA base region 2. At this time, the lower end of the gate electrode 10 is located at the ratio n^－The interface between the type semiconductor layer 1s and the p-type base region 2 is located below. N-type impurities are ion-implanted into the surface of p-type substrate region 2 to form n as shown in FIG. 7(a)⁺And a source region 3.

An insulating layer IL6 covering the plurality of gate electrodes 10 is formed over the insulating layer IL 5. Insulating layer IL6, insulating layer IL5, n⁺A part of each of the source region 3 and the p-type base region 2 is removed to form an opening OP3 reaching the p-type base region 2. P-type impurities are ion-implanted into the p-type substrate regions 2 through the openings OP3, respectively, to form p-type impurities as shown in fig. 7(b)⁺And a type contact region 5.

A metal layer including tungsten is formed over the insulating layer IL6, filling the plurality of openings OP 3. Forming a plurality of n by retreating the upper surface of the metal layer⁺A plurality of p type source regions 3⁺And a plurality of connecting portions 31 respectively connected to the contact regions 5. A metal layer containing aluminum is formed over the insulating layer IL6 and the plurality of connection portions 31. By patterning this metal layer, the source electrode 13 shown in fig. 8(a) and the gate pad 14 not shown are formed.

To n⁺The back surface of the type semiconductor layer 4s is polished until n⁺The semiconductor layer 4s has a predetermined thickness. Then, as shown in FIG. 8(b), at n⁺The drain electrode 11 is formed on the back surface of the type semiconductor layer 4 s. Through the above steps, the semiconductor device 100 shown in fig. 1 to 3 is manufactured.

In the above-described manufacturing process, Chemical Vapor Deposition (CVD) or sputtering may be used for forming each component. For removing a part of each component, wet etching, Chemical Dry Etching (CDE), or Reactive Ion Etching (RIE) may be used. Wet etching, CDE, or Chemical Mechanical Polishing (CMP) may be used for the step-back of the upper surface of each component.

The effect of embodiment 1 will be described.

The semiconductor device 100 according to embodiment 1 includes a 2 nd insulating portion 22 connected to the 1 st insulating portion 21 below the 1 st insulating portion 21. 1 st insulating partThe 21 nd and 2 nd insulating portions 22 are formed by thermal oxidation of a semiconductor or CVD of an oxide as shown in fig. 5 (a). The 1 st insulating portion 21 and the 2 nd insulating portion 22 formed by these methods have a compressive stress. Therefore, when the 1 st insulating part 21 and the 2 nd insulating part 22 are formed, n between the 1 st insulating parts 21 and the 2 nd insulating parts 22 and n between the 2 nd insulating parts 22 are positioned by the compressive stress of the 1 st insulating part 21 and the 2 nd insulating part 22^－The type semiconductor layer 1s is applied with tensile stress in the 1 st direction D1. This tensile stress remains after the completion of the manufacture of the semiconductor device 100. As a result, in the semiconductor device 100 shown in fig. 2, n is located between the 1 st insulating portions 21 and between the 2 nd insulating portions 22^－Tensile strain occurs in the type drift region 1.

When the semiconductor device 100 is in the on state, carriers flow in the 1 st direction D1. In other words, the tensile strain occurs along the direction of carrier flow. If tensile strain occurs along the direction in which carriers flow, the mobility of carriers increases. I.e. by applying a voltage at n^－Type drift region 1 is subjected to tensile strain, and the on-resistance of semiconductor device 100 can be reduced. For example, by providing both the 1 st insulating part 21 and the 2 nd insulating part 22, n can be made smaller than the case where only the 1 st insulating part 21 is provided^－A larger extent of the type drift region 1 is tensile strained.

The length L1 of the 2 nd insulating part 22 in the 1 st direction D1 is greater than n^－The thickness T1 of the 1 st insulating portion 21 between the type drift region 1 and the FP electrode 12 is long. This enables the number n of insulating parts 22 to be set between each other^－The strain occurring in the type drift region 1 becomes large. For example, if the length L1 is shorter than the thickness T1, sufficient tensile strain does not occur in a region away from the 2 nd insulating portion 22, and the improvement in the mobility of carriers is small.

Further, if the 2 nd insulating portion 22 is provided, the path through which the current flows becomes narrow in the region below the 1 st insulating portion 21. In the semiconductor device 100, the length L2 of the 2 nd insulating portion 22 in the 2 nd direction D2 is shorter than 2 times the thickness T1. Thus, n can be made^－Length L4 of 2 nd portion 1b of type drift region 1 to n^－Part 1 of drift region 1Length L5 of 1a is long. This can suppress the width of the current path between the 2 nd insulating portions 22 from becoming narrow even when the 2 nd insulating portions 22 are provided.

That is, according to the relationship among the length L1, the length L2, and the thickness T1, the effect of reducing the on-resistance due to the tensile strain of the 2 nd insulating portion 22 can be made larger than the effect of increasing the on-resistance due to the provision of the 2 nd insulating portion 22. Therefore, the on-resistance of the semiconductor device 100 can be reduced as compared with the case where only the 1 st insulating portion 21 is provided.

Further, if the length L2 is shorter than 2 times the thickness T1, the 2 nd insulating part 22 can be formed at the same time as forming part of the 1 st insulating part 21, as shown in fig. 5 (b). This makes it possible to manufacture the semiconductor device 100 more easily.

The lower end of the 2 nd insulating part 22 may reach n⁺The 2 nd insulating portion 22 is provided in the pattern of the drain region 4. Preferably, the lower end of the 2 nd insulating portion 22 is aligned with the lower end of the n nd insulating portion in the 1 st direction D1 as shown in fig. 2⁺The type drain regions 4 are separated. If the 2 nd insulating part 22 and n⁺When the type drain region 4 is separated, the width of the current path is wider below the 2 nd insulating portion 22. In addition, the formation of the 2 nd insulating portion 22 becomes easy, and the yield of the semiconductor device 100 can be improved.

The following is an example of a preferable size ratio.

The ratio of the length L1 to the length L6 (shown in fig. 3) in the 1 st direction D1 of the FP electrode 12 is 0.5 to 2.0. The ratio of the length L2 to the length L7 in the 2 nd direction D2 of the FP electrode 12 is 0.5 to 2.0. The ratio of the distance Di2 in the 1 st direction D1 between the drain electrode 11 and the 2 nd insulating portion 22 to the distance Di1 (shown in fig. 2) in the 1 st direction D1 between the drain electrode 11 and the p-type base region 2 is 0.1 to 0.5.

If the ratio of the length L1 to the length L6 is too small, the strain generated becomes small, and the effect of reducing the on-resistance becomes small. On the other hand, if the ratio is too large, the width of the current path becomes narrow, and the current path becomes narrow. As a result, the on-resistance increases.

If the ratio of the length L2 to the length L7 is too small, the strain generated becomes small, and the effect of reducing the on-resistance becomes small. On the other hand, if the ratio is too large, the current path becomes narrow and the on-resistance increases.

As for the ratio of the distance Di2 to the distance Di1, if the ratio is too small, the current path becomes narrow and the on-resistance increases. On the other hand, if the ratio is too large, the strain generated becomes small, and the effect of reducing the on-resistance becomes small.

By setting at least one of the ratio of the length L1 to the length L6, the ratio of the length L2 to the length L7, and the ratio of the distance Di2 to the distance Di1 in the above range, the ratio of the decrease in on-resistance due to tensile strain to the increase in on-resistance due to the narrowing of the current path can be made larger. This can further reduce the on-resistance of the semiconductor device 100. Further, when all of the three ratios fall within the above range, the on-resistance can be further reduced.

(modification 1)

Fig. 9 is a perspective cross-sectional view showing a part of a semiconductor device according to modification 1 of embodiment 1.

In the semiconductor device 110 shown in fig. 9, a gap V is provided in at least a part of the plurality of 2 nd insulating portions 22. The void V is a cavity existing inside the 2 nd insulating portion 22. For example, the dimension of the void V in the 1 st direction D1 is longer than the dimension of the void V in the 2 nd direction D2. The gap V may be linear along the 1 st direction D1.

If the gap V is provided, n is applied from the 2 nd insulating part 22^－The stress of type drift region 1 is relaxed. For example, the larger the gap V, the more relaxed the stress. By providing the gap V in the 2 nd insulating portion 22, the effect on n can be adjusted^－The stress of the type drift region 1.

In order to form the void V, for example, an insulating layer IL3 is formed by CVD in the step shown in fig. 5 (a). At this time, by setting the film formation conditions close to the supply rate limit, the deposition rate of the oxide in the vicinity of the upper end of the opening OP2 can be made larger than the deposition rate of the oxide in the middle of the opening OP 2. As a result, the upper end of the opening OP2 is closed in a state where the material is not completely deposited inside the opening OP 2. This enables formation of the void V inside the insulating layer IL3 provided in the opening OP 2.

However, in order to make n at n by the smaller 2 nd insulating part 22^－The drift region 1 is more strained, and preferably, the no void V is formed in the 2 nd insulating portion 22. In order to suppress the formation of the void V, it is preferable that the side of the opening OP2 be inclined with respect to the 1 st direction D1. By inclining the side surface of the opening OP2, the upper end of the opening OP2 can be suppressed from being closed in a state where the material is not completely accumulated inside the opening OP 2. When the side surface of the opening OP2 is inclined with respect to the 1 st direction D1, the length of the 2 nd insulating portion 22 in the 2 nd direction D2 is shorter toward the lower side.

(modification 2)

Fig. 10 is a perspective cross-sectional view showing a part of a semiconductor device according to modification 2 of embodiment 1.

In the semiconductor device 120 shown in fig. 10, a plurality of 2 nd insulating portions 22 are provided under one 1 st insulating portion 21. The plurality of 2 nd insulating parts 22 are separated from each other in the 3 rd direction D3. Therefore, when the semiconductor device 100 is in the on state, carriers can move between the 2 nd insulating portions 22 adjacent to each other in the 3 rd direction D3.

According to the semiconductor device 120 of modification 2, the width of the current path below the 1 st insulating portion 21 can be made wider than that of the semiconductor device 100. Therefore, according to modification 2, the on-resistance can be further reduced.

(embodiment 2)

Fig. 11 is a plan view showing the semiconductor device according to embodiment 2.

Fig. 12 is a plan view showing a portion XII of fig. 11. The source electrode 13, the insulating layer 41, and the insulating layer 42 are omitted in fig. 12.

FIG. 13 is a cross-sectional view XIII-XIII in FIG. 12. FIG. 14 is a cross-sectional view XIV-XIV of FIG. 12. Fig. 15 is a sectional view XV-XV of fig. 12.

The semiconductor device 200 according to embodiment 2 further includes a gate wiring layer 15, a connection portion 32, a connection portion 33, an insulating layer 41, and an insulating layer 42, compared to the semiconductor device 100.

As shown in fig. 12 to 15, in the semiconductor device 200, a plurality of gate electrodes 10, FP electrodes 12, 1 st insulating portions 21, and 2 nd insulating portions 22 are provided in the 2 nd direction D2 and the 3 rd direction D3. As shown in fig. 12, the gate electrode 10 has a ring shape when viewed from the 1 st direction D1. The FP electrode 12 is located inside the gate electrode 10. p-type substrate region 2, n⁺Type source region 3 and p⁺The contact regions 5 are located around the 1 st insulating portions 21 in the 2 nd direction D2 and the 3 rd direction D3.

As shown in fig. 13, the gate wiring layer 15 is provided over the gate electrode 10 with an insulating layer 41 interposed therebetween. The connection portion 32 is provided between the gate electrode 10 and the gate wiring layer 15, and electrically connects the gate electrode 10 and the gate wiring layer 15. The source electrode 13 is provided on the gate wiring layer 15 with an insulating layer 42 interposed therebetween. The connection portion 33 is provided between the FP electrode 12 and the source electrode 13, and electrically connects the FP electrode 12 and the source electrode 13. The connection portion 31 connects n at a position where the gate wiring layer 15 is not provided⁺Type source region 3 and p⁺The type contact region 5 is electrically connected to the source electrode 13.

As shown in fig. 12, a plurality of gate wiring layers 15 are provided in the 3 rd direction D3, and each gate wiring layer 15 extends in the 2 nd direction D2. Each gate wiring layer 15 is provided above the gate electrodes 10 arranged in the 2 nd direction D2, and is electrically connected to the gate electrodes 10 arranged in the 2 nd direction D2. As shown in fig. 13, the source electrode 13 is provided on the plurality of gate wiring layers 15 with an insulating layer 42 interposed therebetween.

The gate pad 14 is provided on the insulating layer 42, for example, as shown in fig. 11, apart from the source electrode 13. The gate wiring layer 15 and the gate pad 14 are electrically connected to each other by a connection portion, not shown, penetrating the insulating layer 42. Alternatively, the gate pad 14 may be disposed over the insulating layer 41. In this case, the gate pad 14 is located below the source electrode 13.

As shown in FIG. 14, in the semiconductor device 200, the length L1 of the 2 nd insulating portion 22 in the 1 st direction D1 is longer than n^－The thickness T1 of the 1 st insulating portion 21 between the type drift region 1 and the FP electrode 12 is long. Length of the 2 nd insulating part 22 in the 2 nd direction D2The degree L2 is shorter than 2 times the thickness T1. Further, as shown in fig. 15, the length L8 in the 3 rd direction D3 of the 2 nd insulating part 22 is shorter than 2 times the thickness T1.

n^－As shown in fig. 14 and 15, the drift region 1 of the type has 1 st to 4 th parts 1a to 1 d. The 1 st portions 1a are located between the 1 st insulating parts 21 adjacent in the 2 nd direction D2. The 2 nd portions 1b are located between the 2 nd insulating parts 22 adjacent in the 2 nd direction D2. The 3 rd portion 1c is located between the 1 st insulating parts 21 adjacent in the 3 rd direction D3. The 4 th part 1D is located between the 2 nd insulating parts 22 adjacent in the 3 rd direction D3.

The length L4 in the 2 nd direction D2 of the 2 nd part 1b is longer than the length L5 in the 2 nd direction D2 of the 1 st part 1 a. The length L9 in the 3 rd direction D3 of the 4 th part 1D is longer than the length L10 in the 3 rd direction D3 of the 3 rd part 1 c.

According to embodiment 2, the gate electrode 10 is provided in plurality in the 2 nd direction D2 and the 3 rd direction D3. According to this structure, when the semiconductor device 200 is in an on state, a channel is formed around each gate electrode 10. Therefore, the area of the channel per unit area can be increased as compared with the semiconductor device 100, and the on-resistance can be further reduced.

Further, as in embodiment 1, by providing the 2 nd insulating part 22 under the 1 st insulating part 21, n between the 2 nd insulating parts 22 can be set to be equal to each other^－The type drift region 1 is tensile strained. Further, length L1 is longer than thickness T1. The lengths L2 and L8 are each shorter than 2 times the thickness T1. According to this relationship, the effect of reducing the on-resistance due to the tensile strain caused by the 2 nd insulating portion 22 can be made larger than the effect of increasing the on-resistance by providing the 2 nd insulating portion 22. Therefore, the on-resistance of the semiconductor device 200 can be reduced as compared with the case where only the 1 st insulating portion 21 is provided.

Further, if the lengths L2 and L8 are shorter than 2 times the thickness T1, respectively, the formation of the 2 nd insulating portion 22 becomes easy, and the yield of the semiconductor device 200 can be improved.

The relative high or low of the impurity concentration between the semiconductor regions in the above-described embodiments can be confirmed, for example, by using SCM (scanning capacitance microscope). The carrier concentration in each semiconductor region can be considered to be equal to the impurity concentration activated in each semiconductor region. Therefore, the relative high or low carrier concentration between the semiconductor regions can also be confirmed using SCM. The impurity concentration in each semiconductor region can be measured by SIMS (secondary ion mass spectrometry), for example.

While the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof. The above embodiments can be combined with each other.