阅读说明：本技术 半导体元件 (Semiconductor device with a plurality of semiconductor chips ) 是由 林时彦 陈冠超 陈璿安 李伦铭 于 2020-01-22 设计创作，主要内容包括：一种半导体元件,包含基板、半导体二维材料层、导电二维材料层、栅极介电层,及栅极电极。半导体二维材料层配置于基板上方。导电二维材料层沿着半导体二维材料层延伸,其中导电二维材料层包含四族元素。栅极介电层沿着半导体二维材料层的沟道区域延伸。栅极电极配置于栅极介电层上。(A semiconductor device includes a substrate, a semiconductor two-dimensional material layer, a conductive two-dimensional material layer, a gate dielectric layer, and a gate electrode. The semiconductor two-dimensional material layer is arranged above the substrate. The conductive two-dimensional material layer extends along the semiconductor two-dimensional material layer, wherein the conductive two-dimensional material layer comprises a group IV element. The gate dielectric layer extends along a channel region of the semiconductor two-dimensional material layer. The gate electrode is disposed on the gate dielectric layer.)

1. A semiconductor device, comprising:

a substrate;

a semiconductor two-dimensional material layer disposed above the substrate;

a conductive two-dimensional material layer extending along the semiconductor two-dimensional material layer, wherein the conductive two-dimensional material layer comprises a group IV element;

a gate dielectric layer extending along a channel region of the semiconductor two-dimensional material layer; and

and a gate electrode disposed on the gate dielectric layer.

Technical Field

The present disclosure relates to a semiconductor device.

Background

The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and designs have resulted in different generations of integrated circuits. Each generation has smaller and more complex circuitry than the previous generation. However, these advances have also increased the complexity of integrated circuits in fabrication and processing.

In the evolution of integrated circuits, the functional density (e.g., the number of interconnected elements per chip area) has increased, while the size (e.g., the smallest element (or line) that can be used in a manufacturing process) has become smaller. This reduced size process provides benefits because it increases process efficiency and reduces associated overhead.

However, as feature sizes continue to shrink, manufacturing processes become more difficult to perform. Therefore, it is a challenge to produce a semiconductor element having a small size and reliability.

Disclosure of Invention

Some embodiments of the present disclosure are a semiconductor device comprising a substrate, a semiconductor two-dimensional material layer, a conductive two-dimensional material layer, a gate dielectric layer, and a gate electrode. The semiconductor two-dimensional material layer is arranged above the substrate. The conductive two-dimensional material layer extends along the semiconductor two-dimensional material layer, wherein the conductive two-dimensional material layer comprises a group IV element. The gate dielectric layer extends along a channel region of the semiconductor two-dimensional material layer. The gate electrode is disposed on the gate dielectric layer.

Drawings

Various aspects of the embodiments of the disclosure can be understood from the following detailed description, taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-8B are schematic diagrams of a portion of an embodiment of the present disclosure illustrating a semiconductor device at various stages of manufacture;

FIG. 9 illustrates a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

wherein, the notation:

100 substrate 110 two-dimensional material layer

110SD source/drain region 110CH channel region

150 mask layer 152 opening

154 opening 160 contact layer

162 separation metal layer, 164 electrode metal layer

160A first portion/two-dimensional material layer 160B second portion

165A source/drain contact 165B source/drain contact

170 gate dielectric layer 180 gate electrode

S101-S108 blocks B-B lines.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter presented herein. A specific example of components and arrangements are described below to simplify the present disclosure. Of course, this example is merely illustrative and not intended to be limiting. For example, the following description of a first feature formed over or on a second feature may, in embodiments, include the first feature being in direct contact with the second feature, and may also include forming additional features between the first and second features such that the first and second features are not in direct contact. Moreover, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below", "lower", "above", "upper", and the like, are used herein to simplify description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms also encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Fig. 1A-8B are schematic diagrams of a portion of a semiconductor device according to various stages of the present disclosure. Although fig. 1A-8B describe one method, it should be understood that the structure of fig. 1A-8B is not intended to be limiting and may be independent of this method. Although fig. 1A-8B depict a series of operations, it should be understood that the operations of fig. 1A-8B are not limited to the order in which the operations may be switched in other embodiments, and that the method may be applied to other structures. In other embodiments, portions of the operations depicted and/or discussed may be omitted, either partially or completely.

Referring to fig. 1A and 1B, fig. 1A is a top view of a semiconductor device, and fig. 1B is a cross-sectional view taken along line B-B of fig. 1A. The initial structure includes a substrate 100. In some embodiments, the substrate 100 may provide mechanical and/or structural support for features subsequently described in fig. 2A-8B. These features or structures may be part of a semiconductor device, such as a transistor, and may be formed on or over the substrate 100.

The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include sapphire (e.g., crystalline Al)₂O₃) Sapphire in a large lattice or single crystal layer, or a coating layer of sapphire. In other examples, the substrate 100 may be a sapphire substrate, such as a transparent sapphire substrate including, for example, α -Al₂O₃. Other exemplary semiconductors include germanium, which may also be used for the substrate 100. Alternatively or additionally, the substrate 100 includes a compound semiconductor such as silicon carbide, gallium arsenide, gallium indium oxide, and/or indium phosphide. In addition, the substrate 100 also includes a silicon-on-insulator (SOI) structure. The substrate 100 may also be other suitable substrates, which may be included in the embodiments of the present disclosure and are not limited thereto. The substrate 100 may include epitaxial layers and/or may be stressed to increase performance. The substrate 100 may also include different doping, such as a P-type substrate and/or an N-type substrate, and doped wells, such as P-wells or N-wells, depending on the design.

Referring to fig. 2A and 2B, fig. 2A is a top view of the semiconductor device, and fig. 2B is a cross-sectional view taken along line B-B of fig. 2A. The first two-dimensional material layer 110 is formed on the substrate 100. In some embodiments, the first two-dimensional material layer 110 directly contacts the substrate 100. Herein, according to a well-accepted definition in the solid-state physics arts, a "two-dimensional material" refers to a crystalline material that includes a single layer composed of multiple atoms. The "two-dimensional material" may also be referred to as a "monolayer" material, according to well-established definitions. In the embodiments of the present disclosure, "two-dimensional material" and "monolayer" may be used interchangeably and are not to be construed differently unless otherwise specified.

The first two-dimensional material layer 110 may be a two-dimensional material and have a suitable thickness. In some embodiments, the two-dimensional material comprises a monolayer of atoms in which the monolayer is one of its monolayer structure materials. The thickness of the two-dimensional material is thus dependent on the number of monolayers, which may be one monolayer or more than one monolayer. The coupling between adjacent two monolayers of a two-dimensional material is van der Waals forces (van der Waals forces), where van der Waals forces are weaker than chemical bonding between atoms between monolayers of a monolayer.

Since the first two-dimensional material layer 110 is provided with a second two-dimensional material layer (e.g., the second two-dimensional material layer 160A of fig. 5B) grown thereon. In some embodiments, the upper surface of the first two-dimensional material layer 110 has no atomic bonds in a vertical direction, or at least a portion of the upper surface of the first two-dimensional material layer 110 for forming the second two-dimensional material layer has no atomic bonds in a vertical direction.

Forming the first two-dimensional material layer 110 includes an appropriate process, which is determined according to the specific first two-dimensional material layer 110 and the substrate 100. In some embodiments, the first two-dimensional material layer 110 includes a Transition Metal Dichalcogenide (TMD) monolayer material. In some embodiments, the transition metal dichalcogenide monolayer includes a layer of transition metal atoms sandwiched between two layers of chalcogenide atoms. The substrate 100 may comprise any substrate suitable for growing a transition metal dichalcogenide thereon. For example, the substrate 100 may be selected to have the ability to withstand the potentially high temperatures at which transition metal dichalcogenides are formed. In some embodiments, the substrate 100 is a sapphire substrate.

In some embodiments, when the first two-dimensional material layer 110 is a transition metal dichalcogenide monolayer, the transition metal dichalcogenide monolayer includes molybdenum disulfide (MoS 2). Molybdenum disulfide may be formed on substrate 100, such as a sapphire substrate, and a suitable method may be used. For example, molybdenum disulfide may be coupled to the substrate 100 by a micro mechanical ablation (micro mechanical ablation) or a molybdenum layer previously deposited on the substrate 100 may be vulcanized.

In other embodiments, when the mo disulfide is formed by a micro-mechanical lift-off process, the first two-dimensional material layer 110 is formed on another substrate and then transferred to the substrate 100. For example, in some embodiments, the two-dimensional material layer is formed on a first substrate by chemical vapor deposition, sputtering, or atomic layer deposition. A polymer layer, such as poly (methyl methacrylate); PMMA, is then formed over the two-dimensional material layer. After the polymer layer is formed, the sample is heated, for example, by placing the sample on a hot plate. After heating, one corner of the two-dimensional material layer can be peeled off from the first substrate, for example, using tweezers, and the sample can be immersed in a solution to facilitate separation of the two-dimensional material layer film and the first substrate. The two-dimensional material layer and the polymer layer are transferred to the substrate 100. The polymer layer is then removed from the two-dimensional material layer using a suitable solvent.

In other embodiments, when the molybdenum disulfide is a molybdenum layer previously deposited on the substrate 100 by sulfidation, the molybdenum layer may be formed on the substrate 100 by a suitable method, such as using RF sputtering in conjunction with a molybdenum target. The sputtering power is maintained at about 35W to about 45W and the background pressure is maintained at about 4.5X 10 during the deposition of the molybdenum layer^-3torr to about 5.5X 10^-3torr, and argon (Ar) flow rate of 35sccm to about 45 sccm. After the molybdenum layer is deposited, the sapphire substrate 100 and the molybdenum layer are removed from the sputtering chamber and exposed to air. The molybdenum layer will be oxidized and form molybdenum oxide. Then, the master is placed in a hot furnace and vulcanization is performed. Before vulcanization, the tube of the furnace is evacuated to 4.5X 10^-3torr to about 5.5X 10^-3the torr to extract gaseous molecules, such as oxygen, from the environment. In the presence of sulfurDuring the formation, the flow rate of argon as carrier gas is about 40sccm to about 200sccm, and the pressure of the furnace is about 0.1Torr to about 10 Torr. The growth temperature of the sample is maintained at about 400 ℃ to about 1200 ℃, wherein the sulfur powder is disposed upstream of the gas flow. About 0.5g to about 2g of sulfur powder is heated in a gas stream to an ambient temperature upstream of the furnace tube of about 120 ℃ to about 200 ℃. During the high temperature growth, the decomposition of molybdenum oxide and the sulfurization reaction will occur simultaneously. If the background sulfur is sufficient, the sulfidation reaction will be the dominant mechanism. Most of the molybdenum oxide surface will be converted to molybdenum sulfide in a short time. In this step, the first two-dimensional material layer 110 may be uniformly formed on the large-area substrate 100. In some embodiments, the first two-dimensional material layer 110 has an area ranging from about 0.1mm²To about 50mm²。

In some embodiments, forming the first two-dimensional material layer 110 also includes processing the first two-dimensional material layer 110 to obtain a desired electrical property of the first two-dimensional material layer 110. These processes include thinning (i.e., reducing the thickness of the first two-dimensional material layer 110), doping, or stressing to allow the first two-dimensional material layer 110 to exhibit certain semiconductor characteristics, such as direct bandgap (direct bandgap). Thinning the first two-dimensional material layer 110 may be achieved by different suitable processes and may be included in embodiments of the present disclosure. For example, a plasma dry etch, such as a reactive-ion etching (RIE), may be used to reduce the number of monolayers in the first two-dimensional material layer 110.

As described herein, the mo sulfide film of the first two-dimensional material layer 110 has semiconductor characteristics (and may be referred to as a semiconductor two-dimensional material layer) as an illustrative example. The thickness of the monomolecular layer of each molybdenum sulfide layer is aboutTo about(e.g. in). In some embodiments, the thickness of the molybdenum sulfide thin film of the first two-dimensional material layer 110 is less than 1.5nm, i.e., equal to or less than two monolayers of molybdenum sulfide. It should also be understood that other transition metal dichalcogenides such As molybdenum diselenide (MoSe 2) or other two-dimensional materials such As group five monolayers of arsenic (As) and phosphorus (α -P) may be possible materials for the first two-dimensional material layer 110.

Referring to fig. 3A and 3B, fig. 3A is a top view of the semiconductor device, and fig. 3B is a cross-sectional view taken along line B-B of fig. 3A. The first two-dimensional material layer 110 is patterned. In some embodiments, the patterning process includes a photolithography process and an etching process to remove a portion of the first two-dimensional material layer 110.

Referring to fig. 4A and 4B, fig. 4A is a top view of the semiconductor device, and fig. 4B is a cross-sectional view taken along line B-B of fig. 4A. The mask layer 150 is formed on the substrate 100 and the first two-dimensional material layer 110. In some embodiments, the masking layer 150 is patterned with openings 152 and 154 that expose a portion of the upper surface of the first two-dimensional material layer 110. In some embodiments, the mask layer 150 is a photoresist material. In some embodiments, the portion of the first two-dimensional material layer 110 exposed through the openings 152 and 154 may be referred to as a source/drain region 110SD, and the portion between the source/drain regions 110SD may be referred to as a channel region 110 CH.

In some embodiments, the masking layer 150 may be formed by depositing a photoresist layer on the substrate 100 by a suitable process, such as a spin-on technique, which includes baking the photoresist layer after coating. The photoresist layer may comprise a positive photoresist material or a negative photoresist material. For example, the photoresist layer may comprise polymethyl methacrylate. Subsequently, the photoresist layer is exposed. For example, the photoresist layer is exposed to radiation energy, such as extreme ultraviolet radiation, through a mask (photoresist) having a predetermined pattern, such as the pattern defining openings 152 and 154, which is then patterned. The radiation energy may be krypton fluoride (KrF) laser or argon fluoride (argon fluoride; ArF) laser. Then, the photoresist layer can be subjected to a post-exposure baking process. The photoresist layer is then developed by a suitable process. For example, the photoresist layer is exposed to a developer, such as tetramethylammonium hydroxide (TMAH), to remove portions of the photoresist layer to form openings 152 and 154 exposing the upper surface of the first two-dimensional material layer 110. Then, a cleaning process, such as a deionized water cleaning, may be performed. The patterned photoresist layer is the mask layer 150.

Referring to fig. 5A and 5B, fig. 5A is a top view of the semiconductor device, and fig. 5B is a cross-sectional view taken along line B-B of fig. 5A. A contact layer 160, a separation metal layer 162, and an electrode metal layer 164 are sequentially formed within the openings 152 and 154. In addition, a contact layer 160, a separation metal layer 162, and an electrode metal layer 164 are also formed on the upper surface of the mask layer 150.

In some embodiments, the contact layer 160 includes a first portion 160A located in the openings 152 and 154 and extending along the source/drain regions 110SD of the first two-dimensional material layer 110, and a second portion 160B located on the mask layer 150 and extending along the upper surface of the mask layer 150. In some embodiments, the first portion 160A and the second portion 160B are composed of the same material, however the first portion 160A and the second portion 160B have different crystalline structures. For example, the first portion 160A of the contact layer 160 has a two-dimensional structure, and the second portion 160B of the contact layer 160 has a three-dimensional structure. In some embodiments, the first portion 160A of the contact layer 160 is thinner than the separation metal layer 162 and the electrode metal layer 164. In some embodiments, the first portion 160A of the contact layer 160 is thinner than the first two-dimensional material layer 110. Herein, "three-dimensional structure" refers to a structure having atoms regularly arranged in three dimensions and may be represented by repeating units, wherein a unit means the smallest three-dimensional repeating unit that can be used to represent the complete crystalline structure. On the other hand, a "two-dimensional structure" refers to a structure having atoms regularly arranged in two dimensions.

In some embodiments, the contact layer 160 may be formed by a thermal evaporation process (hermal evaporation). The pressure of the system was maintained at about 5x10 during the thermal evaporation process^-7torr to about 7x10^-7torr (e.g., 6x 10)^-7 torr) and a deposition rate of aboutSec to aboutThe output of the second phase is measured in/sec (for example,sec). In some embodiments, the contact layer 160 is formed at a temperature of about 25 ℃ (room temperature) to about 500 ℃. If the temperature is higher than 500 deg.c, the two-dimensional crystalline structure of the first two-dimensional material layer 110, for example, molybdenum sulfide, may be broken due to the high temperature. Further, if the temperature is below 25 ℃, the quality of the second two-dimensional material layer 160 will not be satisfactory.

In some embodiments, the contact layer 160 may be formed by a molecular beam epitaxy process or electron gun evaporation. The sample may be moved into the molecular beam epitaxy system to form the contact layer 160. Molecular beam epitaxy is performed in a high vacuum or extreme vacuum environment. The deposition rate of molecular beam epitaxy allows the film to grow epitaxially. Such deposition rates require a correspondingly better vacuum environment to achieve the same doping levels as other deposition techniques. Such as an extreme vacuum environment without entrained gases, can also result in a high purity grown film. Therefore, by the molecular beam epitaxy process, the contact layer 160 having a single element can be achieved.

In some embodiments, the second two-dimensional material layer 160A includes a group iv material, such as germanium (De), tin (Sn), lead (Pb), and the like. In some embodiments, the second two-dimensional material layer 160A behaves like a topological insulator (topologic insulator), but has superconducting properties at its edges at room temperature. In particular, germenene or stannene is a two-dimensional structural allotrope of germanium and tin, respectively. Topological insulators are characterized by an insulator inside, but by a conductor characteristic at their boundary portions (e.g., the surface of a block or the edge of a thin film), which means that carriers can only move along the material boundary. In particular, the topological-like insulator exhibited by tin (stannene) in two dimensions has superconducting properties at the edges of stannene at room temperature, which allows the second two-dimensional material layer 160A to serve as a possible source/drain material (and thus may be referred to herein as a conductive two-dimensional material layer). In some embodiments, the first two-dimensional material layer 110 and the second two-dimensional material layer 160A have different materials. For example, the first two-dimensional material layer 110 may be molybdenum sulfide, and the second two-dimensional material layer 160A may be germanium-ene, tin-ene, or other two-dimensional materials of group iv elements.

In some embodiments, when the second two-dimensional material layer 160A is tin alkene, each monolayer of the second two-dimensional material layer 160A has a thickness of aboutTo aboutFor example, the thickness of the monolayer of stannene is about one hundred meters (HRTEM) as detected by a High Resolution Transmission Electron Microscope (HRTEM)Alternatively, the thickness of the tin alkene monolayer may be estimated from two peaks of a curve of the tin alkene monolayer detected by X-ray diffraction (XRD) and inferred through Bragg's law (n λ ═ 2d sin θ), and the thickness of the tin alkene monolayer is estimated to be aboutIn some embodiments, the thickness of the layer of tin alkene second two-dimensional material 160A is less than about 50nm, i.e., equal to or less than 170 layers of tin alkene monolayers.

In some embodiments, when the second two-dimensional material layer 160A is germanium alkene, each monolayer of the second two-dimensional material layer 160A has a thickness of aboutTo aboutFor example, the thickness of the germanium-ene monolayer is aboutAlternatively, the thickness of the germanium alkene monolayer may be estimated from two peaks of a curve of the tin alkene monolayer detected by X-ray diffraction (XRD) and inferred through Bragg's law (n λ ═ 2d sin θ), and the thickness of the germanium alkene monolayer is estimated to be aboutIn some embodiments, the thickness of the second two-dimensional material layer 160A of germanene is less than about 50nm, i.e., equal to or less than 150 monolayers of germanene.

In some embodiments, the first portion 160A of the contact layer 160 tends to form a two-dimensional crystalline structure on the first two-dimensional material layer 110. The coupling between the layers due to van der waals forces is between the layers in the direction of the plane of penetration (i.e., the direction perpendicular to the largest surface of the two-dimensional material layer). Therefore, there is no chemical bond between the first two-dimensional material layer 110 and the first portion 160A of the contact layer 160. Van der waals forces between a two-dimensional material and another two-dimensional material are not affected by lattice mismatch between the two-dimensional materials (e.g., the first two-dimensional material layer 110 and the second two-dimensional material layer 160A). Accordingly, this allows the second two-dimensional material layer 160A to be formed on the first two-dimensional material layer 110 (e.g., a two-dimensional material of molybdenum sulfide) in a large area. Furthermore, selective growth methods, such as molecular beam epitaxy, may also be used.

On the other hand, since the mask layer is made of a polymer material, such as polymethyl methacrylate, it is not a two-dimensional material layer. Therefore, the second portion 160B of the contact layer 160 tends to be formed on the mask layer in the form of a three-dimensional crystalline structure. In some embodiments, second portion 160B includes a group four material such as germanium, tin, lead, and the like.

In some embodiments, the separation metal layer 162 is used to separate the second two-dimensional material layer 160A and the electrode metal layer 164, so that the electrode metal layer 164 does not contact the second two-dimensional material layer 160A. In some embodiments, if the separation metal layer 162 is omitted, the second two-dimensional material layer 160A will extend over the electrode metal layer 164. However, the electrode metal layer 164 may be alloyed with the second two-dimensional material layer 160A at the time of deposition, which may destroy the two-dimensional crystalline structure of the second two-dimensional material layer 160A. Without the two-dimensional crystalline structure, the contact resistance may increase to an unsatisfactory value. Therefore, the material of the separation metal layer 162 is selected to be a material that does not form an alloy with the second two-dimensional material layer 160A. In some embodiments, the material of the separation metal layer 162 is aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), tungsten (W), or other suitable metals. The deposition of the separated metal layer 162 of the above-mentioned materials will not form an alloy with the second two-dimensional material layer 160A.

In some embodiments, the electrode metal layer 164 may be formed of a suitable conductive material, such as polysilicon, graphene, and one or more layers of metals, such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), nickel (Ni), manganese (Mg), silver (Ag), palladium (Pd), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum (Pt), zirconium (Zr), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, or combinations thereof. In other embodiments, the electrode metal layer 164 may include a material that can be alloyed with the second two-dimensional material layer 160A, such as indium (In), lead (Pb), copper (Cu), silver (Ag), gold (Au), nickel (Ni), platinum (Pt), cobalt (Co), rhodium (Rh), iron (Fe), ruthenium (Ru), manganese (Mn), molybdenum (Mo), vanadium (V), titanium (Ti), zirconium (Zr), hafnium (Hf), and magnesium (Mg). In some embodiments, the electrode metal layer 164 may be referred to as a source/drain contact.

In some embodiments, the separation metal layer 162 and the electrode metal layer 164 may be formed by a suitable process, such as a multi-chamber physical vapor deposition system. In other embodiments, low temperature sputtering may be used to form the separation metal layer 162 and the electrode metal layer 164. In some embodiments, the mask layer 150 is substantially thicker than the stack of the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164, so that the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164 in the openings 152 and 154 can be separated from the separation metal layer 162 and the electrode metal layer 164 on the mask layer 150.

Referring to fig. 6A and 6B, fig. 6A is a top view of the semiconductor device, and fig. 6B is a cross-sectional view taken along line B-B of fig. 6A. The mask layer 150 is removed and the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164 remain on the upper surface of the first two-dimensional material layer 110. In detail, the second portion 160B of the contact layer 160 and the separation metal layer 162 and the electrode metal layer 164 thereon are removed together with the mask layer 150. After the mask layer 150 is removed, a first source/drain contact 165A and a second source/drain contact 165B are formed. In some embodiments, first source/drain contact 165A and second source/drain contact 165B include a second two-dimensional material layer 160A, a separation metal layer 162, and an electrode metal layer 164, respectively.

The second two-dimensional material layer 160A and the first two-dimensional material layer 110 of the first source/drain contact 165A and the second source/drain contact 165B are in direct contact. In some embodiments, the contact resistance between the second two-dimensional material layer 160A and the first two-dimensional material layer 110 is smaller than the contact resistance between the metal and the first two-dimensional material layer 110. Therefore, by using a source/drain contact having a two-dimensional material layer disposed on a source/drain region of the two-dimensional material layer, the contact resistance between the source/drain contact and the source/drain region is reduced and the device performance is enhanced.

In some embodiments, the process of fig. 5A-6B may be referred to as a lift-off process. For example, the substrate 100 may be immersed in a suitable solvent in a container that reacts with the mask layer 150. The mask layer 150 expands, dissolves, and leaves the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164 on the first two-dimensional material layer 110. And the completed structure is shown in figures 6A and 6B.

In some embodiments, since the patterns of the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164 are defined by the same mask layer 150, the edges (or sidewalls) of the second two-dimensional material layer 160A, the separation metal layer 162, and the electrode metal layer 164 are substantially vertically aligned and adjacent and collinear.

Any remaining masking layer 150 may optionally be removed via other solvents or suitable plasma chemistries to control the density of defects. Suitable solvents are, for example, xylene (xylene) and methyl iso-butyl ketone (MIBK). In some embodiments, the process may be accompanied by agitation in an ultrasonic bath to improve unwanted metallization during lift-off.

Referring to fig. 7A and 7B, fig. 7A is a top view of the semiconductor device, and fig. 7B is a cross-sectional view taken along line B-B of fig. 7A. A gate dielectric layer 170 is formed on the channel region 110CH, the first source/drain contact 165A, and the second source/drain contact 165B of the first two-dimensional material layer 110. In some embodiments, the gate dielectric layer 170 extends over a portion of the upper surface of the first and second source/drain contacts 165A, 165B, while exposing another portion of the upper surface of the first and second source/drain contacts 165A, 165B. In some embodiments, the gate dielectric layer 170 extends over the sidewalls of the first and second source/drain contacts 165A, 165B. In some embodiments, the gate dielectric layer 170 extends completely over the surface of the first two-dimensional material layer 110 between the first source/drain contact 165A and the second source/drain contact 165B.

The gate dielectric layer 170 may be blanket formed on the substrate 100 by, for example, depositing a dielectric material layer and performing a patterning process to remove a portion of the dielectric material layer. The completed structure is shown in fig. 7A and 7B.

The gate dielectric layer 170 comprises silicon oxide, silicon oxynitride, combinations thereof, or other suitable materials. In some embodiments, the gate dielectric layer 170 comprises a high dielectric constant material (high-k). The high dielectric constant material comprises metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, aluminum oxide, hafnium oxide-aluminum (HfO 2-Al)₂O₃) Alloys, other suitable materials, or combinations thereof. The high dielectric constant material comprises hafnium oxide(HfO₂) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or combinations thereof. The gate dielectric layer 170 may be formed by chemical vapor deposition or other suitable techniques.

Referring to fig. 8A and 8B, fig. 8A is a top view of the semiconductor device, and fig. 8B is a cross-sectional view taken along line B-B of fig. 8A. A gate electrode 180 is formed on the gate dielectric layer 170. The gate electrode 180 may be formed of a conductive material including polysilicon, graphene, and one or more layers of a metal such as aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), nickel (Ni), manganese (Mg), silver (Ag), palladium (Pd), rhenium (Re), iridium (Ir), ruthenium (Ru), platinum (Pt), zirconium (Zr), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, a metal alloy, other suitable materials, or a combination thereof. The gate electrode 180 may be formed by one or more deposition processes, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, electroplating, and/or other suitable methods, accompanied by one or more etching processes to pattern the deposited material of the gate electrode 180.

Fig. 9 illustrates a method M1 for fabricating a semiconductor device according to some embodiments of the present disclosure. Although method M1 is described as a series of acts or steps, it should be understood that the method is not limited by the acts or the order of acts. Thus, in some embodiments, these operations or steps may be performed in a different order, and/or simultaneously. In addition, in some embodiments, a described operation or step may be divided into multiple operations or steps, which may be performed at different times or at the same time with other operations or sub-operations. In some embodiments, described operations or steps may be omitted, or other operations or steps not described may be included.

In block S101, an initial structure including a substrate is provided. Fig. 1A and 1B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S101.

In block S102, a first two-dimensional material layer is formed on a substrate. Fig. 2A and 2B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S102.

In block S103, the first two-dimensional material layer is patterned. Fig. 3A and 3B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S103.

At block S104, a mask layer having first and second openings is formed over the substrate and the first two-dimensional material layer. Fig. 4A and 4B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S103.

In block S105, a second two-dimensional material layer, a separation metal layer, and an electrode metal layer are sequentially formed within the first and second openings. Fig. 5A and 5B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S105.

In block S106, the mask layer is removed to form first and second source/drain contacts, wherein each of the first and second source/drain contacts includes a second two-dimensional material layer, a separate metal layer, and an electrode metal layer, respectively. Fig. 6A and 6B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S106.

In block S107, a gate dielectric layer is formed over the first two-dimensional material layer and the first and second source/drain contacts. Fig. 7A and 7B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S107.

At block S108, a gate electrode is formed on the gate dielectric layer. Fig. 8A and 8B depict a top view and a cross-sectional view, respectively, of a portion of an embodiment of block S108.

From the above discussion, it can be seen that some embodiments of the present disclosure provide advantages. It is to be understood, however, that these embodiments may provide additional advantages, and that not all advantages need be discussed herein, and that not all embodiments have a particular advantage. One advantage is that source/drain contacts having two-dimensional conductive layers of material are formed over source/drain regions of the two-dimensional layer of material, which reduces contact resistance between the source/drain contacts and the source/drain regions of the two-dimensional layer of material and improves device performance. Another advantage includes an increased reliability of the device, since the two-dimensional material of the source/drain contacts is performed at a temperature that does not damage the two-dimensional crystalline structure of the two-dimensional material layer.

Some embodiments of the present disclosure include a semiconductor device comprising a substrate, a semiconductor two-dimensional material layer, a conductive two-dimensional material layer, a gate dielectric layer, and a gate electrode. The semiconductor two-dimensional material layer is arranged above the substrate. The conductive two-dimensional material layer extends along the semiconductor two-dimensional material layer, wherein the conductive two-dimensional material layer comprises a group IV element. The gate dielectric layer extends along a channel region of the semiconductor two-dimensional material layer. The gate electrode is disposed on the gate dielectric layer.

According to some embodiments, the group IV element is Sn-rare or Ge-ene.

According to some embodiments, wherein the layer of semiconducting two-dimensional material comprises molybdenum sulfide.

According to some embodiments, the two-dimensional conductive material layer further includes a separation metal layer extending along an upper surface of the two-dimensional conductive material layer and an electrode metal layer extending along an upper surface of the separation metal layer.

According to some embodiments, wherein the separation metal layer comprises aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), tungsten (W).

According to some embodiments, wherein the gate dielectric layer further extends along sidewalls of the conductive two-dimensional material, sidewalls of the separation metal layer, and sidewalls of the electrode metal layer.

According to some embodiments, the gate dielectric layer further extends along an upper surface of the electrode metal layer.

According to some embodiments, the conductive two-dimensional material is thinner than the discrete metal layers.

According to some embodiments, the conductive two-dimensional material is thinner than the semiconductor two-dimensional material.

Some embodiments of the present disclosure include a semiconductor device comprising a substrate, a semiconductor two-dimensional material layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The semiconductor two-dimensional material layer is arranged above the substrate. The source/drain contact includes a bottom layer extending along the source/drain region of the semiconductor two-dimensional material layer, wherein the bottom layer of the source/drain contact is comprised of a two-dimensional allotrope of a group-four element. The gate dielectric layer extends along a channel region of the semiconductor two-dimensional material layer. The gate electrode is disposed on the gate dielectric layer.

According to some embodiments, the source/drain contact comprises an intermediate layer extending along the top surface of the bottom layer, and the intermediate layer is comprised of a metal that is not alloyed with the two-dimensional allotrope of the group IV element.

According to some embodiments, the source/drain contact comprises an upper layer extending along an upper surface of the intermediate layer, and the upper layer is comprised of a different metal than the intermediate layer.

According to some embodiments, wherein the sidewalls of the upper layer and the sidewalls of the bottom layer are substantially collinear.

According to some embodiments, the metal of the intermediate layer comprises aluminum (Al), bismuth (Bi), cadmium (Cd), chromium (Cr), iridium (Ir), niobium (Nb), tantalum (Ta), tellurium (Te), tungsten (W).

According to some embodiments, wherein the sidewalls of the middle layer and the sidewalls of the bottom layer are substantially collinear.

Some embodiments of the present disclosure include a method comprising forming a first two-dimensional material layer over a substrate; forming a mask layer over the first two-dimensional material layer; patterning the mask layer to form an opening exposing the first two-dimensional material layer; forming a layer of a group-IV element on the mask layer and within the opening, wherein the group-IV element layer includes a first portion extending along an upper surface of the first two-dimensional material layer and a second portion extending along an upper surface of the mask layer; removing the mask layer and a second portion of the layer of group IV elements; forming a gate dielectric layer over the first two-dimensional material layer; forming a gate electrode over the gate dielectric layer.

According to some embodiments, wherein the first portion of the group IV element layer has a two-dimensional crystalline structure and the second portion of the group IV element layer has a three-dimensional crystalline structure.

According to some embodiments, the gate dielectric layer is formed such that the gate dielectric layer contacts the first portion of the layer of group iv elements.

According to some embodiments, the first portion of the layer comprised of a group iv element comprises wustite and germylene.

According to some embodiments, the method further comprises forming a separate metal layer over the group iv element layer and not alloyed with the group iv element layer; and forming an electrode metal layer over the separation metal layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.