阅读说明：本技术 半导体器件及其形成方法 (Semiconductor device and method of forming the same ) 是由 林政明 杨世海 方子韦 徐志安 赵皇麟 于 2020-04-14 设计创作，主要内容包括：本公开涉及一种半导体器件,其包括衬底以及位于衬底上的第一间隔件和第二间隔件。半导体器件还包括位于第一间隔件和第二间隔件之间的栅极堆叠。栅极堆叠包括栅极介电层,具有形成在衬底上的第一部分和形成在第一间隔件和第二间隔件上的第二部分；内部栅极,形成在栅极介电层的第一部分和第二部分上；铁电介电层,形成在内部栅极上并且与栅极介电层接触；以及栅电极,位于铁电介电层上。本公开的实施例还涉及形成半导体器件的方法。(The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack located between the first spacer and the second spacer. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first spacer and the second spacer; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer. Embodiments of the present disclosure also relate to methods of forming semiconductor devices.)

1. A semiconductor device, comprising:

a substrate;

a first spacer and a second spacer on the substrate; and

a gate stack between the first spacer and the second spacer, the gate stack comprising:

a gate dielectric layer comprising a first portion on the substrate and a second portion on the first and second spacers;

an internal gate on the first and second portions of the gate dielectric layer;

a ferroelectric dielectric layer on the internal gate and in contact with the gate dielectric layer; and

a gate electrode on the ferroelectric dielectric layer.

2. The semiconductor device of claim 1, wherein the semiconductor device comprises a Negative Capacitance Field Effect Transistor (NCFET) device.

3. The semiconductor device of claim 1, wherein the semiconductor device comprises a ferroelectric field effect transistor (FeFET) device.

4. The semiconductor device of claim 1, further comprising a fin on the substrate, wherein the gate stack is on the fin.

5. The semiconductor device of claim 1, wherein the ferroelectric dielectric layer is between the internal gate and the gate electrode.

6. The semiconductor device of claim 1, wherein the ferroelectric dielectric layer is between the second portion of the gate dielectric layer and the gate electrode.

7. The semiconductor device of claim 1, wherein the ferroelectric dielectric layer is in physical contact with the second portion of the gate dielectric layer through a nonlinear surface.

8. The semiconductor device of claim 1, wherein the second portion of the gate dielectric layer has a non-linear surface.

9. A method of forming a semiconductor device, comprising:

forming a first spacer and a second spacer;

depositing a gate dielectric layer between and on sidewalls of the first and second spacers;

forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes:

forming a first metal layer on the gate dielectric layer; and

selectively depositing a second metal layer on the first metal layer;

depositing a ferroelectric dielectric layer on the internal gate and the gate dielectric layer; and

forming a gate electrode on the ferroelectric dielectric layer.

10. A method of forming a semiconductor device, comprising:

forming a fin;

forming a first spacer and a second spacer on the fin;

depositing a gate dielectric layer on the fins and on sidewalls of the first and second spacers;

forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes:

depositing a first metal layer on the gate dielectric layer;

forming a barrier layer on a portion of the first metal layer;

removing a portion of the first metal layer not covered by the barrier layer;

removing the barrier layer; and

selectively depositing a second metal layer on the first metal layer;

etching back the grid dielectric layer;

depositing a ferroelectric dielectric layer on the internal gate and the gate dielectric layer; and

forming a gate electrode on the ferroelectric dielectric layer.

Technical Field

Embodiments of the invention relate to semiconductor devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in several generations of ICs, each of which has smaller, more complex circuits than the previous generation. In the course of IC evolution, functional density (e.g., the number of interconnected devices per chip area) generally increases while geometry (e.g., the smallest feature or line that can be created using a fabrication process) decreases. Such a scaled-down process generally provides benefits by increasing production efficiency and reducing associated costs.

Disclosure of Invention

An embodiment of the present invention provides a semiconductor device including: a substrate; a first spacer and a second spacer on the substrate; and a gate stack located between the first spacer and the second spacer,

the gate stack includes: a gate dielectric layer including a first portion on the substrate and a second portion on the first spacer and the second spacer; an internal gate on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Embodiments of the present invention also provide a method of forming a semiconductor device, including: forming a first spacer and a second spacer; depositing a gate dielectric layer between and on sidewalls of the first and second spacers; forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes: forming a first metal layer on the gate dielectric layer; and selectively depositing a second metal layer on the first metal layer; depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer; and forming a gate electrode on the ferroelectric dielectric layer.

Embodiments of the present invention also provide a method of forming a semiconductor device, including: forming a fin; forming a first spacer and a second spacer on the fin; depositing a gate dielectric layer on the fins and on sidewalls of the first and second spacers; forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes: depositing a first metal layer on the gate dielectric layer; forming a barrier layer on a portion of the first metal layer; removing the part of the first metal layer which is not covered by the barrier layer; removing the barrier layer; and selectively depositing a second metal layer on the first metal layer; etching back the grid dielectric layer; depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer; and forming a gate electrode on the ferroelectric dielectric layer.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a cross-sectional view of a semiconductor device incorporating a ferroelectric dielectric material in accordance with some embodiments.

Fig. 2 is a flow diagram of a method for forming a selectively deposited internal gate, in accordance with some embodiments.

Fig. 3A-3E are cross-sectional views of semiconductor structures according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "lower," "below," "over," "upper," etc.) may be used herein to readily describe one element or component's relationship to another element(s) or component as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The acronym "FET," as used herein, refers to a field effect transistor. One example of a FET is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). MOSFETs may, for example, be (i) planar structures built in and on a planar surface of a substrate, such as a semiconductor wafer, or (ii) planar structures built with vertical structures.

The term "FinFET" refers to a FET formed over a fin that is oriented vertically with respect to the planar surface of the wafer.

"S/D" refers to the source and/or drain junctions that form the two terminals of the FET.

The term "perpendicular" as used herein refers to nominally perpendicular to the surface of the substrate.

The term "nominal" as used herein refers to a desired or target value and values above and/or below the desired value set at the design stage of a product or process for a characteristic or parameter of a component or process operation. The range of values is typically due to slight variations in manufacturing processes or tolerances.

The terms "about" and "substantially" as used herein refer to a value of a given quantity that may vary based on the particular technology node associated with the subject semiconductor device. In some embodiments, the terms "about" and "substantially" may, for example, indicate a change within 5% of a given number of values (e.g., ± 1%, ± 2%, ± 3%, ± 4%, ± 5% of the values), based on the particular technology node.

The terms "vertical direction" and "horizontal direction" refer to the z-direction and x-direction, respectively, as shown in the figures herein.

The performance and scalability of silicon-based transistors is approaching limits. For example, as device dimensions scale down to achieve higher packing densities, scaling silicon-based transistors becomes more challenging. Field Effect Transistor (FET) devices may be used to address these challenges due to their compact form factor and improved performance, such as drive current enhancement and sub-threshold leakage reduction. The FET device may be a metal oxide semiconductor FET (mosfet).

Fin field effect transistors (finfets) utilize a vertical device structure. A channel region of the finFET is formed in a fin protruding from a substrate, and a gate structure is disposed over sidewalls and a top surface of the fin. A gate structure that wraps around the channel has the benefit of controlling the channel region, for example, from three sides. Although finfets may exhibit improved performance, they also face challenges such as high sub-threshold swing (SS).

FET to reduce power supply (e.g. V) incorporating Negative Capacitance (NC) technology (NCFET)_DD) A feasible solution is provided and a low SS for low power consumption operation is achieved. SS generally describes the amount of voltage required to turn the device on and off, and thus can affect the operating speed of the device. In particular, the use of ferroelectric high-k dielectric materials allows devices (e.g., FETs) to operate in a negative capacitance state (e.g., in a negative capacitance FET or NCFET) to improve device performance. In one such example, ferroelectric high-k dielectric materials allow for the formation of FETs with SS reduction. In many cases, other factors are constant, and decreasing SS generally increases the switching speed of the FET. SS can be controlled by the degree of ferroelectricity of the gate dielectric material included in the gate stack, with higher ferroelectricity being associated with lower SS. In addition, the ferroelectric high-k dielectric material can also enlarge the memory window to improve the nonvolatile memory deviceThe performance of (c). It is noted that dielectric materials having similar compositions (e.g., all hafnium-based high-k dielectric materials) can have different degrees of ferroelectricity, depending on their particular crystalline phases (e.g., distinguished by different spatial groups). In a device such as HfO₂In the example of the hafnium-based high-k dielectric material of (2), the ferroelectric orthorhombic phase Pca2₁Has greater ferroelectricity than its opposite orthorhombic phase.

The negative capacitance in the NCFET can be realized by integrating a ferroelectric capacitor. Specifically, in the NCFET, a negative capacitor having a ferroelectric material is connected in series to the gate of the FET. The ferroelectric negative capacitor may be a separate capacitor connected to the gate of the FET by a conductive layer (e.g., a line/contact). In some embodiments, one electrode of the negative capacitor is a gate electrode of the MOSFET.

One type of NCFET is a metal-insulator-metal (MIM) NCFET, in which an internal gate electrode is interposed between a ferroelectric gate dielectric layer and a non-ferroelectric gate dielectric layer in a gate stack. Suitable high-k dielectric materials (e.g., gate dielectric layers having a dielectric constant greater than 3.9) can be used as the non-ferroelectric gate dielectric layer in the NCFET. A work function adjusting metal may be formed over the ferroelectric dielectric layer to adjust a work function of the transistor. MIM NCFETs offer many benefits but also present challenges. First, forming the internal gate electrode and work function layer results in an increase in the thickness of the gate stack and makes it challenging to form the gate structure in a high aspect ratio trench during the replacement gate process. Second, the increased thickness also results in a reduced gate contact area, which may increase contact resistance. Third, parasitic capacitance in the gate structure can cause gate leakage, thereby degrading device performance. Fourth, for MIM NCFET devices, the gate electrode and the internal gate may form a ferroelectric capacitor using the ferroelectric layer as a capacitor dielectric, and the channel region and the internal gate may form a high-k capacitor using the high-k gate dielectric as a capacitor dielectric. Mismatch between the first capacitor and the second capacitor may also degrade device performance.

Various embodiments according to the present disclosure provide methods for forming selectively grown internal gates for transistor devices. In some embodiments, the transistor device may be a finFET, NCFET, nanosheet device, nanowire device, and/or other suitable device. The internal gate may include one or more layers. For example, the internal gate may include a seed layer and a metal layer selectively grown on the seed layer. A selectively grown internal gate may provide the following benefits: (i) reducing parasitic capacitance by incorporating horizontal internal gates, which in turn reduces gate leakage; (ii) modulating the gate area by etching back the high-k dielectric layer; (iii) device performance is improved by matching the capacitance of the ferroelectric capacitor and the high-k capacitor; and (iv) homogenizing the electric field across the ferroelectric layer in the channel region of the transistor device by gate area modulation.

Fig. 1 illustrates a cross-sectional view of a semiconductor device 100 incorporating an internal gate, in accordance with some embodiments. In some embodiments, the semiconductor device 100 may be a vertical FET device. The replacement gate process includes forming an opening in the ILD 109 layer after removing the sacrificial polysilicon. Replacement metal gates are used in scaled finFET-based devices to improve circuit performance. For example, a metal gate electrode may replace a polysilicon gate electrode to achieve reduced gate leakage and improved drive current. One process for implementing a metal gate is referred to as a "gate last" or "replacement gate" process. Such processes include forming a sacrificial polysilicon gate, performing various processes associated with the semiconductor device to remove the sacrificial gate to form a trench or opening, and depositing a metal gate material in the trench or opening to form a metal gate.

As shown in fig. 1, a gate stack is formed between opposing sidewall surfaces of ILD 109 and the top surface of semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 may be a fin of a vertical transistor device. In fig. 1, the high-k dielectric layer 102, the internal gate 103, the ferroelectric dielectric layer 105, and the gate electrode 107 are collectively referred to herein as a "metal gate stack" and are located above the semiconductor substrate 101. Spacers 110 are formed on the sidewalls of the metal gate stack to facilitate subsequent source/drain alignment operations. As shown in fig. 1, the high-k dielectric layer 102, the internal gate 103, and the ferroelectric dielectric layer 105 line between the semiconductor substrate 101 and the gate electrode 107 and also between the spacer 110 and the gate electrode 107. In some embodiments, the semiconductor device 100 may further include a liner layer, a seed layer, an adhesion layer, a barrier layer, a work function layer, or an equivalent thereof, in addition to the layers described above.

A pair of source/drain (S/D)108 is formed in the semiconductor substrate 101, and a distance between the source and the drain of the S/D108 is a gate length L_g. In some embodiments, the gate length L of the semiconductor device 100_gAnd may be about 16 nm. In some embodiments, the gate length L_gAnd may be less than about 16 nm. In some embodiments, the gate length L_gAnd may be greater than about 16 nm. In some embodiments, the gate length L_gMay depend on the technology node. For example, the gate length L_gAnd may be about 7nm or about 5 nm. In some embodiments, a p-type or n-type work function layer may be formed between the gate electrode 107 and the substrate 101 to provide various threshold voltages for the semiconductor device 100. The S/D108 may be doped with p-type or n-type dopants, depending on the type of device being formed and not described in detail herein for simplicity.

The semiconductor substrate 101 may be a bulk semiconductor substrate on which various layers and device structures are formed. In some embodiments, the semiconductor substrate 101 may comprise silicon or a compound semiconductor, such as gallium arsenide (GaAs), indium phosphide (InP), silicon germanium (SiGe), silicon carbide (SiC), other suitable semiconductor materials, and/or combinations thereof. In some embodiments, various layers may be formed on the semiconductor substrate 101, such as dielectric layers, doped layers, polysilicon layers, conductive layers, other suitable layers, and/or combinations thereof. In some embodiments, various devices, such as transistors, resistors, capacitors, other suitable devices, and/or combinations thereof, may be formed on the semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 may be a fin of a vertical transistor device. In some embodiments, the semiconductor substrate 101 may be a device layer including other suitable devices.

ILD 109 may comprise a dielectric material. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, spin-on glass (SOG), Fluorinated Silicate Glass (FSG), carbon doped silicon oxide (e.g., SiCOH), amorphous carbon fluoride, parylene, bis-benzocyclobutene, polyimide, other suitable porous polymer material, other suitable dielectric material, and/or combinations thereof. In some embodiments, ILD 109 may comprise a High Density Plasma (HDP) dielectric material (e.g., HDP oxide) and/or a High Aspect Ratio Process (HARP) dielectric material (e.g., HARP oxide). ILD 109 may also include one or more dielectric materials and/or one or more dielectric layers. One or more planarization processes may be used to planarize the top surface of ILD 109. In the gate replacement process, the ILD 109 may be planarized by a Chemical Mechanical Polishing (CMP) process until the top of the polysilicon gate is exposed. After replacing the polysilicon gate with a metal gate such as gate electrode 107, another CMP process may be performed to planarize the top surfaces of the gate electrode, spacers 110, and ILD 109. The CMP process includes a high selectivity to provide a substantially planar surface of the metal gate stack, spacers 110, and ILD 109. In some embodiments, the CMP process has low dishing and/or metal erosion effects.

Spacers 110 may be formed on opposing surfaces of ILD 109 and on a surface of substrate 101. The spacer 110 may include a plurality of sub-spacers and is not shown in fig. 1 for clarity. The spacers 110 may be formed using a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, any other suitable dielectric material, and/or combinations thereof. Spacers 110 may be formed by blanket depositing a dielectric material and anisotropically etching the dielectric material to form a remaining dielectric material on the sidewalls of ILD 109.

According to some embodiments, the high-k dielectric layer 102 may be formed on the top surface of the substrate 101 and on the sidewall surface of the spacer 110. The high-k dielectric layer 102 may comprise a dielectric material having a dielectric constant greater than about 3.9. In some embodiments, high-k dielectric layer 102 may comprise hafnium oxide. In some embodiments, the high-k dielectric layer 102 may be in crystalline form. The high-k dielectric layer 102 may be formed by chemical oxidation, thermal oxidation, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), any other suitable deposition method, and/or combinations thereof. In some embodiments, the high-k dielectric layer may be formed using an amorphous material.

The internal gate 103 may be a metal layer formed on the high-k dielectric layer 102. In some embodiments, the internal gate 103 may extend vertically (e.g., z-direction) and horizontally (e.g., x-direction). The internal gate 103 may be formed of tungsten, copper, titanium, silver, aluminum, titanium aluminide, titanium aluminum nitride, tantalum carbide, tantalum silicon nitride, manganese, cobalt, palladium, nickel, platinum, titanium nitride, tungsten nitride, tantalum nitride, any suitable conductive material, and/or combinations thereof. In some embodiments, the internal gate 103 may be formed of a metal alloy, such as a titanium-aluminum alloy, a rhenium-tantalum alloy, a rhenium-zirconium alloy, a platinum-titanium alloy, a cobalt-nickel alloy, a tungsten nitride alloy, a titanium nitride alloy, a molybdenum nitride alloy, a tantalum silicon nitride alloy, any suitable metal alloy, and/or combinations thereof.

Ferroelectric dielectric layer 105 may be a suitable crystalline material having ferroelectric properties. In some embodiments, ferroelectric dielectric layer 105 may be a high-k dielectric layer with a dielectric constant greater than 3.9. For example, ferroelectric dielectric layer 105 may comprise a high-k dielectric material, such as a hafnium-based oxide material. In some embodiments, the internal gate 103 may include hafnium oxide (HfO)₂). Other suitable crystalline ferroelectric dielectric materials may be used. Ferroelectric dielectric layer 105 may be formed by any suitable process, such as by ALD, CVD, metal organic CVD (mocvd), Physical Vapor Deposition (PVD), plasma enhanced CVD (pecvd), plasma enhanced ALD (peald), thermal oxidation, other suitable deposition techniques, and/or combinations thereof. In some embodiments, ferroelectric dielectric layer 105 can have a thickness between aboutTo aboutTo the thickness of (d) in between.

A gate electrode 107 is formed on the ferroelectric dielectric layer 105 to form a metal gate stack. In some embodiments, the gate electrode 107 may be referred to as a metal gate electrode. In some implementationsIn an example, a work function layer may be formed between the high-k dielectric layer 102 and the gate electrode 107. The gate electrode 107 may comprise any metallic material suitable for forming a metal gate or a portion of a metal gate. For example, the gate electrode 107 may include tungsten. In some embodiments, the gate electrode 107 may be formed using tungsten nitride (WN), TaN, ruthenium, silver, aluminum, any other suitable material, and/or combinations thereof. In some embodiments, the gate electrode 107 may be formed using a damascene process followed by a planarization process (e.g., a CMP process) to remove any excess material formed on the top surface of the ILD 109. In some embodiments, the gate electrode length L of the gate electrode 107_cCan be in the range of aboutTo aboutIn the meantime. For example, the gate electrode length L_cMay be aboutLength L_cAnd L_gMay be between about 0.4 and about 0.7.

Since portions of the inner gate 103 extend vertically (e.g., in the z-direction), they can cause parasitic capacitance that results in an undesirable gate leakage path through the spacer 110 and into the substrate 101. As shown in fig. 1, this vertically-configured gating of the internal gate 103 results in the creation of a gate leakage path (shown by arrow 120) between the gate electrode 107 and the substrate 101. The gate leakage path reduces device performance and can lead to device failure. In addition, the vertical configuration also reduces the significant horizontal contact area of the gate electrode 107, which is used for subsequent formation of contact structures, which in turn increases contact resistance.

Fig. 2 is a flow chart of a method 200 for forming a selectively deposited inner gate structure in a semiconductor device according to some embodiments of the present disclosure. It should be noted that the operations of method 200 may be performed in a different order and/or with variations, and that method 200 may include more operations and are not described for simplicity. Fig. 3A-3E are cross-sectional views of fabricating an exemplary semiconductor structure 300 incorporating a selectively deposited internal gate structure. The semiconductor structure 300 may include NCFET and/or FeFET devices. Fig. 3A-3E are provided as exemplary cross-sectional views to facilitate explanation of method 200. Semiconductor structure 300 may include substrate 301, S/D308, ILD 309, and spacer 310, substrate 301, S/D308, ILD 309, and spacer 310 being similar to substrate 101, S/D108, ILD 109, and spacer 110, respectively, as described above in fig. 1 and not described in detail herein for the sake of simplicity. In some embodiments, the substrate 301 may comprise a portion of a fin of a finFET device.

Although described herein with reference to a fabrication process for a planar device and/or finFET, the fabrication process may be applied to a variety of semiconductor structures, such as trenches or gaps, single fin finfets, and any other suitable semiconductor structure. The manufacturing processes provided herein are exemplary and alternative processes according to the present disclosure, not shown in these figures, may be performed.

At operation 202, a stack of layers is deposited in an opening of a semiconductor device, in accordance with some embodiments of the present disclosure. The openings may have a high aspect ratio (e.g., greater than 6). The openings may be gate trenches and other suitable high aspect ratio openings. In some embodiments, an opening may be formed between opposing sidewalls of the spacer and expose a top surface of the substrate. In some embodiments, the opening may expose a top surface of the fin formed as part of the substrate. In some embodiments, the stacked layers may include a first metal layer and a gate dielectric layer.

Referring to fig. 3A, high-k dielectric material 302 and first metal material 303 are deposited in gate trenches 360, the gate trenches 360 being formed between sidewalls of the spacers 310 and on the top surface 301A of the substrate 301. The high-k dielectric material 302 may be used as a gate dielectric and is formed of a dielectric material having a dielectric constant greater than about 3.9. For example, the high-k dielectric material 302 may be formed of a hafnium-based oxide material, such as hafnium oxide. In some embodiments, the high-k dielectric material 302 may be formed using an oxygen-deficient hafnium-based oxide. High-k dielectric material 302 may be used in combination with the aboveThe high-k dielectric layer 102 described in fig. 1 is formed of similar materials. In some embodiments, the high-k dielectric material 302 may have a dielectric constant of aboutTo aboutA thickness T in between. For example, depending on the device design, the thickness T may be aboutTo aboutBetween and aboutTo aboutOr any suitable thickness range. The first metallic material 303 may be formed using a suitable metallic material, which may be used as a seed layer for subsequent metal deposition. For example, the first metal material 303 may be formed using TiN having high conductivity. In some embodiments, the first metallic material 303 may be formed using silver, aluminum, gold, cobalt, tungsten, any suitable conductive material, and/or combinations thereof. In some embodiments, the first metallic material 303 may be formed using one of copper or a copper alloy including silver, chromium, nickel, tin, gold, and combinations thereof. In some embodiments, the thickness of the first metal material 303 may be aboutTo aboutIn the meantime. The lower thickness of the first metallic material 303 may reduce the etching time required to subsequently remove portions of the first metallic material 303. In some embodiments, the thickness of the first metal material 303The degree can be aboutTo aboutBetween and aboutTo aboutBetween and aboutTo aboutOr any other suitable range. The high-k dielectric material 302 and the first metallic material 303 may be deposited using a substantially conformal deposition method such as ALD. In some embodiments, the high-k dielectric material 302 and the first metal material 303 may be formed by any suitable process, such as CVD, MOCVD, PVD, PECVD, PEALD, thermal oxidation, any other suitable deposition technique, and/or combinations thereof.

In some embodiments, the high-k dielectric material 302 may be deposited using ALD or CVD at a temperature between about 150 ℃ to about 300 ℃. For example, the deposition temperature may be between about 150 ℃ to about 200 ℃, between about 200 ℃ to about 300 ℃, or any suitable temperature range. In some embodiments, the first metallic material 303 may be deposited at a different temperature than the high-k dielectric layer 302. For example, the deposition of the first metallic material may be an ALD or CVD process performed at a temperature between about 300 ℃ to about 600 ℃. For example, the deposition temperature may be between about 300 ℃ to about 400 ℃, between about 400 ℃ to about 500 ℃, between about 500 ℃ to about 600 ℃, or any suitable temperature range. In some embodiments, the deposition process may be performed in one or more suitable chambers of a semiconductor wafer processing cluster tool.

After depositing the high-k dielectric material 302 and the first metallic material 303, a barrier layer 380 may be deposited on the bottom of the trench 360. The barrier layer 380 serves to protect underlying layers, such as the high-k dielectric material 302 and the first metal material 303, during subsequent processing. In some embodiments, barrier layer 380 may be formed using a bottom anti-reflective coating (BARC) material. In some embodiments, barrier layer 380 may be formed using a blanket deposition of a barrier material followed by an etch back process (such as a recess process), wherein barrier layer 380 remains only at the bottom of trench 360.

Referring to fig. 2, in operation 204, portions of the first metal are removed to form a first metal layer, according to some embodiments of the present disclosure. Referring to fig. 3B, an etching process is performed on the semiconductor device 300 to etch back the first metal material 303. Portions of the first metallic material 303 exposed and not protected by the barrier layer 380 are removed by a suitable etching process. For example, a wet chemical etching process may be performed. The wet chemical process may be a timed process until the exposed portions of the first metallic material 303 are etched away. In some embodiments, as shown in fig. 3B, the wet chemical etching process may be continued with an over-etch that may remove additional portions of the first metallic material 303 formed between the barrier layer 380 and the high-k dielectric material 302. In some embodiments, wet chemical etching may use a solution containing an oxidizing agent (e.g., hydrogen peroxide). In some embodiments, the wet chemical etch may be performed at an elevated temperature to facilitate the chemical reaction. For example, the etching temperature may be between about 40 ℃ to about 150 ℃. In some embodiments, the etching temperature may be between about 40 ℃ to about 60 ℃. In this way, the remaining first metal material 303 may form a first metal layer 303 comprising horizontal portions 303A and vertical portions 303B. The horizontal portion 303A extends in the horizontal direction (e.g., x direction). The vertical portion 303B extends in a vertical direction (e.g., z direction). Due to the over-etching, the upper surface 303C of the vertical portion 303B may be lower than the top surface of the barrier layer 380 and may be a curved surface. In some embodiments, upper surface 303C may be substantially flush with the top surface of barrier layer 380. The barrier layer 380 is then removed using a suitable process, such as a wet chemical etch process having a high barrier material selectivity to the high-k dielectric material 302 and the underlying first metal layer 303.

Referring to fig. 2, at operation 206, a second metal layer 304 is selectively deposited on the first metal layer 303 using the first metal layer as a seed layer, such that the first and second metal layers form an internal gate 305, in accordance with some embodiments of the present disclosure. As shown in fig. 3C, second metal layer 304 may be deposited in trench 360 and on first metal layer 303 using a selective deposition process, according to some embodiments. For example, a selective tungsten chemical vapor deposition process may be performed to selectively deposit tungsten in the trenches 360. Specifically, using hydroxylamine sulfate and copper sulfate (CuSO) may be performed on the first metal layer 303 formed of aluminum₄) A combined cleaning process. The copper ions in the solution react with the aluminum surface and form a copper passivation layer that aids in tungsten nucleation during CVD tungsten deposition, wherein tungsten is formed on the exposed surface of first metal layer 303. Other suitable selective growth methods may also be used. For example, a self-assembled monolayer (SAM) deposition may be used in which the material forming second metal layer 304 is attracted to the surface of first metal layer 303. In some embodiments, second metal layer 304 gradually fills trench 360 as second metal layer 304 is deposited and accumulates on first metal layer 303. After the deposition process, a second metal layer 304 is also deposited on the high-k dielectric material 302 and in physical contact with the high-k dielectric material 302. In some embodiments, an electroplating or electroless plating process may be used to selectively deposit the second metal layer 304 in the trenches 360 and on the first metal layer 303.

Referring to fig. 2, at operation 208, portions of the gate dielectric layer are etched back, in accordance with some embodiments of the present disclosure. As shown in fig. 3D, the high-k dielectric material 302 is etched back to form a high-k dielectric layer 302 including horizontal portions 302A and vertical portions 302B. The horizontal portion 302A extends in a horizontal direction (e.g., x-direction) and is formed between the first metal layer 302 and the substrate 301. The vertical portion 302B extends in a vertical direction (e.g., z direction) and is formed between the spacer 310 and the internal gate 305. In some embodiments, vertical portion 302B is on the top surface of inner gate 305And (4) square extension. The etch back of the high-k dielectric material 302 forms an opening 380 between the opposing spacer 310 and the remaining high-k dielectric material 302. The etch-back process may be an anisotropic etch process 350, the anisotropic etch process 350 having a greater etch rate in the vertical direction than in the horizontal direction. In this way, high-k dielectric material 302 formed on the top surfaces of ILD 309 and spacer 310 is removed first, while high-k dielectric material 302 formed on the sidewalls of spacer 310 is gradually removed and its remaining portions form vertical portions 302B. As the etch-back process continues, the thickness of the vertical portion 302B remaining above the top surface 304A of the inner gate 305 continues to decrease. As shown in fig. 3D, the exposed surface of the vertical portion 302B extending above the top surface 304A of the second metal layer 304 may have a non-linear surface (e.g., a curved surface). For simplicity, thickness T_aIs the average thickness of the vertical portion 302B remaining above the top surface of the inner gate 305. Since the opening 380 is subsequently filled with the ferroelectric dielectric layer and the gate electrode, the etch-back process can be controlled so that the outline of the opening 380 obtains a shape that meets the design requirements of the ferroelectric dielectric layer and the gate electrode to be subsequently formed. For example, a lower average thickness T_aThis results in opening 380 having a greater width which may increase the width of a subsequently formed gate electrode. The lower average thickness T may be achieved by a longer etch time and/or a higher etch rate of the etch process 350_a. Further, the profile of vertical portion 302B remaining above top surface 304A may be adjusted by an etch-back process so that capacitance matching may be achieved between the high-k capacitor and a subsequently formed ferroelectric capacitor. In some embodiments, the average thickness T of the high-k dielectric material 302 ×_aThe ratio to the thickness T may be between about 5% to about 10%, between about 10% to about 20%, between about 20% to about 30%, between about 30% to about 40%, between about 40% to about 50%, between about 50% to about 60%, between about 60% to about 70%, between about 70% to about 80%, between about 80% to about 90%, between about 90% to about 99%, or any other suitable range. In some embodiments, the average thickness T of the high-k dielectric material 302 ×_aThe ratio to the thickness T may be about50％。

Referring to fig. 2, at operation 210, a ferroelectric layer and a gate electrode are deposited on an internal gate, according to some embodiments of the present disclosure. As shown in fig. 3E, ferroelectric dielectric layer 320 is disposed on internal gate 305 and between vertical portions 302B of high-k dielectric layer 302. In some embodiments, ferroelectric dielectric layer 320 is in physical contact with vertical portion 302B through nonlinear surface 302C. Gate electrode 340 is then deposited over ferroelectric dielectric layer 320. Specifically, gate electrode 340 is deposited in openings formed between opposing sidewall portions and horizontal portions of ferroelectric dielectric layer 320. In some embodiments, ferroelectric dielectric layer 320 may be formed using a layer that provides ferroelectric properties. For example, the ferroelectric dielectric layer 320 may be formed using crystalline hafnium oxide. In some embodiments, ferroelectric dielectric layer 320 may be deposited using a substantially conformal deposition process, such as an ALD or CVD process. In some embodiments, the composition and deposition method used to form ferroelectric dielectric layer 320 may be similar to the composition and deposition method of ferroelectric layer 105 described above as fig. 1.

Gate electrode 340 may include tungsten, WN, TaN, ruthenium, silver, aluminum, any other suitable material, and/or combinations thereof. A damascene process may be used followed by a planarization process to remove any excess material deposited to form gate electrode 340. One example of a planarization process is a CMP process. In some embodiments, the planarization process may also reduce the height of ILD 309 and spacers 310. The planarization process may continue until the top surfaces of ILD 309, spacer 310, ferroelectric dielectric layer 320, and gate electrode 340 are substantially horizontal (e.g., coplanar). In some embodiments, portions of the vertical portions 302B may also be exposed after the planarization process. In some embodiments, vertical portion 302B is covered by ferroelectric dielectric layer 320. After the planarization process, the gate stack formed may include high-k dielectric layer 302, internal gate 305, ferroelectric dielectric layer 320, and gate electrode 340.

The configuration of the semiconductor device 300 shown in fig. 3E may provide several benefits. For example, gate area modulation by etching back the high-k dielectric layer may provide reduced gate contact resistance, capacitance matching, uniform electric field, and the like. First, due to the high-k dielectricEtch back of layer and horizontal internal gate, gate electrode length L of gate electrode 340_fMay be greater than the gate electrode length L in fig. 1 described above_c. In some embodiments, the gate length L_fAnd gate length L_gMay be between about 0.4 and about 0.7. In some embodiments, the gate length L_gMay be between about 15nm and about 20 nm. For example, the gate length L_gAnd may be about 17 nm. Larger gate electrode length L_fProviding a larger surface area for subsequently formed gate contacts, which in turn reduces the gate contact resistance. Second, a ferroelectric capacitor C_FEAnd a high-k capacitor C_HKCan be matched by gate area modulation. As shown in FIG. 3E, gate electrode 340 and internal gate 305 may form ferroelectric capacitor C using ferroelectric dielectric layer 320 as the capacitor dielectric_FEAnd the substrate 301 and internal gate 305 may form a high-k capacitor C using the high-k gate dielectric 302 as a capacitor dielectric_HK. By adjusting the gate electrode length L_fThe ferroelectric capacitor C can be adjusted_FETo match the capacitance of the high-k capacitor C_HKThe capacitance of (c). In addition, the non-linear surface of the vertical portion 302B of the high-k dielectric layer and the resulting non-linear surface of the ferroelectric layer 320 thereon reduce sharp corners and provide a uniform electric field between the gate electrode 340 and the internal gate 305, which in turn improves device performance. Third, by employing horizontal internal gates 305 as shown in fig. 3E, parasitic capacitance and resulting gate leakage 120 as shown in fig. 1 can be avoided, which in turn improves device performance.

Various embodiments according to the present disclosure provide methods for forming selectively grown internal gates for transistor devices. In some embodiments, the transistor devices may be finFET, NCFET, nanosheet, nanowire, and other suitable devices. Selectively growing the internal gate may provide the following benefits: (i) reducing parasitic capacitance by incorporating horizontal internal gates, which in turn reduces gate leakage; (ii) performing gate area modulation by etching back and forth the high-k dielectric layer using the internal gate as an etch stop layer; (iii) device performance is improved by matching the capacitance of the ferroelectric capacitor and the high-k capacitor; (iv) by the gate area modulation, the electric field across the ferroelectric layer is uniform in the channel region of the transistor device.

In some embodiments, a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first spacer and the second spacer. The gate stack includes: a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

In some embodiments, a method for forming a semiconductor device includes: forming a first spacer and a second spacer; and depositing a gate dielectric layer between and on sidewalls of the first and second spacers. The method also includes forming an internal gate on the gate dielectric layer. The step of forming the internal gate includes: forming a first metal layer on the gate dielectric layer; and selectively depositing a second metal layer on the first metal layer using a selective Chemical Vapor Deposition (CVD) process. The method further includes depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer. The method further includes forming a gate electrode on the ferroelectric dielectric layer.

In some embodiments, a method for forming a semiconductor device includes forming a fin and forming a first spacer and a second spacer on the fin. The method also includes depositing a gate dielectric layer on the sidewalls of the fin and the first and second spacers, and forming an internal gate on the gate dielectric layer. Forming the internal gate includes depositing a first metal layer on the gate dielectric layer and forming a barrier layer on portions of the first metal layer. The method further comprises the following steps: removing the part of the first metal layer which is not covered by the barrier layer; removing the barrier layer; and selectively depositing a second metal layer on the first metal layer. The method further includes etching back the gate dielectric layer and depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer. The method further includes forming a gate electrode on the ferroelectric dielectric layer.

According to some embodiments, there is provided a semiconductor device including: a substrate; a first spacer and a second spacer on the substrate; and a gate stack between the first spacer and the second spacer, the gate stack comprising: a gate dielectric layer including a first portion on the substrate and a second portion on the first spacer and the second spacer; an internal gate on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

In the above semiconductor device, the semiconductor device includes a Negative Capacitance Field Effect Transistor (NCFET) device.

Among the above semiconductor devices, the semiconductor device includes a ferroelectric field effect transistor (FeFET) device.

In the above semiconductor device, further comprising a fin on the substrate, wherein the gate stack is on the fin.

In the above semiconductor device, the ferroelectric dielectric layer is located between the internal gate and the gate electrode.

In the above semiconductor device, the ferroelectric dielectric layer is located between the second portion of the gate dielectric layer and the gate electrode.

In the above semiconductor device, the ferroelectric dielectric layer is in physical contact with the second portion of the gate dielectric layer through the nonlinear surface.

In the above semiconductor device, the second portion of the gate dielectric layer has a nonlinear surface.

In the above semiconductor device, the internal gate includes a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer.

In the above semiconductor device, the first metal layer includes: a first portion on the first portion of the gate dielectric layer; and a second portion on the second portion of the gate dielectric layer.

According to some embodiments, there is provided a method of forming a semiconductor device, comprising: forming a first spacer and a second spacer; depositing a gate dielectric layer between and on sidewalls of the first and second spacers; forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes: forming a first metal layer on the gate dielectric layer; and selectively depositing a second metal layer on the first metal layer; depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer; and forming a gate electrode on the ferroelectric dielectric layer.

In the above method, etching back the gate dielectric layer includes performing an anisotropic dry etching process on the gate dielectric layer.

In the above method, forming the first metal layer includes: blanket depositing a first metal material on the gate dielectric layer; forming a barrier layer on portions of the first metallic material; removing the part of the first metal material which is not covered by the barrier layer; and removing the barrier layer.

In the above method, removing the portion of the first metallic material includes performing a wet chemical etching process on the portion of the first metallic material.

In the above method, selectively depositing the second metal layer comprises: a cleaning process is performed on the first metal layer, and a second metal layer is grown using the first metal layer as a seed layer.

According to some embodiments, there is provided a method of forming a semiconductor device, comprising: forming a fin; forming a first spacer and a second spacer on the fin; depositing a gate dielectric layer on the fins and on sidewalls of the first and second spacers; forming an internal gate on the gate dielectric layer, wherein forming the internal gate includes: depositing a first metal layer on the gate dielectric layer; forming a barrier layer on a portion of the first metal layer; removing the part of the first metal layer which is not covered by the barrier layer; removing the barrier layer; and selectively depositing a second metal layer on the first metal layer; etching back the grid dielectric layer; depositing a ferroelectric dielectric layer on the inner gate and the gate dielectric layer; and forming a gate electrode on the ferroelectric dielectric layer.

In the above method, depositing the ferroelectric dielectric layer comprises depositing the ferroelectric dielectric material directly on the gate dielectric layer.

In the above method, etching back the gate dielectric layer includes performing an anisotropic dry etching process on the gate dielectric layer.

In the above method, selectively depositing the second metal layer comprises: a cleaning process is performed on the first metal layer, and a second metal layer is grown using the first metal layer as a seed layer.

In the above method, selectively depositing the second metal layer includes depositing tungsten.

It is to be understood that the detailed description section, and not the abstract of the disclosure, is intended to be used to explain the present disclosure. The abstract section of the disclosure may set forth one or more, but not all exemplary embodiments, and, accordingly, is not intended to limit the disclosure.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.