阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 黄允泰 金完敦 金仅祐 于 2020-05-14 设计创作，主要内容包括：一种半导体器件包括：包括第一金属的下部接触图案；包括第二金属的上部接触图案,所述第一金属的第一电阻率大于所述第二金属的第二电阻率；以及位于所述下部接触图案与所述上部接触图案的下部之间的金属阻挡层,所述金属阻挡层包括第三金属,所述第三金属与所述第一金属和所述第二金属不同。所述上部接触图案的下部宽度可以小于所述下部接触图案的上部宽度。(A semiconductor device includes: a lower contact pattern including a first metal; an upper contact pattern comprising a second metal, a first resistivity of the first metal being greater than a second resistivity of the second metal; and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first metal and the second metal. A lower width of the upper contact pattern may be smaller than an upper width of the lower contact pattern.)

1. A semiconductor device, the semiconductor device comprising:

a lower contact pattern including a first metal;

an upper contact pattern comprising a second metal, a first resistivity of the first metal being greater than a second resistivity of the second metal; and

a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer comprising a third metal that is different from the first metal and the second metal,

wherein a lower width of the upper contact pattern is smaller than an upper width of the lower contact pattern.

2. The semiconductor device of claim 1, wherein a bottom surface of the upper contact pattern is located between a top and a bottom of the lower contact pattern.

3. The semiconductor device of claim 1, further comprising:

a lower metal barrier layer surrounding a bottom surface and sidewalls of the lower contact pattern.

4. The semiconductor device of claim 1, wherein the upper contact pattern is in an interlayer dielectric layer, and the second metal included in the upper contact pattern is in direct contact with the interlayer dielectric layer.

5. The semiconductor device of claim 1, further comprising:

a semiconductor layer;

an interlayer dielectric layer on the semiconductor layer; and

a conductive line on the interlayer dielectric layer,

wherein the lower contact pattern is in the semiconductor layer, and

wherein the upper contact pattern penetrates the interlayer dielectric layer and connects the conductive line to the lower contact pattern.

6. The semiconductor device of claim 1, wherein the first metal comprises one of cobalt, titanium, nickel, tungsten, molybdenum, and tantalum.

7. The semiconductor device of claim 1, wherein the second metal comprises one of rhenium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, and gold.

8. The semiconductor device of claim 1, wherein the third metal comprises one of tungsten, molybdenum, manganese, indium, aluminum, and nickel.

9. The semiconductor device of claim 1, wherein the first metal comprises cobalt and the third metal comprises ruthenium.

10. The semiconductor device of claim 1, further comprising:

a semiconductor substrate including an active pattern;

a gate structure crossing over the active pattern; and

a plurality of source/drain patterns in the active pattern on opposite sides of the gate structure,

wherein the lower contact pattern is coupled to a corresponding source/drain pattern of the plurality of source/drain patterns.

11. The semiconductor device of claim 10, wherein a top surface of the lower contact pattern is at the same level as a top surface of the source/drain pattern.

12. The semiconductor device of claim 10, further comprising:

a metal silicide layer between the corresponding source/drain pattern and the lower contact pattern.

13. A semiconductor device, the semiconductor device comprising:

a semiconductor substrate;

an interlayer dielectric layer on the semiconductor substrate;

an upper contact pattern penetrating the interlayer dielectric layer, the upper contact pattern including a first metal;

a lower contact pattern surrounding a lower portion of the upper contact pattern, the lower contact pattern including a second metal, the second metal being different from the first metal; and

a metal barrier layer between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer comprising a third metal different from the first metal and the second metal,

wherein the lower contact pattern has a first upper width and a first lower width smaller than the first upper width,

wherein the upper contact pattern has a second upper width and a second lower width, both of which are smaller than the first lower width, and

wherein a bottom surface of the upper contact pattern is located between a top and a bottom of the lower contact pattern.

14. The semiconductor device of claim 13, wherein the bottom surface of the upper contact pattern is lower than a bottom surface of the interlayer dielectric layer.

15. The semiconductor device of claim 13,

a first resistivity of the first metal is greater than a second resistivity of the second metal at the first lower width, and

at the second lower width, the first resistivity of the first metal is less than the second resistivity of the second metal.

16. The semiconductor device of claim 13, wherein the first metal comprises ruthenium and the second metal comprises cobalt.

17. A semiconductor device, the semiconductor device comprising:

a semiconductor substrate including an active pattern;

a gate structure crossing the active pattern and extending in a first direction;

a plurality of source/drain patterns on the active pattern, each of the plurality of source/drain patterns being on an opposite side of the gate structure; and

a contact structure coupled to a corresponding source/drain pattern of the plurality of source/drain patterns,

wherein the contact structure comprises:

a lower contact pattern in the corresponding source/drain pattern, the lower contact pattern including a first metal,

an upper contact pattern including a lower portion in a recess defined by a top surface of the lower contact pattern, the upper contact pattern including a second metal, an

A metal barrier layer between the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer comprising a third metal, wherein a bottom of the upper contact pattern is lower than a top of the lower contact pattern.

18. The semiconductor device of claim 17,

the first lower width of the lower contact pattern is greater than the second lower width of the upper contact pattern,

a first resistivity of the first metal is less than a second resistivity of the second metal at the first lower width, and

at the second lower width, a second resistivity of the second metal is less than a first resistivity of the first metal.

19. The semiconductor device of claim 17, wherein the first metal comprises cobalt and the second metal comprises ruthenium.

20. The semiconductor device of claim 17, wherein the third metal comprises tungsten or molybdenum.

Technical Field

The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a low-resistance contact structure.

Background

As semiconductor devices become highly integrated, the scaling down of elements (e.g., Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) included in the semiconductor devices is gradually accelerating. In this case, since the reduction of the Critical Dimension (CD) increases the resistance of the wiring and the capacitance between the wirings, it is difficult to achieve high-speed operation of the semiconductor device. Accordingly, various studies have been made to manufacture a semiconductor device having improved performance while overcoming limitations due to high integration of the semiconductor device.

Disclosure of Invention

Some example embodiments of the inventive concepts provide semiconductor devices including low-resistance contact structures.

Objects of the inventive concept are not limited to the above objects, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a lower contact pattern including a first metal; an upper contact pattern comprising a second metal, a first resistivity of the first metal being greater than a second resistivity of the second metal; and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first metal and the second metal. A lower width of the upper contact pattern may be smaller than an upper width of the lower contact pattern.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a semiconductor substrate; an interlayer dielectric layer on the semiconductor substrate; an upper contact pattern penetrating the interlayer dielectric layer, the upper contact pattern including a first metal; a lower contact pattern surrounding a lower portion of the upper contact pattern, the lower contact pattern including a second metal, the second metal being different from the first metal; and a metal barrier layer between the lower portion of the lower contact pattern and the lower portion of the upper contact pattern, the metal barrier layer including a third metal different from the first metal and the second metal. The lower contact pattern may have a first upper width and a first lower width smaller than the first upper width. The upper contact pattern may have a second upper width and a second lower width, both of which are smaller than the first lower width. The bottom surface of the upper contact pattern may be located between the top and the bottom of the lower contact pattern.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a semiconductor substrate including an active pattern; a gate structure crossing the active pattern and extending in a first direction; a plurality of source/drain patterns on the active pattern, each of the plurality of source/drain patterns being on an opposite side of the gate structure; and a contact structure coupled to a corresponding source/drain pattern of the plurality of source/drain patterns.

The contact structure may include: a lower contact pattern in the corresponding source/drain pattern, the lower contact pattern including a first metal; an upper contact pattern including a lower portion located in a recess defined by a top surface of the lower contact pattern, the upper contact pattern including a second metal; and a metal barrier layer between the lower portion of the upper contact pattern and the lower portion of the lower contact pattern, the metal barrier layer including a third metal. The bottom of the upper contact pattern may be lower than the top of the lower contact pattern.

Details of some example embodiments are included in the description and the drawings.

Drawings

Fig. 1 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 2 illustrates a cross-sectional view taken along lines I-I 'and II-II' in fig. 1, showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 3A and 3B show enlarged views showing a section a in fig. 2.

Fig. 4 illustrates a graph showing a relationship between resistivity and a width or size of a metal included in a contact structure according to some example embodiments of the inventive concepts.

Fig. 5A to 5D illustrate cross-sectional views taken along line I-I' of fig. 1, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 6A to 6C illustrate cross-sectional views taken along line I-I' of fig. 1, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 7 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 8A illustrates a cross-sectional view taken along line III-III' in fig. 7, showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 8B and 8C illustrate cross-sectional views taken along line IV-IV' of fig. 7, showing semiconductor devices according to some example embodiments of the inventive concepts.

Fig. 9 shows an enlarged view showing a section B in fig. 8A.

Fig. 10A to 10D illustrate cross-sectional views taken along line III-III' in fig. 7, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 11A and 11B illustrate cross-sectional views taken along lines III-III 'and IV-IV' in fig. 7, respectively, showing semiconductor devices according to some example embodiments of the inventive concepts.

Fig. 12 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 13A and 13B illustrate cross-sectional views taken along lines V-V and VI-VI' in fig. 12, respectively, showing semiconductor devices according to some example embodiments of the inventive concepts.

Fig. 14 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the inventive concepts.

Detailed Description

A semiconductor device and a method of manufacturing the same according to some example embodiments of the inventive concepts will now be described below with reference to the accompanying drawings.

Although the terms "same" or "same" are used in the description of example embodiments, it should be understood that some imprecision may exist. Thus, when an element is referred to as being the same as another element, it is understood that one element or value is the same as another element or value within the desired manufacturing or operating tolerance range (e.g., ± 10%).

When the term "about" or "substantially" is used in this specification in connection with a numerical value, the relevant numerical value is intended to include manufacturing or operating tolerances (e.g., ± 10%) around the numerical value recited. Further, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the precision of the geometric shape is not required, but that the range of variation of the shape is within the scope of the present disclosure.

As used herein, expressions such as "at least one of" modify an entire list of elements as opposed to modifying individual elements in the list when preceding the list of elements. Thus, "at least one (kind) of A, B or C" and "A, B and C" modify the entire list of elements without modifying individual elements in the list, and thus refer to A, B, C or any combination thereof.

Fig. 1 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 2 illustrates a cross-sectional view taken along lines I-I 'and II-II' in fig. 1, showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 3A and 3B show enlarged views showing a section a in fig. 2. Fig. 4 illustrates a graph showing a relationship between resistivity and a width or size of a metal included in a contact structure according to some example embodiments of the inventive concepts.

Referring to fig. 1 and 2, the semiconductor substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, silicon germanium, or the like. For example, the semiconductor substrate 100 may be a silicon substrate.

The semiconductor substrate 100 may include an active pattern 101. The active pattern 101 may be a portion of the semiconductor substrate 100, and may be defined by a trench (e.g., a device isolation layer 102) formed on the semiconductor substrate 100. The active pattern 101 may extend in the first direction D1.

The active pattern 101 may be disposed between the device isolation layers 102. The top surface of the device isolation layer 102 may be lower than the top surface of the active pattern 101. In other words, the active pattern 101 may protrude upward with respect to the top surface of the device isolation layer 102. An upper portion of the active pattern 101 may be exposed by the device isolation layer 102. The device isolation layers 102 may extend in the first direction D1, and may be spaced apart from each other in a second direction D2 intersecting the first direction D1.

A gate structure GS may be disposed on the semiconductor substrate 100 across the active pattern 101. The gate structures GS may extend across the active pattern 101 in the second direction D2 and may be spaced apart from each other in the first direction D. The gate structures GS may have the same or substantially similar width and may be spaced apart from each other at regular intervals.

Each gate structure GS may include a gate dielectric layer 111, a gate conductive pattern 113, and a capping dielectric pattern 115. Gate spacers 121 may be disposed on opposing sidewalls of each gate structure GS.

The gate dielectric layer 111 may extend along the second direction D2, and may conformally cover the upper portion of the active pattern 101. The gate dielectric layer 111 may extend from between the gate conductive pattern 113 and the active pattern 101 to between the gate conductive pattern 113 and the gate spacer 121. For example, the gate dielectric layer 111 may extend from the bottom surface of the gate conductive pattern 113 toward opposite sidewalls of the gate conductive pattern 113. In other words, the gate dielectric layer 111 may extend upward from the bottom surface of the gate conductive pattern 113 along the sidewalls of the gate conductive pattern 113. The gate dielectric layer 111 may comprise a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The gate dielectric layer 111 may comprise, for example, a metal oxide, a metal silicate, or a metal silicate nitride.

The gate conductive pattern 113 may include a barrier metal pattern (not specifically shown) and a metal pattern (not specifically shown). The barrier metal pattern may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). The metal pattern may include a metal material (e.g., tungsten, aluminum, titanium, and/or tantalum).

The capping dielectric pattern 115 may cover a top surface of the gate conductive pattern 113. The top surface of the capping dielectric pattern 115 may be coplanar or substantially coplanar with the top surface of the gap-fill dielectric layer 161. The capping dielectric pattern 115 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), or silicon oxycarbonitride (SiCON). The gate spacers 121 may comprise a dielectric material, such as silicon oxide or silicon nitride.

The source/drain regions 130 may be disposed on upper portions of the active patterns 101 at opposite sides of each gate structure GS. Each source/drain region 130 may include n-type or p-type impurities. The active pattern 101 may have portions (e.g., channel regions) located between the source/drain regions 130 spaced apart from each other in a horizontal direction.

The gap-fill dielectric layer 161 may fill the space between the gate structures GS and may cover the source/drain regions 130. For example, the top surface of the gap-fill dielectric layer 161 may be coplanar or substantially coplanar with the top surface of the gate structure GS.

The gap-fill dielectric layer 161 may be provided thereon with a first interlayer dielectric layer 163 covering the top surface of the gate structure GS. The gap-fill dielectric layer 161 and the first interlayer dielectric layer 163 may be formed of a dielectric material having an etch selectivity with respect to the gate spacer 121, and may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

The contact structure CP may penetrate the first interlayer dielectric layer 163 and the gap-fill dielectric layer 161, and may be coupled to the source/drain region 130. According to some example embodiments, each contact structure CP may include a lower contact pattern 140, an upper contact pattern 150, and a metal barrier layer between the lower contact pattern 140 and the upper contact pattern 150.

For example, the lower contact pattern 140 may be disposed in the source/drain region 130. In this case, the lower contact pattern 140 may be disposed in a recess of the source/drain region 130. The bottom surface of the lower contact pattern 140 may be at a lower level than the top of the source/drain region 130. The level of the top of the lower contact pattern 140 may be the same as or substantially similar to the level of the top of the source/drain region 130.

The lower contact pattern 140 may have a first upper width a1 at the top thereof and a first lower width a2 at the bottom thereof that is less than the first upper width a 1. The top of the lower contact pattern 140 may be partially removed to form a recess. The width of the recess may be less than the first upper width a 1. For example, the lower contact pattern 140 may have a width of about 5nm to about 30 nm.

Referring to fig. 3A, the lower contact pattern 140 may include a first barrier metal pattern 141 and a first metal pattern 143. The first metal pattern 143 may include a first metal. The first metal may include, for example, one selected from cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), and tantalum (Ta). The first barrier metal pattern 141 may conformally cover the bottom surface and sidewalls of the first metal pattern 143. The first barrier metal pattern 141 may be formed of, for example, one or more of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, and WN.

The second metal barrier layer 145 may be partially disposed in the recess defined by the lower contact pattern 140. The second metal barrier layer 145 may substantially conformally cover the recess of the lower contact pattern 140. The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140. The second metal may include, for example, one selected from tungsten (W), molybdenum (Mo), manganese (Mn), indium (In), aluminum (Al), and nickel (Ni). The second metal barrier layer 145 may reduce or prevent diffusion and/or intermixing between the first metal included in the lower contact pattern 140 and the third metal included in the upper contact pattern 150.

The upper contact pattern 150 may penetrate the first interlayer dielectric layer 163 and the gap filling dielectric layer 161, and may be disposed on the lower contact pattern 140. The lower portion of the upper contact pattern 150 may be located in the recess of the lower contact pattern 140.

The upper contact pattern 150 may have a second upper width B1 at the top thereof and a second lower width B2 at the bottom thereof, the second lower width B2 being less than the second upper width B1. The second lower width B2 of the upper contact pattern 150 may be less than the first upper width a1 and the first lower width a2 of the lower contact pattern 140. For example, the upper contact pattern 150 may have a width of about 3nm to about 15 nm.

The third metal of the upper contact pattern 150 may be a noble metal material. The upper contact pattern 150 may include, for example, one or more of rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

The third metal of the upper contact pattern 150 may be in direct contact with the gap-fill dielectric layer 161, as shown in fig. 3A. For another example, referring to fig. 3B, the upper contact pattern 150 may include an upper barrier metal pattern 151 conformally covering a bottom surface and sidewalls of the upper metal pattern 153, similar to the lower contact pattern 140.

A metal silicide layer 135 may be disposed between each contact structure CP and each source/drain region 130. The metal silicide layer 135 may contact the bottom surface and the sidewall of the lower contact pattern 140. The metal silicide layer 135 may include, for example, one or more of titanium, nickel, cobalt, tungsten, tantalum, platinum, palladium, and erbium.

Referring to fig. 4, the first metal M1 of the lower contact pattern 140 may have a resistivity that rapidly increases below a certain width W. At the second lower width B2, the resistivity of the third metal M3 of the upper contact pattern 150 may be lower than the resistivity of the first metal M1 below the specific width W.

According to some example embodiments, since a portion of the lower contact pattern 140 is filled with a third metal having a resistivity lower than that of the first metal below the certain width W, the resistivity of the contact structure CP may be reduced. Accordingly, a signal delay through the contact structure CP may be reduced, thereby improving an operation speed of the semiconductor device.

Fig. 5A to 5D illustrate cross-sectional views taken along line I-I' of fig. 1, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Referring to fig. 5A, the semiconductor substrate 100 may be patterned to form an active pattern 101 vertically protruding from the semiconductor substrate 100. A device isolation layer (see 102 of fig. 2) may be formed at opposite sides of the active pattern 101. The device isolation layer 102 may have a top surface recessed from a top surface of the active pattern 101.

The gate structure GS may be formed to cross the active pattern 101. The forming of the gate structure GS may include: forming a sacrificial gate pattern (not shown); forming gate spacers 121 on opposite sidewalls of the sacrificial gate pattern; after removing the sacrificial gate pattern, sequentially forming a gate dielectric layer 111 and a gate conductive pattern 113 in the gate region between the pair of gate spacers 121; and a capping dielectric pattern 115 is formed on the gate dielectric layer 111 and the gate conductive pattern 113.

Source/drain regions 130 may be formed on opposite sides of each gate structure GS. As described above, the source/drain regions 130 may be in-situ doped with dopants having conductivity types opposite to those of corresponding portions of the semiconductor substrate 100, respectively.

The gate spacers 121 may be used as an etch mask to etch a portion of the source/drain regions 130 to form a first recess RS1 on each source/drain region 130. The depth of the first recess RS1 may be determined based on the electrical characteristics of the semiconductor device.

Referring to fig. 5B, a metal silicide layer 135 and a lower contact pattern 140 may be formed in the first recess RS1 of the source/drain region 130.

The lower contact pattern 140 may be formed by: sequentially depositing a first metal barrier layer and a first metal layer in the first recesses RSl of the source/drain regions 130; the first metal barrier layer and the first metal layer located on the top surface of the active pattern 101 are then partially etched. The first metallic barrier layer may conformally cover the surface of the first recess RS 1. While depositing and annealing the first metal barrier layer and the first metal layer, the first metal barrier layer and the source/drain region 130 may react with each other to form the silicide layer 135 on the surface of the first recess RS1 of the source/drain region 130.

Referring to fig. 5C, after the lower contact pattern 140 is formed, a gap filling dielectric layer 161 filling the space between the gate structures GS may be formed, and then a first interlayer dielectric layer 163 covering the gate structures GS may be formed. The contact hole CH may be formed to penetrate the first interlayer dielectric layer 163 and the gap filling dielectric layer 161, thereby exposing a portion of the lower contact pattern 140. The forming of the contact hole CH may include: an etch mask is formed on the first interlayer dielectric layer 163, and a portion of the first interlayer dielectric layer 163, a portion of the gap-filling dielectric layer 161, and a portion of the lower contact pattern 140 are sequentially etched using the etch mask. Accordingly, a portion of the top surface of the lower contact pattern 140 may be partially recessed to form the second recess RS 2.

Referring to fig. 5D, a second metal blocking layer 145 may be formed on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal barrier layer 145 may be formed by performing a selective deposition process. The selective deposition process may use different deposition rates depending on the underlying film quality. The selective deposition process may deposit the second metal barrier layer 145 only on the surface of the lower contact pattern 140 exposed to the contact hole CH.

The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140. The second metal barrier layer 145 may be formed of a metal layer or a metal nitride layer including, for example, one or more of tantalum (Ta), titanium (Ti), tungsten (W), cobalt (Co), molybdenum (Mo), manganese (Mn), nickel (Ni), and aluminum (Al). In example embodiments, the second metal barrier 145 may include tungsten (W) or molybdenum (Mo).

An upper contact pattern (see 150 of fig. 2) may be formed in the contact hole CH in which the second metal blocking layer 145 is formed. The upper contact pattern 150 may be formed by: depositing a metal layer comprising a third metal different from the second metal; and etching the metal layer to expose a top surface of the first interlayer dielectric layer 163. The upper contact pattern 150 may include a noble metal material. The upper contact pattern 150 may include, for example, one or more of rhenium (Re), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au).

Fig. 6A to 6C illustrate cross-sectional views taken along line I-I' of fig. 1, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

For the sake of brevity of description, the same technical features as those of the example embodiment discussed above with reference to fig. 5A to 5D may be omitted.

Referring to fig. 6A, after the step discussed in fig. 5B above, the lower contact pattern 140 may be formed in the source/drain region 130, and then a portion of the lower contact pattern 140 may be etched to form the second recess RS 2.

Referring to fig. 6B, a second metal barrier layer 145 may be formed on the second recess RS2 of the lower contact pattern 140. The second metal barrier layer 145 may be selectively deposited on the surface of the lower contact pattern 140 having the second recess RS2 using a selective deposition process.

The first upper contact pattern 150a may be formed to fill the second recess RS2 in which the second metal barrier layer 145 is formed. The first upper contact pattern 150a may include a third metal having a lower resistivity than that of the lower contact pattern 140.

Referring to fig. 6C, a first interlayer dielectric layer 163 may be formed to cover the gate structure GS. The contact hole CH may be formed to penetrate the first interlayer dielectric layer 163 and expose a portion of the first upper contact pattern 150 a. The forming of the contact hole CH may include: forming an etch mask on the first interlayer dielectric layer 163; and etching a portion of the first interlayer dielectric layer 163 using the etch mask until the first upper contact pattern 150a is exposed.

A second upper contact pattern 150b may be formed in the contact hole CH, the second upper contact pattern 150b including a third metal identical to that in the first upper contact pattern 150 a.

Fig. 7 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 8A illustrates a cross-sectional view taken along line III-III' in fig. 7, showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 8B and 8C illustrate cross-sectional views taken along line IV-IV' of fig. 7, showing semiconductor devices according to some example embodiments of the inventive concepts.

For the sake of brevity of description, the same technical features as those of the embodiment discussed with reference to fig. 1 and 2 may be omitted.

The semiconductor substrate 100 may include a first active region Rl and a second active region R2. The first and second active regions R1 and R2 may be included in a logic cell region in which logic transistors constituting a logic circuit of the semiconductor device are disposed. For example, a PMOS field effect transistor may be provided on the first active region R1, and an NMOS field effect transistor may be provided on the second active region R2. The semiconductor substrate 100 may include a dopant having a conductivity type different from that in the second active region R2 in the first active region R1.

On the first active region Rl, the plurality of first active patterns 101a may extend along the first direction Dl and may be spaced apart from each other in a second direction D2 intersecting the first direction Dl. On the second active region R2, the plurality of second active patterns 101b may extend in the first direction D1 and may be spaced apart from each other in a second direction D2 intersecting the first direction D1. The first and second active patterns 101a and 101b may be a portion of the semiconductor substrate 100, and may be defined by a first trench formed on the semiconductor substrate 100. In example embodiments, three first active patterns 101a are shown, but the number of the first active patterns 101a may be variously changed. This may also be the case for the second active pattern 101 b.

The first device isolation layer 102 may be disposed between the first active patterns 101a and between the second active patterns 101 b. The first device isolation layer 102 may separate the first and second active patterns 101a and 101b from each other in the second direction D2. The first device isolation layer 102 may expose upper portions of the first active patterns 101a and upper portions of the second active patterns 101 b. For example, the top surface of the first device isolation layer 102 may be lower than the top surfaces of the first and second active patterns 101a and 101b, and the upper portions of the first and second active patterns 101a and 101b may protrude upward from the top surface of the first device isolation layer 102.

The second device isolation layer 105 may extend in the first direction D1, and may define a first active region R1 and a second active region R2. The second device isolation layer 105 may be disposed between the outermost first active patterns 101a among the first active patterns 101a of the first active region R1 and the adjacent outermost second active patterns 101b among the second active patterns 101b of the second active region R2. The width of the second device isolation layer 105 in the second direction D2 may be greater than the width of the first device isolation layer 102 in the second direction D2. The bottom surface of second device isolation layer 105 may be at a level lower than, equal to, or substantially similar to the level at which the bottom surface of first device isolation layer 102 is located. The second device isolation layer 105 may separate the first and second active regions R1 and R2 from each other in the second direction D2.

The gate structure GS may extend in the second direction D2 while crossing the first active pattern 101a of the first active region R1 and the second active pattern 101b of the second active region R2. The gate structures GS may be arranged at a regular pitch. For example, the gate structures GS may have the same or substantially similar width and may be spaced apart from each other at a regular interval.

Each gate structure GS may include a gate dielectric layer 111, a gate conductive pattern 113, and a capping dielectric pattern 115. Gate spacers 121 may be disposed on opposing sidewalls of each gate structure GS.

The source/drain patterns 130a may be disposed at opposite sides of each gate structure GS. The source/drain pattern 130a may include a first source/drain pattern on an upper portion of the first active pattern 101a and a second source/drain pattern on an upper portion of the second active pattern 101 b. The first active pattern 101a or the second active pattern 101b may have portions (e.g., channel regions) located between the source/drain patterns 130a spaced apart from each other in the horizontal direction.

When the first active region R1 is provided with an NMOS Field Effect Transistor (FET), the first source/drain pattern may be configured to provide tensile strain to a channel region of the NMOSFET (e.g., to an upper portion of the active pattern 101). For example, the first source/drain pattern may be an epitaxial layer of silicon carbide (SiC). When the second active region R2 is provided with a PMOSFET, the second source/drain pattern may be configured to provide compressive strain to a channel region of the PMOSFET. For example, the second source/drain pattern may be an epitaxial layer of silicon germanium (SiGe).

The first source/drain pattern on the first active region Rl may include p-type impurities, and the second source/drain pattern on the second active region R2 may include n-type impurities. For example, the source/drain patterns 130a may be epitaxial layers grown from the first and second active patterns 101a and 101 b. The first source/drain pattern on the first active region R1 may be an epitaxial layer of silicon germanium (SiGe), and the second source/drain pattern on the second active region R2 may be an epitaxial layer of silicon carbide (SiC). For example, the volume of the first source/drain pattern may be greater than the volume of the second source/drain pattern. The bottom end of the first source/drain pattern may be lower than the bottom end of the second source/drain pattern.

The gap-fill dielectric layer 161 may fill the space between the gate structures GS and may cover the first and second source/drain patterns. For example, the top surface of the gap-fill dielectric layer 161 may be coplanar or substantially coplanar with the top surface of the gate structure GS.

The gap-fill dielectric layer 161 may be provided thereon with a first interlayer dielectric layer 163 covering the top surface of the gate structure GS. The gap-fill dielectric layer 161 and the first interlayer dielectric layer 163 may be formed of a dielectric material having an etch selectivity with respect to the gate spacer 121, and may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer.

On the first and second active regions R1 and R2, the active contact structure ACP may penetrate the first interlayer dielectric layer 163 and the gap filling dielectric layer 161, and may be coupled to the source/drain pattern 130 a.

Similar to the contact structure CP discussed above with reference to fig. 2, each active contact structure ACP may include a lower contact pattern 140, an upper contact pattern 150, and a metal barrier 145 between the lower contact pattern 140 and the upper contact pattern 150.

For example, referring to fig. 9, the bottom of the lower contact pattern 140 may be at a lower level than the top of the source/drain pattern 130 a. The top of the lower contact pattern 140 may be located at substantially the same level as the level of the top of the source/drain pattern 130 a.

Referring to fig. 7, 8A and 8B, the gate contact structures GCP may be respectively coupled to the corresponding gate conductive patterns 113 of the gate structures GS. The gate contact structure GCP may penetrate the first interlayer dielectric layer 163 and the capping dielectric pattern 115 of the gate structure GS. Although not specifically shown, the gate contact structure GCP may also penetrate the gap filling dielectric layer 161. The gate contact structure GCP may be formed simultaneously with the active contact structure ACP, and may include the same metal material as that of the active contact structure ACP. The top surface of the gate contact structure GCP may be coplanar or substantially coplanar with the top surface of the active contact structure ACP.

For example, referring to fig. 8B, the gate contact structure GCP may include a lower contact pattern 140, a metal barrier layer 145, and an upper contact pattern 150, similar to the active contact structure ACP, and a lower portion of the upper contact pattern 150 may be disposed in a recess defined by a top surface of the lower contact pattern 140.

For another example, referring to fig. 8C, the gate contact structure GCP may include a metal barrier layer and an upper contact pattern, but not include a lower contact pattern. In this case, the metal blocking layer may be in direct contact with the gate conductive pattern 113 of the gate structure GS.

Referring to fig. 7, 8A, and 8B, the via pattern VP may be disposed in the second interlayer dielectric layer 165 and may be coupled to the active contact structure ACP. The via pattern VP may include a metal (e.g., one or more of tungsten, titanium, tantalum, cobalt, and copper) and a conductive metal nitride (e.g., one of titanium nitride, tantalum nitride, and tungsten nitride).

The interconnect pattern ICP may be disposed in the third interlayer dielectric layer 167, and may be coupled to the via pattern VP. On each of the first and second active regions R1 and R2, the interconnection pattern ICP may cross one gate structure GS. For example, the interconnect pattern ICP may have a stripe or line shape extending in the first direction D1 on the second device isolation layer 105.

Fig. 10A to 10D illustrate cross-sectional views taken along line III-III' in fig. 7, showing methods of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Referring to fig. 10A, the semiconductor substrate 100 may be patterned to form an active pattern 101a vertically protruding from the semiconductor substrate 100. A device isolation layer (see 102 of fig. 8B) may be formed at the opposite side of the active pattern 101 a. The device isolation layer 102 may have a top surface recessed from the top surface of the active pattern 101 a.

The gate structure GS may be formed to cross the active pattern 101 a. The forming of the gate structure GS may include: forming a sacrificial gate pattern (not shown); forming gate spacers 121 on opposite sidewalls of the sacrificial gate pattern; after removing the sacrificial gate pattern, sequentially forming a gate dielectric layer 111 and a gate conductive pattern 113 in the gate region between the pair of gate spacers 121; and a capping dielectric pattern 115 is formed on the gate dielectric layer 111 and the gate conductive pattern 113.

The source/drain patterns 130a may be formed at opposite sides of each gate structure GS. The source/drain pattern 130a may be formed by epitaxial growth from the active pattern 101 a. The source/drain pattern 130a may include an epitaxial layer of silicon germanium (SiGe) or silicon carbide (SiC).

According to some example embodiments, after the source/drain pattern 130a is formed, a gate structure GS including a metal material may be formed. The gap-fill dielectric layer 161 may fill the space between the gate structures GS.

Referring to fig. 10B, the lower contact pattern 140 may be formed to penetrate the gap-fill dielectric layer 161 so as to be coupled to the corresponding source/drain pattern 130 a.

As discussed above with reference to fig. 5B, the formation of the lower contact pattern 140 may include depositing a first metal barrier layer and a first metal layer.

At the same time of forming the lower contact pattern 140, a silicide layer 135 may be formed between the source/drain pattern 130a and the lower contact pattern 140.

Referring to fig. 10C, an interlayer dielectric layer 163 may be deposited on the lower contact pattern 140. The interlayer dielectric layer 163 may cover the top surface of the lower contact pattern 140 and the top surface of the gate structure GS.

The contact hole CH may be formed to penetrate the interlayer dielectric layer 163 and expose a portion of the lower contact pattern 140. The forming of the contact hole CH may include: forming an etch mask on the interlayer dielectric layer 163; and sequentially etching the interlayer dielectric layer 163 and a portion of the lower contact pattern 140 using the etch mask. Accordingly, the top of the lower contact pattern 140 may be partially removed or partially recessed to form a recess. The bottom surface of the recess may be at a level lower than the level of the top surface of the gate structure GS.

Referring to fig. 10D, as discussed above with reference to fig. 5D, a second metal blocking layer 145 may be formed on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal blocking layer 145 may be deposited only on the surface of the lower contact pattern 140 exposed to the contact hole CH. The second metal barrier layer 145 may include a second metal different from the first metal of the lower contact pattern 140.

An upper contact pattern may be formed in the contact holes CH in which the second metal blocking layer 145 is formed (see 150 of fig. 8A). As described above, the upper contact pattern 150 may include a third metal different from the first metal of the lower contact pattern 140. The third metal may have a lower resistivity than the first metal, and the third metal may include a noble metal material.

Fig. 11A and 11B illustrate cross-sectional views taken along lines III-III 'and IV-IV' in fig. 7, respectively, showing semiconductor devices according to some example embodiments of the inventive concepts.

For the sake of brevity of description, the same technical features as those of the embodiment discussed with reference to fig. 7, 8A and 8C may be omitted.

The semiconductor device shown in fig. 11A and 11B may be a multi-bridge channel field effect transistor (MBCFET). The MBCFET may include a plurality of thin rectangular nanosheet channels and gate electrodes surrounding the channels, both above and below and to the left and right. A plurality of thin nanosheets may be stacked in a vertical direction.

For example, referring to fig. 11A and 11B, first channel patterns CH1 vertically stacked and spaced apart from each other may be disposed on each of the first active patterns 101A. The first channel patterns CH1 stacked on the first active patterns 101a may vertically overlap each other.

Each of the second active patterns 101b may be provided thereon with second channel patterns CH2 vertically stacked and spaced apart from each other. The second channel patterns CH2 stacked on the second active patterns 101b may vertically overlap each other. The first and second channel patterns CH1 and CH2 may include one or more of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

The first source/drain patterns 130a may be disposed on each of the first active patterns 101 a. The stacked first channel pattern CH1 may be disposed between a pair of adjacent first source/drain patterns 130 a. The stacked first channel patterns CH1 may connect pairs of adjacent first source/drain patterns 130 a.

A second source/drain pattern may be disposed on each of the second active patterns 101 b. The stacked second channel pattern CH2 may be disposed between a pair of adjacent second source/drain patterns. The stacked second channel patterns CH2 may connect pairs of adjacent second source/drain patterns.

As described above, each gate structure GS may include the gate dielectric layer 111, the gate conductive pattern 113, and the capping dielectric pattern 115, and the gate spacers 121 may be disposed on opposite sidewalls of each gate structure GS. In some example embodiments, the capping dielectric pattern 115 may have a circular bottom surface, and the circular bottom surface may be in contact with the top surface of the gate conductive pattern 113. The rounded surface of the capping dielectric pattern 115 may contact the sidewalls of the gate spacers 121.

On each gate structure GS, the gate conductive pattern 113 may surround the first channel pattern CH1 and the second channel pattern CH 2. For example, the gate conductive pattern 113 may surround the top and bottom surfaces and the opposite sidewalls of each of the first and second channel patterns CH1 and CH 2. In this sense, the transistors disposed on the first and second active regions R1 and R2 may be gate-all-around type field effect transistors.

The gate dielectric layer 111 may be disposed between the gate conductive pattern 113 and each of the first and second channel patterns CH1 and CH 2. The gate dielectric layer 111 may surround respective ones of the first and second channel patterns CH1 and CH 2.

The inner spacers 112 may be disposed under the gate spacers 121 and on sidewalls of the gate structure GS. When viewed in a cross-sectional view, the inner spacer 112 may be partially disposed between the adjacent first channel patterns CH1 and between the first active pattern 101a and the lowermost first channel pattern CH 1. When viewed in a top view, the one or more inner spacers 112 may be locally disposed between the first source/drain pattern 130a and opposite sidewalls of the gate structure GS. The inner spacer 112 may be in contact with the gate dielectric layer 111 and may be formed of a dielectric material.

According to some embodiments, the active contact structure ACP may penetrate the first interlayer dielectric layer 163 and may be coupled to the first source/drain pattern 130a, as described above. Although not specifically shown, the active contact structure ACP may also penetrate the gap fill dielectric layer 161. The active contact structure ACP may be disposed in a portion of the first source/drain pattern 130 a. A metal silicide layer 135 may be formed between the active contact structure ACP and the first source/drain pattern 130 a.

The gate contact structure GCP may be coupled to the gate conductive pattern 113 of the gate structure GS. As described above, the gate contact structure GCP may include the same metal material as that of the active contact structure ACP.

Fig. 12 illustrates a top view showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 13A and 13B illustrate cross-sectional views taken along lines V-V and VI-VI' in fig. 12, respectively, showing semiconductor devices according to some example embodiments of the inventive concepts. For the sake of brevity of description, the same technical features as those of the embodiment discussed with reference to fig. 1 and 2 may be omitted.

Referring to fig. 12, 13A, and 13B, a selection transistor as a selection element of a memory cell may be provided on a semiconductor substrate 100. The selection transistor may include cell active patterns CA, gate structures GS crossing the cell active patterns CA, and first and second impurity regions formed in the cell active patterns CA at opposite sides of each of the gate structures GS.

For example, the device isolation pattern 102 defining the cell active pattern CA may be disposed on the first region R1 of the semiconductor substrate 100. Each cell active pattern CA may be defined between the device isolation patterns 102 adjacent to each other. In an example embodiment, the cell active pattern CA may have a line shape or a stripe shape having a major axis in the first direction D1. The cell active pattern CA may include impurities having the first conductive type.

On the semiconductor substrate 100, the gate structure GS may cross the cell active pattern CA and the device isolation pattern 102. The gate structures GS may each have a line shape extending along the second direction D2. The gate dielectric layer 111 may be disposed between the semiconductor substrate 100 and the cell gate electrode CG.

The gate structure GS may comprise, for example, one or more of a doped semiconductor material, a metal, a conductive metal nitride and a metal-semiconductor compound. The gate dielectric layer 111 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric.

The source/drain regions 130 may be disposed in the cell active pattern CA at opposite sides of each cell gate electrode CG. The source/drain regions 130 may be doped with a dopant having a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type) of the cell active pattern CA.

The lower dielectric layer 210 may cover the entire surface of the semiconductor substrate 100. For example, the lower dielectric layer 210 may cover the selection transistor.

The source line SL may penetrate the lower dielectric layer 210 and may be connected to one of the source/drain regions 130. The source line SL may extend parallel to the gate structure GS. When viewed in a plan view, each source line SL may be disposed between the gate structures GS adjacent to each other. The top surfaces of the source lines SL may be coplanar or substantially coplanar with the top surface of the lower dielectric layer 210. The contact plug ACP may penetrate the lower dielectric layer 210 and may be electrically connected to the source/drain region 130.

According to some example embodiments, the source line SL and the contact plug ACP may have the same characteristics as those of the contact structure described above.

The contact pins ACP may have disposed thereon conductive pads 225 disposed in the dielectric layer 220, and an intermediate dielectric layer 230 may be disposed on the conductive pads 225. A lower contact plug 235 may be disposed in the intermediate dielectric layer 230. The data storage pattern DSP may be disposed on the intermediate dielectric layer 230. The data storage patterns DSP may be arranged to be spaced apart from each other along a first direction D1 and a second direction D2 intersecting each other when viewed in a plan view, and may be coupled to the corresponding lower contact pins 235. The data storage pattern DSP may be coupled to the corresponding source/drain region 130 through the lower contact plug 235 and the contact plug ACP. For example, the data storage pattern DSP may be electrically connected to the corresponding selection transistor.

The bottom electrode BE may BE disposed between the data storage pattern DSP and the lower contact plug 235. The top electrode TE may be disposed on the top surface of the data storage pattern DSP. The top electrode TE, the data storage pattern DSP, and the bottom electrode BE may have sidewalls aligned with each other.

The bottom electrode BE and the top electrode TE may comprise a conductive metal nitride. For example, the bottom electrode BE may include one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

An upper dielectric layer 240 filling the space between the data storage patterns DSP may be disposed on the intermediate dielectric layer 230.

The upper dielectric layer 240 may have disposed thereon a bit line BL disposed in the dielectric layer 250. Each bit line BL may be in contact with a top electrode TE arranged in the first direction Dl.

Fig. 14 illustrates a cross-sectional view showing a semiconductor device according to some example embodiments of the inventive concepts. For the sake of brevity of description, the same technical features as those of the embodiment discussed with reference to fig. 1 and 2 may be omitted. In the example embodiment shown in fig. 14, the contact structure CP may electrically connect the upper connection line UCL to the lower connection line LCL.

For example, referring to fig. 14, a gate structure GS may be provided on the semiconductor substrate 100 across the active pattern 101. The source/drain patterns 130 may be disposed in the active pattern 101 at opposite sides of each gate structure GS. The source/drain pattern 130 may be doped with a dopant having a second conductivity type (e.g., n-type) different from the first conductivity type (e.g., p-type) of the active pattern 101.

The lower dielectric layer 210 may cover the gate structure GS and the source/drain pattern 130. The contact plug ACP may penetrate the interlayer dielectric layer 163 and may be electrically coupled to the source/drain pattern 130. In example embodiments, the lower dielectric layer 210 is shown covering the gate structure GS and the source/drain pattern 130, but the lower dielectric layer 210 may cover the capacitor, the resistor, the contact plug, and the connection line formed on the semiconductor substrate 100.

The lower dielectric layer 210 may have a lower connection line LCL disposed in the dielectric layer 220 disposed thereon.

The middle dielectric layer 230 and the upper dielectric layer 240 may be stacked on the lower connection line LCL, and the contact structure CP may penetrate the middle dielectric layer 230 and the upper dielectric layer 240 and may be coupled to the lower connection line LCL. As described above, the contact structure CP may include: a lower contact pattern 140 including a first metal, a metal barrier 145 including a second metal, and an upper contact pattern 150 including a third metal. The lower portion of the upper contact pattern 150 may be disposed in a recess defined by the top surface of the lower contact pattern 140.

The upper connection line UCL disposed in the dielectric layer 250 may intersect the lower connection line LCL and may be coupled to the contact structure CP.

According to some example embodiments of the inventive concepts, a semiconductor device may include a contact structure having a lower contact pattern and an upper contact pattern. The upper contact pattern may include a second metal having a resistivity below a certain width lower than that of the first metal of the lower contact pattern, and a portion of the upper contact pattern may be disposed in the recess of the lower contact pattern. Accordingly, the lower contact pattern may have a reduced resistivity, and in turn, the resistivity of the contact structure may be reduced. Accordingly, signal delay through the contact structure can be reduced, thereby improving the operation speed of the semiconductor device.

Although the present inventive concept has been described in connection with some exemplary embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the present inventive concept.