Semiconductor element with embedded sigma-shaped structure and manufacturing method thereof
阅读说明：本技术 具有内埋σ形结构的半导体元件及其制造方法 (Semiconductor element with embedded sigma-shaped structure and manufacturing method thereof ) 是由 黄登烟 于 2020-06-23 设计创作，主要内容包括：本公开提供一种具有内埋Σ形结构的半导体元件及其制造方法。该半导体元件包括一半导体基板、一半导体鳍片、以及一经填充的沟槽。该半导体鳍片从该半导体基板向上延伸。该经填充的沟槽形成于该半导体鳍片中且包括一第一Σ部分、一第二Σ部分、以及一中间部分。该第一Σ部分由一半导体缓冲区域部分地填充,且该第一Σ部分的一未填充部分由生长在该半导体缓冲区域上的一经掺杂的半导体区域填充。该第二Σ部分由该半导体缓冲区域填充。该中间部分将该第一Σ部分连接至该第二Σ部分,且该中间部分由该半导体缓冲区域填充。(The present disclosure provides a semiconductor device having a buried sigma-shaped structure and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate, a semiconductor fin, and a filled trench. The semiconductor fin extends upward from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first Σ portion, a second Σ portion, and an intermediate portion. The first sigma-delta is partially filled by a semiconductor buffer region, and an unfilled portion of the first sigma-delta is filled by a doped semiconductor region grown on the semiconductor buffer region. The second Σ portion is filled by the semiconductor buffer region. The intermediate portion connects the first sigma portion to the second sigma portion, and the intermediate portion is filled by the semiconductor buffer region.)
1. A semiconductor component, comprising:
a semiconductor substrate;
a semiconductor fin extending upward from the semiconductor substrate; and
a filled trench formed in the semiconductor fin, wherein the filled trench comprises:
a first sigma-delta portion partially filled by a semiconductor buffer region, wherein an unfilled portion of the first sigma-delta portion is filled by a doped semiconductor region grown on the semiconductor buffer region;
a second sigma portion filled by the semiconductor buffer region; and
an intermediate portion connecting the first sigma portion to the second sigma portion, wherein the intermediate portion is filled by the semiconductor buffer region.
2. The semiconductor device of claim 1, further comprising a gate structure formed over said semiconductor fin, wherein said gate structure comprises a gate stack spanning a channel portion of said semiconductor fin and a gate spacer present on sidewalls of said gate stack.
3. The semiconductor device of claim 2, wherein said first Σ portion comprises a horizontal tip region extending below said gate spacer and a bottom region extending towards said semiconductor substrate.
4. The semiconductor device as defined in claim 3, wherein the semiconductor buffer region fills the horizontal tip region and the bottom region of the first Σ portion.
5. The semiconductor device of claim 2, wherein said filled trench has sidewalls vertically coincident with outer sidewalls of said gate spacer.
6. The semiconductor device of claim 1, wherein a depth of said second Σ portion is greater than a depth of said first Σ portion.
7. A method for manufacturing a semiconductor device includes:
providing a semiconductor substrate;
forming a trench in a semiconductor substrate, wherein the trench includes a first Σ portion, a second Σ portion, and an intermediate portion connecting the first and second Σ portions;
epitaxially growing a semiconductor buffer region in the trench, wherein the semiconductor buffer region fills the second Σ portion, the intermediate portion, and a portion of the first Σ portion; and
epitaxially growing a doped semiconductor region on the semiconductor buffer region, wherein the doped semiconductor region fills an unfilled portion of the first Σ portion.
8. The manufacturing method of a semiconductor element according to claim 7, further comprising:
forming a gate structure over a semiconductor fin extending upward from the semiconductor substrate, wherein the gate structure includes a gate stack spanning a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack; and
a horizontal tip region extending below the gate spacer and a bottom region extending toward the semiconductor substrate are formed in the first Σ portion.
9. The method of claim 8, wherein forming the trench further comprises:
forming an initial cavity by performing an anisotropic etch to remove a portion of the semiconductor fin on each side of the gate structure, wherein the initial cavity has a sidewall that vertically coincides with an outer sidewall of the gate spacer; and
an oxide ring is formed on a middle portion of the sidewall of the initial cavity.
10. The method of claim 9, wherein forming said trench further comprises performing a crystallographic anisotropic etch to form said first Σ portion above said oxide ring and said second Σ portion below said oxide ring, wherein said first Σ portion and said second Σ portion have facets oriented along (111).
11. The method of claim 10, wherein forming the trench further comprises removing the oxide ring from the middle portion of the sidewall of the initial cavity such that the middle portion of the trench connects the first Σ portion and the second Σ portion.
12. The method according to claim 10, wherein the crystallographic anisotropic etching uses an etchant comprising at least one of tetramethylammonium hydroxide, ammonium hydroxide, and potassium hydroxide.
13. The method for manufacturing a semiconductor device according to claim 12, wherein the etchant etches (001) and (110) crystal planes faster than (111) crystal planes.
14. A method for manufacturing a semiconductor device includes:
providing a semiconductor substrate;
forming an initial cavity by performing an anisotropic etch to remove a portion of a semiconductor fin on each side of a gate structure;
forming an oxide ring on a middle portion of the sidewall of the initial cavity;
performing a crystallographic anisotropic etch to form a first sigma-bit on the oxide ring and a second sigma-bit below the oxide ring; and
removing the oxide ring from the intermediate portion of the sidewall of the initial cavity to obtain a trench including a first Σ portion, a second Σ portion, and an intermediate portion connecting the first Σ portion and the second Σ portion.
15. The manufacturing method of a semiconductor element according to claim 14, further comprising:
forming a gate structure over a semiconductor fin extending upward from the semiconductor substrate, wherein the gate structure includes a gate stack spanning a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack; and
a horizontal tip region extending below the gate spacer and a bottom region extending toward the semiconductor substrate are formed in the first Σ portion.
16. The method of claim 15, wherein said initial cavity has a sidewall vertically coincident with an outer sidewall of said gate spacer.
17. The method of claim 16, wherein said first Σ portion and said second Σ portion have facets oriented along (111).
18. The manufacturing method of a semiconductor element according to claim 15, further comprising:
epitaxially growing a semiconductor buffer region in the trench, wherein the semiconductor buffer region fills the second Σ portion, the intermediate portion, and a portion of the first Σ portion; and
epitaxially growing a doped semiconductor region on the semiconductor buffer region, wherein the doped semiconductor region fills an unfilled portion of the first Σ portion.
19. The method of claim 18, wherein the semiconductor buffer region fills the horizontal tip region and the bottom region of the first Σ portion.
20. The method of claim 19, wherein a depth of the second Σ portion is greater than a depth of the first Σ portion.
Technical Field
The present disclosure claims priority and benefit of 2019/08/21 application U.S. official application No. 16/547,160, the contents of which are incorporated herein by reference in their entirety.
Background
In modern electronic components, the range of applications of Integrated Circuits (ICs) is expanding. In particular, the increasing demand for mobility of electronic components exhibiting high performance and low power consumption has led to a push toward ever more compact components having components with a size range shrinking to the low sub-micron (submicron) scale. Current semiconductor technology is capable of producing structures with dimensions of 10 nm. Because an IC represents a group of electronic circuit elements integrated on a semiconductor material, the IC can be made smaller than a discrete circuit made up of individual circuit components. Generally, modern integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
To enhance channel strain, embedding "sigma-shaped" structures in the source/drain regions of fin field effect transistors (finfets) has proven to be an effective approach. In one conventional method, a gate structure is formed over a semiconductor fin, and a sigma-shaped source/drain structure is buried in the sigma-shaped cavity between the gate structures. The sigma-shaped source/drain structure allows the source/drain structure to be placed in close proximity to the transistor channel region, thereby maximizing stress within the transistor channel region. However, for finfets, subsequent drive-in anneals to such sigma-shaped source/drain structures may result in non-uniform junction profiles along the fin height direction, resulting in non-uniform gate lengths in each semiconductor fin. Accordingly, it is desirable to provide buried source/drain structures and processes having uniform source/drain junction profiles.
The above description of "prior art" is merely provided as background, and it is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and that any description of "prior art" above should not be taken as an admission that it is any part of the present disclosure.
Disclosure of Invention
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin, and a filled trench. The semiconductor fin extends upward from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first Σ portion, a second Σ portion, and an intermediate portion. The first sigma-delta is partially filled by a semiconductor buffer region, and an unfilled portion of the first sigma-delta is filled by a doped semiconductor region grown on the semiconductor buffer region. The second Σ portion is filled by the semiconductor buffer region. The intermediate portion connects the first sigma portion to the second sigma portion, and the intermediate portion is filled by the semiconductor buffer region.
In some embodiments, the semiconductor device further includes a gate structure formed over the semiconductor fin, wherein the gate structure includes a gate stack spanning (straddling) a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack.
In some embodiments, the first Σ portion includes a horizontal tip region extending below the gate spacer and a bottom region extending toward the semiconductor substrate.
In some embodiments, the semiconductor buffer region fills the horizontal tip region and the bottom region of the first Σ portion.
In some embodiments, the filled trench has sidewalls that vertically coincide with outer sidewalls of the gate spacers.
In some embodiments, a depth of the second Σ portion is greater than a depth of the first Σ portion.
The present disclosure further provides a method for manufacturing a semiconductor device. The manufacturing method comprises providing a semiconductor substrate; forming a trench in a semiconductor substrate, wherein the trench includes a first Σ portion, a second Σ portion, and an intermediate portion connecting the first Σ portion and the second Σ portion; epitaxially growing a semiconductor buffer region in the trench, wherein the semiconductor buffer region fills the second Σ portion, the intermediate portion, and a portion of the first Σ portion; and epitaxially growing a doped semiconductor region on the semiconductor buffer region, wherein the doped semiconductor region fills an unfilled portion of the first Σ portion.
In some embodiments, the method of manufacturing further includes forming a gate structure over a semiconductor fin extending upward from the semiconductor substrate, wherein the gate structure includes a gate stack spanning a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack; and forming a horizontal tip region extending under the gate spacer and a bottom region extending toward the semiconductor substrate in the first Σ portion.
In some embodiments, forming the trench further comprises forming an initial cavity by performing an anisotropic etch to remove a portion of the semiconductor fin on each side of the gate structure, wherein the initial cavity has a sidewall vertically coincident with an outer sidewall of the gate spacer; and forming an oxide ring on a middle portion of the sidewall of the initial cavity.
In some embodiments, forming the trench further comprises performing a crystallographic anisotropic etch (crystallographic anisotropic etch) to form the first Σ portion above the oxide ring and the second Σ portion below the oxide ring, wherein the first and second Σ portions have facets oriented along (111).
In some embodiments, forming the trench further comprises removing the oxide ring from the middle portion of the sidewall of the initial cavity such that the middle portion of the trench connects the first Σ portion and the second Σ portion.
In some embodiments, the crystalline anisotropic etch uses an etchant comprising at least tetramethylammonium hydroxide (TMAH), ammonium hydroxide, and potassium hydroxide.
In some embodiments, the etchant etches the (001) and (110) crystallographic planes faster than the (111) crystallographic planes.
The present disclosure further provides a method for manufacturing a semiconductor device. The manufacturing method comprises providing a semiconductor substrate; forming an initial cavity by performing an anisotropic etch to remove a portion of a semiconductor fin on each side of a gate structure; forming an oxide ring on a middle portion of the sidewall of the initial cavity; performing a crystallographic anisotropic etch to form a first sigma-bit on the oxide ring and a second sigma-bit below the oxide ring; and removing the oxide ring from the intermediate portion of the sidewall of the initial cavity to obtain a trench including a first Σ portion, a second Σ portion, and an intermediate portion connecting the first Σ portion and the Σ second portion.
In some embodiments, the method of manufacturing further comprises: forming a gate structure over a semiconductor fin extending upward from the semiconductor substrate, wherein the gate structure includes a gate stack spanning (straddling) a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack; and forming a horizontal tip region extending under the gate spacer and a bottom region extending toward the semiconductor substrate in the first Σ portion.
In some embodiments, the initial cavity has a sidewall vertically coincident with an outer sidewall of the gate spacer.
In some embodiments, the first and second Σ portions have facets oriented along (111).
In some embodiments, the method of manufacturing further comprises: epitaxially growing a semiconductor buffer region in the trench, wherein the semiconductor buffer region fills the second Σ portion, the intermediate portion, and a portion of the first Σ portion; and epitaxially growing a doped semiconductor region on the semiconductor buffer region, wherein the doped semiconductor region fills an unfilled portion of the first Σ portion.
In some embodiments, the semiconductor buffer region fills the horizontal tip region and the bottom region of the first Σ portion.
In some embodiments, a depth of the second Σ portion is greater than a depth of the first Σ portion.
With the above-described configuration of the semiconductor element and the method of manufacturing the same, the volume of each source/drain cavity is increased, and more stress-generating material (stress-generating material) can be deposited therein, thereby generating more stress on the channel region of the FinFET. As a result, the operating speed of the FinFET may be greatly increased.
The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.
Drawings
Aspects of the disclosure can be read with reference to the following drawings and detailed description. It is emphasized that, in accordance with industry standard practice, the various features (features) are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of discussion.
Fig. 1 shows a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 shows a flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 3A illustrates a cross-sectional view of an exemplary semiconductor device including a semiconductor fin extending upward from a semiconductor substrate and a gate structure formed over the semiconductor fin, wherein the cross-sectional view is taken along a direction parallel to a longitudinal direction of the semiconductor fin, according to an embodiment of the present disclosure.
Fig. 3B is another cross-sectional view of the exemplary semiconductor component of fig. 3A, the cross-sectional view being taken along a direction perpendicular to the longitudinal direction of the semiconductor fin.
Figure 4 is a cross-sectional view of the semiconductor fin of the exemplary semiconductor device of figure 3A after forming initial cavities in the semiconductor fin on opposite sides of the gate structure.
Fig. 5 is a cross-sectional view after an oxide ring is formed on the sidewalls of the initial cavity of the exemplary semiconductor device of fig. 4.
Fig. 6 is a cross-sectional view after forming first and second Σ portions in the initial cavity of the exemplary semiconductor element of fig. 5.
Fig. 7 is a cross-sectional view of the exemplary semiconductor device of fig. 6 after the oxide ring has been removed from the sidewalls of the initial cavity.
Fig. 8 is a cross-sectional view of the exemplary semiconductor device of fig. 7 after epitaxially growing a semiconductor buffer region on the (111) facet of each of the first Σ portions.
Fig. 9 is a cross-sectional view of the exemplary semiconductor device of fig. 8 after forming a doped semiconductor region on each of the semiconductor buffer regions.
Description of reference numerals:
3: semiconductor device with a plurality of semiconductor chips
30: material interface
40: grid structure
50: initial cavity
50': groove
50": filled trench
52: oxide ring
60: semiconductor buffer region
80: doped semiconductor region
100: manufacturing method
200: manufacturing method
300: semiconductor device with a plurality of semiconductor chips
302: semiconductor substrate
304: semiconductor fin
304': channel region
308: shallow trench isolation
402: grid cover
404: grid electrode
406: gate dielectric
408: gate spacer
502: first sigma part
502': first sigma part
503: first horizontal tip region
504: middle part
504': middle part
505: second horizontal tip region
506: second sigma part
506': second sigma part
S102: step (ii) of
S104: step (ii) of
S106: step (ii) of
S108: step (ii) of
S202: step (ii) of
S204: step (ii) of
S206: step (ii) of
S208: step (ii) of
S210: step (ii) of
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of embodiments of the disclosure. Examples of specific elements and arrangements thereof are described below to simplify the embodiments of the present disclosure. These are, of course, merely examples and are not intended to limit the scope of the embodiments of the disclosure in any way. For example, when reference is made in the description to a first element being formed "on" or "over" a second element, it can include embodiments in which the first element is in direct contact with the second element, and can also include embodiments in which other elements are formed therebetween without direct contact. In addition, the present disclosure may repeat reference numerals and/or symbols in various embodiments. These iterations are not intended to define relationships between the various embodiments and/or structures discussed for simplicity and clarity.
Furthermore, spatially related terms are used therein, such as: "below," "lower," "above," "upper," and similar terms in the … … figures are used for convenience in describing the relationship of one element or component to another element or component. These spatial relationships are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be turned to a different orientation (rotated 90 degrees or otherwise), and the spatially relative adjectives used herein may be similarly interpreted.
Fig. 1 illustrates a flow chart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. In some embodiments, the manufacturing method 100 includes a number of steps S102, S104, S106, and S108, and the following description and illustrations are not to be considered as limiting the order of the steps. In step S102, a semiconductor substrate 302 is provided, as shown in fig. 3A to 3B. In step S104, a trench 50' is formed in the semiconductor substrate 302, as shown in fig. 7. In some embodiments, the trench 50' includes a first Σ portion 502, a second Σ portion 506, and an intermediate portion 504 connecting the first and second Σ portions. In step S106, a semiconductor buffer region 60 is epitaxially grown in the trench 50'. In some embodiments, the semiconductor buffer region 60 fills a portion of the second Σ portion 506, the intermediate portion 504, and the first Σ portion 502, as shown in fig. 8. In step S108, a doped semiconductor region 80 is epitaxially grown on the semiconductor buffer region 60, as shown in fig. 9. In some embodiments, the doped semiconductor region 80 fills an unfilled portion of the first Σ portion 502.
Fig. 2 illustrates a flow chart of a method 200 for fabricating a semiconductor device according to an embodiment of the present disclosure. In some embodiments, the manufacturing method 200 includes a number of steps S202, S204, S206, S208, and S210, and the following description and illustrations are not to be considered as limiting the order of the steps. In step S202, a semiconductor substrate 302 is provided, as shown in fig. 3A to 3B. In step S204, an initial cavity 50 is formed by performing an anisotropic etch to remove a portion of the semiconductor fin 304 on each side of the gate structure 40, as shown in fig. 4. In step S206, an oxide ring 52 is formed on a middle portion of the sidewall of the initial cavity 50, as shown in fig. 5. In step S208, a crystallographic anisotropic etch is performed to form the first Σ portion 502 above the oxide ring 52 and the second Σ portion 506 below the oxide ring 52, as shown in fig. 6. In step S210, the oxide ring 52 is removed from the intermediate portion of the sidewalls of the initial cavity 50 to obtain a trench 50' comprising a first Σ portion 502, a second Σ portion 506, and an intermediate portion 504 connecting the first Σ portion 502 and the second Σ portion 506.
Fig. 3A illustrates a cross-sectional view of an exemplary semiconductor device 3 according to an embodiment of the present disclosure, including a semiconductor fin extending upward from a semiconductor substrate and a gate structure formed over the semiconductor fin. Fig. 3B is another cross-sectional view of the exemplary semiconductor component of fig. 3A, the cross-sectional view being taken along a direction perpendicular to the longitudinal direction of the semiconductor fin.
Referring to fig. 3A-3B, the semiconductor device includes a semiconductor fin 304 extending upward from a semiconductor substrate 302 and a gate structure 40 formed over the semiconductor fin 304. Although only a single semiconductor fin 304 is shown, some embodiments may include multiple semiconductor fins formed over the semiconductor substrate 302.
The exemplary semiconductor structure shown in fig. 3A-3B may be formed by first providing a bulk semiconductor substrate (not shown). "bulk semiconductor substrate" refers to a substrate that is composed entirely of at least one semiconductor material having semiconductor properties. In the present disclosure, at least an upper portion of the bulk semiconductor substrate is composed of a semiconductor material including, for example, silicon (Si), germanium (Ge), a silicon germanium (SiGe) alloy, a carbon-doped silicon (Si: C) alloy, a III-V group compound semiconductor, or a II-VI group compound semiconductor. In one embodiment, the semiconductor substrate is entirely comprised of silicon.
The at least one semiconductor material providing the bulk semiconductor substrate may be monocrystalline, polycrystalline, or amorphous. In one example, the bulk semiconductor substrate is composed entirely or at least in an upper portion of a single crystalline semiconductor material (e.g., monocrystalline silicon). In some embodiments, the thickness of the semiconductor substrate may be between about 30 μm and about 2mm, although lesser and greater thicknesses may also be employed.
After providing the bulk semiconductor substrate, the bulk semiconductor substrate is patterned to provide the semiconductor fins 304. In the present disclosure, the semiconductor fins 304 are formed in an upper portion of the bulk semiconductor substrate, while the semiconductor substrate 302 represents the remaining lower portion of the bulk semiconductor substrate. The material interface 30 may or may not be present between the semiconductor fin 304 and the semiconductor substrate 302. The semiconductor fins 304 may have a circular or rectangular shape. In an embodiment of the present disclosure, the semiconductor fin 304 has a width between 5nm and 30nm, although smaller or larger widths may also be used. The height of the semiconductor fins 304 may be between 30nm and 200nm, although smaller or larger heights may also be used. If multiple fins are formed, each semiconductor fin 304 is spaced a distance from its nearest neighbor semiconductor fin 304. In an embodiment, the distance between adjacent semiconductor fins 304 may be between 20nm and 1000 nm. The semiconductor fins 304 are oriented parallel to each other.
The semiconductor fins 304 may be formed by patterning an upper portion of a bulk semiconductor substrate. In an embodiment of the present disclosure, the patterning for providing the semiconductor fins 304 may include photolithography and etching. Photolithography includes forming a photoresist layer (not shown) on top of a semiconductor substrate. The photoresist layer may comprise a positive-tone photoresist material, a negative-tone photoresist material, or a hybrid-tone photoresist material. The photoresist layer may be formed by a deposition process such as spin coating. After the photoresist layer is formed, the photoresist layer is subjected to patterned irradiation. Next, the exposed photoresist layer is developed using a conventional photoresist developer. Thus, a patterned photoresist layer is provided on top of the semiconductor substrate to be patterned. Thereafter, at least one pattern transfer etch process is utilized to transfer the pattern provided by the patterned photoresist layer to the underlying semiconductor substrate. Generally, at least one pattern transfer etch process is an anisotropic etch. In one embodiment, a dry etch, such as Reactive Ion Etch (RIE), may be used. In another embodiment, a wet etch with a chemical etchant may be used. In yet another embodiment, a combination of dry and wet etching may be used. In the illustrated embodiment, the etching stops in a portion of the bulk semiconductor substrate.
In another embodiment of the present disclosure, providing the patterning of the semiconductor fins 304 may include a Sidewall Image Transfer (SIT) process. The SIT process includes forming a layer of mandrel material (not shown) on top of the bulk semiconductor substrate to be patterned. The layer of mandrel material may comprise any material (semiconductor, dielectric, or conductive material) that may be selectively removed from the structure during a subsequent etching process. In one embodiment, the layer of mandrel material may be comprised of amorphous silicon or polysilicon. In another embodiment, the mandrel material layer may be composed of a metal such as Al, W, or Cu. The mandrel material layer may be formed by, for example, Chemical Vapor Deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). In a subsequent deposition of a layer of mandrel material, the layer of mandrel material may be patterned by photolithography and etching to form a plurality of mandrel structures (also not shown) on the uppermost surface of the bulk semiconductor substrate.
The SIT process continues with the formation of spacers on each sidewall of each mandrel structure. The spacers may be formed by depositing a spacer material followed by etching the deposited spacer material. The spacer material may comprise any material having a different etch selectivity than the mandrel material. Examples of deposition processes that may be used to deposit the spacer material include, for example, CVD, PECVD, or Atomic Layer Deposition (ALD). Examples of the etching for providing the spacer include any etching process such as RIE.
After the spacers are formed, the SIT process continues by removing each mandrel structure. Each mandrel structure may be removed by an etch process that selectively removes the mandrel material. After the mandrel structures are removed, the SIT process is continued to transfer the pattern provided by the spacers to the underlying semiconductor substrate. The pattern transfer may be achieved by using at least one etching process. Examples of etching processes that may be used to transfer the pattern may include dry etching (i.e., RIE, plasma etching, ion beam etching, or laser ablation) and/or wet etching. In an embodiment, the etching process for transferring the pattern may include one or more RIE steps. After the pattern transfer is completed, the spacers are removed from the structure as the end of the SIT process. The spacers may be removed by an etching or planarization process.
After the semiconductor fin 304 is formed, a Shallow Trench Isolation (STI) 308 is formed to surround the base of the semiconductor fin 304. STI 308 may comprise a dielectric oxide, such as silicon dioxide. The STI 308 may be formed by depositing a dielectric material over the semiconductor substrate 302 and semiconductor fins 304 using conventional deposition techniques, such as CVD or PVD, and planarizing the deposited dielectric material by conventional planarization techniques, such as Chemical Mechanical Planarization (CMP), and then etching back the deposited dielectric material to a desired thickness. In some embodiments, the planarization step may be omitted. An anisotropic etch such as RIE may be employed to remove the dielectric material of the STI 308 selective to the semiconductor material of the semiconductor fin 304.
Still referring to fig. 3A-3B, a gate structure 40 is formed over the semiconductor fin 304. The gate structure 40 includes gate stacks spanning the channel region 304' (i.e., the active fin region) of the semiconductor fin 304 and gate spacers 408 present on sidewalls of each gate stack. The term "cross over" refers to the gate stack being in direct contact with the top surface and the two vertical sidewalls of the semiconductor fin. The gate stack may include a gate dielectric 406, a gate electrode 404, and a gate cap 402 from bottom to top, and may be formed by any process known in the art, including gate-first and gate-last processes.
In a gate-first process, the gate stacks (402, 404, 406) may be formed by providing a material stack (not shown) and lithographically patterning the material stack. The material stack includes, from top to bottom, a gate cap layer, a gate electrode layer, and a gate dielectric layer over the semiconductor fin 304, the STI 308, and the semiconductor substrate 302.
The gate dielectric layer may comprise any suitable insulating material including, but not limited to, an oxide, nitride, or oxynitride. In one embodiment, the gate dielectric layer may comprise a high dielectric constant (high-k) dielectric having a dielectric constant greater than that of silicon dioxide. Exemplary high-k dielectrics include, but are not limited to HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、LaAlOxNy、Y2OxNy、SiON、SiNxThe aforementioned silicates, and the aforementioned alloys. Each value of x is independently between 0.5 and 3, and each value of y is independently between 0 and 2. In some embodiments, a multi-layer gate dielectric structure may be formed that includes different gate dielectric materials (e.g., silicon dioxide) and a high-k dielectric. The gate dielectric layer may be formed by any deposition technique including, for example, CVD, PECVD, PVD, or Atomic Layer Deposition (ALD). Alternatively, the gate dielectric layer may be formed by a thermal growth process, such as oxidation, nitridation, or oxynitridation, to convert a surface portion of the semiconductor fin 304 into a dielectric material. The gate dielectric layer may be formed to a thickness of between 0.5nm and 10nm, more typically between about 0.5nm and about 3 nm.
The gate electrode layer may comprise any conductive material including, for example, doped polysilicon, elemental metals (such as W, Ti, Ta, Al, Ni, Ru, Pd, and Pt), alloys of at least two elemental metals, metal nitrides (such as WN and TiN), metal silicides (such as WSi, NiSi, and TiSi), or multilayer combinations of the foregoing. The gate electrode layer may be formed using a deposition process including, for example, CVD, PECVD, PVD, or ALD. In embodiments using polysilicon or SiGe as the gate electrode material, an in-situ deposition process may be used, or alternatively a method of ion implantation followed by deposition may be used. The thickness of the gate electrode layer formed may be between 50nm and 200nm, although lesser or greater thicknesses may also be employed.
The gate cap may include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride. In one embodiment of the present disclosure, the gate cap layer comprises silicon nitride. The gate cap layer may be formed by a deposition process including, for example, CVD, PECVD, PVD, or ALD. The thickness of the gate cap layer formed may be between 25nm and 100nm, although lesser or greater thicknesses may also be used.
The photolithographic patterning of the material stack may be performed by anisotropic etching, which may be dry etching (e.g., RIE) or wet etching. Each remaining portion of the gate dielectric layer forms a gate dielectric 406, each remaining portion of the gate electrode layer forms a gate electrode 404, and each remaining portion of the gate cap layer forms a gate cap 402.
In a gate-last process, the gate stack (402, 404, 406) may include a sacrificial gate (not shown) that may be later removed and replaced with a gate dielectric and gate electrode such as described above in a gate-first process. In an exemplary embodiment, the sacrificial gate may be formed of polysilicon with a sacrificial dielectric material (e.g., silicon dioxide) formed using deposition techniques known in the art, including, for example, ALD, CVD, and PVD.
Each gate spacer 408 may comprise a dielectric material, such as: an oxide, a nitride, an oxynitride, or any combination of the foregoing. In one embodiment, each gate spacer 408 is comprised of silicon nitride. The gate spacers 408 may be formed by first providing a conformal layer of gate spacer material (not shown) on exposed surfaces of the gate stack (402, 404, 406), the semiconductor fin 304, the STI 308, and the semiconductor substrate 302, and then etching the layer of gate spacer material to remove horizontal portions of the layer of gate spacer material. The layer of gate spacer material may be provided by a deposition process including, for example, CVD, PECVD, or ALD. The etching of the layer of gate spacer material may be performed by a dry etching process (e.g., RIE). The remaining vertical portions of the layer of gate spacer material constitute gate spacers 408. The width of each gate spacer 408, as measured at the bottom of the gate spacer 408, may be between 5nm and 100nm, although lesser or greater thicknesses may be employed.
Fig. 4 shows the semiconductor structure of the exemplary semiconductor structure of fig. 3A after forming initial cavities 50 in the semiconductor fins 304 on opposite sides of the gate structure 40. The initial cavity 50 may have a rectangular shape with substantially vertical sidewalls. The sidewalls of the initial cavity chamber 50 are vertically coincident (i.e., vertically aligned) with the outer sidewalls of the gate spacers 408. The initial cavity 50 may be formed by performing an anisotropic etch that removes portions of the semiconductor fin 304 not covered by the gate structure 40. In one embodiment, a RIE process using, for example, chlorine may be performed. In some embodiments, the depth of the initial cavity 50 may be about 5nm to 10nm, although lesser or greater depths may be employed.
Fig. 5 shows the semiconductor structure of fig. 4 after an oxide ring 52 is formed on a middle portion of the sidewalls of the initial cavity 50 of the semiconductor structure by performing an annealing process. An annealing process is performed in an oxygen-containing ambient to selectively oxidize a middle portion of the sidewalls of the initial cavity 50 to form an oxide ring 52. The annealing is preferably performed at a temperature between about 900 ℃ and 1150 ℃, and more preferably at a temperature of about 1050 ℃.
Fig. 6 shows the semiconductor structure after forming the first Σ portion 502 and the second Σ portion 506 in the initial cavity 50 of the exemplary semiconductor structure of fig. 5 by performing a crystallographic anisotropic etch. The crystallographic anisotropic etch is also referred to as a sigma cavity etch. In some embodiments, the sigma cavity etch may comprise a wet etch using, for example, tetramethylammonium hydroxide (TMAH), ammonium hydroxide, and/or potassium hydroxide as an etchant. The etchant etches the (001) and (110) crystallographic planes faster than the (111) crystallographic planes, forming first Σ portions 502 with facets oriented along the (111) planes (hereinafter referred to as (111) facets). The first Σ portion 502 comprises a first horizontal tip region 503, which first horizontal tip region 503 protrudes in the lateral direction towards the adjacent channel region 304' and extends below the gate spacer 408. The first horizontal tip region 503 comprises the intersection of two facets. In some embodiments, the depth of the second Σ portion 506 is greater than the depth of the first Σ portion 502. The second Σ portion 506 also comprises a second horizontal tip region 505, which second horizontal tip region 505 protrudes in the lateral direction towards the adjacent channel region 304' and extends below the gate spacer 408. In some embodiments, the second horizontal tip region 505 protrudes farther than the first horizontal tip region 503.
Fig. 7 shows the semiconductor structure after removal of the oxide ring 52 from the middle portion of the sidewalls of the initial cavity 50 of the exemplary semiconductor structure of fig. 6 to obtain a trench 50'. The trench 50' includes an intermediate portion 504 connecting a first Σ portion 502 and a second Σ portion 506.
Fig. 8 shows the semiconductor structure after epitaxially growing a semiconductor buffer region 60 on the (111) facet of the first Σ portion 502 in the exemplary semiconductor device of fig. 7. The terms "epitaxial growth and/or deposition" and "epitaxially forming and/or growing" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the semiconductor material being grown may have the same crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and system parameters are set so that the deposited atoms have sufficient energy to reach the deposition surface of the semiconductor substrate to travel over the surface and orient them into a crystalline arrangement of atoms of the deposition surface. Thus, the epitaxial semiconductor material may have the same crystalline characteristics as the deposition surface that may be formed thereon. For example, epitaxial semiconductor material deposited on a (111) crystal surface may exhibit a (111) orientation. In some embodiments, the epitaxial growth and/or deposition process may be selective to formation on semiconductor surfaces and may not deposit material on dielectric surfaces (such as silicon dioxide or silicon nitride surfaces).
The semiconductor buffer region 60 may comprise an intrinsic (i.e., undoped) semiconductor material having a lattice constant that is greater than or less than a lattice constant of a semiconductor material providing the semiconductor fins 304, such that the semiconductor buffer region 60 introduces stress to the channel regions 304' of the semiconductor fins 304. If the lattice constant of the semiconductor material providing the semiconductor buffer region 60 is larger than the lattice constant of the semiconductor material providing the semiconductor fin 304, a tensile stress may be applied to the channel region 304'. For example, in the case where the semiconductor fin 304 is comprised of silicon, for a p-type FinFET, the semiconductor buffer region 60 may comprise a SiGe alloy containing, for example, about 10-80 atomic% germanium to induce a tensile stress toward the channel region 304'; for an n-type FinFET, the semiconductor buffer region 60 may comprise Si: c alloy, the Si: the C alloy contains, for example, about 0.4-3.0 atomic% carbon to induce tensile stress toward the channel region 304'.
The semiconductor buffer region 60 may be formed by a first selective epitaxial growth process. The first selective epitaxial growth process deposits semiconductor material that provides the semiconductor buffer region 60 only on the semiconductor surfaces (i.e., the (111) facet) and not on dielectric surfaces like the gate cap 402, the gate spacer 408, and the STI 308. In one embodiment, the semiconductor buffer region 60 is formed by, for example, CVD, Molecular Beam Epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or other suitable process.
Since the epitaxial growth rate in the (111) plane is significantly less than the epitaxial growth rate in the (110) and (100) planes (where (100) is the fastest), the deposited semiconductor material grows faster in the first horizontal tip region 503, the middle portion 504, and the second Σ portion 506 than in the sidewall region with the (111) facets. A selective epitaxial growth process may be performed such that the semiconductor buffer region 60 completely fills the first horizontal tip region 503 and the intermediate portion 504 and the second Σ portion 506, and the remaining unfilled portion of the first Σ portion 502 is box-shaped (box shape) with substantially vertical sidewalls. Because the growth is fastest at the intermediate portion 504 and the second Σ portion 506, the thickness of the horizontal portion of each semiconductor buffer region 60 is greater than the thickness of the vertical portion. At this point in the manufacturing method, as shown in fig. 8, a portion of the first Σ portion 502 remains unfilled after the semiconductor buffer region 60 is formed.
Fig. 9 shows the semiconductor structure of fig. 8 after forming a doped semiconductor region 80 on each semiconductor buffer region 60 to completely fill the remaining unfilled portion of the first Σ portion 502. As a result, a filled trench 50 ″ is obtained comprising a first Σ -portion 502', a second Σ -portion 506', and an intermediate portion 504 '. As can be seen, the first Σ portion 502', the second Σ portion 506', and the intermediate portion 504' correspond to the first Σ portion 502, the second Σ portion 506, and the intermediate portion 504 after being filled with the semiconductor buffer region 60 and/or the doped semiconductor region. Each doped semiconductor region 80 and the underlying semiconductor buffer region 60 form a source/drain structure. The doped semiconductor region 80 may comprise a semiconductor material that may induce the same type of stress to the channel region 304' of the semiconductor fin 304 as the semiconductor buffer region 60 therebelow. In an embodiment, the doped semiconductor region 80 may comprise the same semiconductor material as the semiconductor buffer region 60. The doped semiconductor region 80 also includes a p-type or n-type dopant. The word "P-type" refers to the addition of impurities to an intrinsic semiconductor that results in a deficiency of valence electrons. Examples of P-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of impurities that contribute free electrons to the intrinsic semiconductor. Examples of N-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, and phosphorus. In an embodiment, for a p-type FinFET, the doped semiconductor region 80 may be comprised of boron doped SiGe, while for an n-type FinFET, the doped semiconductor region 80 may be comprised of phosphorus doped Si: and C, forming. The dopant concentration of the doped semiconductor region 80 may be at 1.0 × 1020Atom/cm3And 3.0X 1021Atom/cm3Although smaller or larger atomic concentrations may also be used.
The doped semiconductor region 80 may be formed by a second selective epitaxial growth process. The second selective epitaxial growth process deposits the doped semiconductor material by in-situ doping, and is referred to herein as an in-situ doped selective epitaxial growth process.
After the doped semiconductor region 80 is provided, the dopants in the doped semiconductor region 80 may be activated by thermal annealing. The thermal annealing may be performed by a rapid thermal annealing process, a laser annealing process, or a furnace annealing process. During the annealing process, dopants contained within the doped semiconductor region 80 diffuse into the semiconductor buffer region 60 and the semiconductor fin 304, forming source/drain junctions between the doped semiconductor region 80 and the channel region 304'. In the present disclosure, since the doped semiconductor region 80 has substantially vertical sidewalls, a uniform source/drain junction is formed between the channel region 304' and the doped semiconductor region 80 along the fin height direction after annealing. The problem of undesirable gate length variations encountered in the prior art can thus be solved.
With the above-described configuration of the semiconductor element and the method of manufacturing the same, the volume of each source/drain cavity is increased, and more stress generating material can be deposited therein, thereby generating more stress on the channel region of the FinFET. As a result, the operating speed of the FinFET may be greatly increased.
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor fin, and a filled trench. The semiconductor fin extends upward from the semiconductor substrate. The filled trench is formed in the semiconductor fin and includes a first Σ portion, a second Σ portion, and an intermediate portion. The first sigma-delta is partially filled by a semiconductor buffer region, and an unfilled portion of the first sigma-delta is filled by a doped semiconductor region grown on the semiconductor buffer region. The second Σ portion is filled by the semiconductor buffer region. The intermediate portion connects the first sigma portion to the second sigma portion, and the intermediate portion is filled by the semiconductor buffer region.
The present disclosure further provides a method for manufacturing a semiconductor device. The manufacturing method comprises providing a semiconductor substrate; forming a trench in a semiconductor substrate, wherein the trench includes a first Σ portion, a second Σ portion, and an intermediate portion connecting the first and second Σ portions; epitaxially growing a semiconductor buffer region in the trench, wherein the semiconductor buffer region fills the second Σ portion, the intermediate portion, and a portion of the first Σ portion; and epitaxially growing a doped semiconductor region on the semiconductor buffer region, wherein the doped semiconductor region fills an unfilled portion of the first Σ portion.
The present disclosure further provides a method for manufacturing a semiconductor device. The manufacturing method comprises providing a semiconductor substrate; forming an initial cavity by performing an anisotropic etch to remove a portion of a semiconductor fin on each side of a gate structure; forming an oxide ring on a middle portion of the sidewall of the initial cavity; performing a crystallographic anisotropic etch to form a first sigma-bit on the oxide ring and a second sigma-bit below the oxide ring; and removing the oxide ring from the intermediate portion of the sidewall of the initial cavity to obtain a trench including a first Σ portion, a second Σ portion, and an intermediate portion connecting the first Σ portion and the Σ second portion.
Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.
Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.