阅读说明：本技术 一种具有表面和体内双沟道的横向超结薄层soi-ldmos器件 (Transverse super-junction thin-layer SOI-LDMOS device with surface and body double channels ) 是由 陈伟中 秦海峰 王礼祥 许峰 黄义 于 2020-12-04 设计创作，主要内容包括：本发明涉及一种具有表面和体内双沟道的横向超结薄层SOI-LDMOS器件,属于半导体功率器件技术领域。该器件在传统表面栅薄层SOI-LDMOS器件上,在埋氧层处额外引入体内栅极并在漂移区引入P型埋层,优点：(1)在正向导通时,该器件的表面与体内同时形成两个导电沟道,使电子的注入能力有很大的提升,从而降低器件的比导通电阻。引入的P型埋层提高了漂移区N型层的浓度进而优化器件的正向导通性能,最终降低器件的比导通电阻。(2)在击穿时,P型埋层优化漂移区的电场强度分布,P型埋层与N型层相互耗尽从而使漂移区发生电荷补偿效应。(3)在埋氧层引入体内栅极,提高了器件的跨导g_m,从而使栅极电压对电流的控制能力增强。(The invention relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface channel and an internal channel, and belongs to the technical field of semiconductor power devices. On a traditional surface gate thin-layer SOI-LDMOS device, a body grid electrode is additionally introduced at a buried oxide layer, and a P-type buried layer is introduced in a drift region, so that the device has the advantages that: (1) when the device is conducted in the forward direction, two conducting channels are formed on the surface and in the body of the device at the same time, so that the injection capability of electrons is greatly improved, and the specific on-resistance of the device is reduced. The introduced P-type buried layer improves the concentration of an N-type layer of the drift region, further optimizes the forward conduction performance of the device and finally reduces the specific on-resistance of the device. (2) When the drift region breaks down, the electric field intensity distribution of the drift region is optimized by the P-type buried layer, and the P-type buried layer and the N-type layer are mutually depleted, so that the drift region generates a charge compensation effect. (3) The internal grid is introduced into the buried oxide layer, so that the transconductance g of the device is improved m Thereby enabling the control capability of the grid voltage to the currentAnd (4) enhancing.)

1. A transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel is characterized in that: the transistor comprises a source electrode contact region (1), a source electrode P + region (2), a source electrode N + region (3), a grid source isolation oxide layer (4), a surface grid oxide layer (5), a surface grid electrode contact region (6), a field oxide layer (7), a first layer of N-type drift region (8), a drain electrode contact region (9), a drain electrode N + region (10), a second layer of N-type drift region (11), an oxygen buried layer (12), a P-type buried layer (13), a substrate (14), an internal grid oxide layer (15), a P-body (16) and an internal grid contact region (17); the source electrode contact region (1) is positioned above the source electrode N + region (3) and the source electrode P + region (2), and the right side of the source electrode contact region (1) is adjacent to the left side of the grid source isolation oxide layer (4); the upper left side of the source electrode P + region (2) is contacted with the lower side of the source electrode contact region (1), the source electrode P + region (2) is also positioned in the source electrode N + region (3) and is L-shaped, and meanwhile, the rightmost side of the source electrode P + region (2) is contacted with a part of the left side of the P-body (16); the upper side of the source N + region (3) is in contact with the lower side of the source contact region (1) and the lower side of the grid source isolation oxide layer (4), the lower side of the source N + region is adjacent to the upper left side of the in-vivo grid oxide layer (15), the rightmost side of the in-vivo grid oxide layer is in contact with the left side of the P-body (16), and meanwhile, an L-shaped source P + region (2) exists in the source N + region (3); the left side of the gate-source isolation oxide layer (4) is adjacent to the right side of the source electrode contact region (1), the right side of the gate-source isolation oxide layer (4) is adjacent to the left sides of the surface gate oxide layer (5) and the surface gate electrode contact region (6), and the lower side of the gate-source isolation oxide layer is in contact with the upper right side of the source electrode N + region (3); the upper edge of the surface gate oxide layer (5) is adjacent to the lower edge of the surface gate contact region (6), the left side of the surface gate oxide layer (5) is in contact with the right lower side of the gate source isolation oxide layer (4), the right side of the surface gate oxide layer is in contact with the left lower side of the field oxide layer (7), and meanwhile, the lower edge of the surface gate oxide layer (5) is adjacent to the upper edge of the P-body (16); the lower side of the surface gate contact region (6) is in contact with the upper side of the surface gate oxide layer (5), the left side of the surface gate contact region is in contact with the upper right side of the gate source isolation oxide layer (4), and the right side of the surface gate contact region is in contact with the upper left side of the field oxide layer (7); the left side of the field oxide layer (7) is adjacent to the right sides of the surface gate oxide layer (5) and the surface gate contact region (6), the right side of the field oxide layer (7) is adjacent to the left side of the drain contact region (9), and meanwhile, the field oxide layer (7) is located above the first N-type drift region (8); the first layer of N-type drift region (8) is positioned on the upper side of the P-type buried layer (13) and the lower side of the field oxide layer (7), the left side of the first layer of N-type drift region is in contact with the right side of the P-body (16), and the right side of the first layer of N-type drift region is in contact with the left side of the drain N + region (10); the drain contact region (9) is positioned above the drain N + region (10), and the left side of the drain contact region (9) is adjacent to the right side of the field oxide layer (7); the drain N + region (10) is positioned right below the drain contact region (9), the left side of the drain N + region is in contact with the P-type buried layer (13), the right sides of the first layer N-type drift region (8) and the second layer N-type drift region (11), and the lower side of the drain N + region (10) is adjacent to the upper right side of the buried oxide layer (12); the upper side of the second layer of N-type drift region (11) is adjacent to the lower side of the P-type buried layer (13), the lower side of the second layer of N-type drift region is in contact with the upper side of the buried oxide layer (12), the left side of the second layer of N-type drift region (11) is in contact with the right side of the P-body (16), and the right side of the second layer of N-type drift region is adjacent to the left side of the drain electrode N + region (10); the lower side of the buried oxide layer (12) is adjacent to the upper side of the substrate (14), the upper side of the buried oxide layer (12) is adjacent to the lower side of the drain electrode N + region (10) and the lower side of the second layer N-type drift region (11), meanwhile, the upper left side of the buried oxide layer (12) is adjacent to the right sides of the in-vivo gate oxide layer (15) and the in-vivo gate contact region (17), and the upper left side of the buried oxide layer is in contact with the lower side of the in-vivo gate contact region (17); the P-type buried layer (13) is positioned between the first layer of N-type drift region (8) and the second layer of N-type drift region (11), the upper side of the P-type buried layer is in contact with the lower side of the first layer of N-type drift region (8), the lower side of the P-type buried layer is in contact with the upper side of the second layer of N-type drift region (11), the left side of the P-body (16) is adjacent to the right side of the P-body, and the right side of the P-body is adjacent to the left side of the; the upper side of the substrate (14) is in contact with the lower side of the buried oxide layer (12), and the substrate is positioned at the bottom of the device; the lower edge of the internal gate oxide layer (15) is in contact with the upper edge of the internal gate contact region (17), the right side of the internal gate oxide layer is in contact with the buried oxide layer (12), and meanwhile, the upper edge of the internal gate oxide layer (15) is in contact with the lower edges of the source N + region (3) and the P-body (16); the left side of the P-body (16) is in contact with the right sides of the source N + region (3) and the source P + region (2), meanwhile, the upper side of the P-body is closely adjacent to the lower side of the surface gate oxide layer (5), the lower side of the P-body is in contact with the upper right side of the internal gate oxide layer (15), and the right side of the P-body is in contact with the left sides of the P-type buried layer (13), the first N-type drift region (8) and the second N-type drift region (11); the internal grid contact region (17) is positioned on the upper left side of the buried oxide layer (12) and the lower side of the internal grid oxide layer (15), and the right side of the internal grid contact region is in contact with the buried oxide layer (12).

2. The lateral super junction thin-layer SOI-LDMOS device with surface and bulk dual channels of claim 1, wherein: the P-type buried layer (13) is doped with P-type impurities with a doping concentration range of 1 x 10¹⁶～1×10¹⁷cm^-3。

3. The lateral super junction thin-layer SOI-LDMOS device with surface and bulk dual channels of claim 1, wherein: the length of the P-type buried layer (13) is 3-7.5 mu m and can be adjusted, and the width of the P-type buried layer is 0.2-0.7 mu m and can be adjusted.

4. The lateral super junction thin-layer SOI-LDMOS device with surface and bulk dual channels of claim 1, wherein: the surface gate contact region (6) is made of doped polysilicon and metal.

5. The lateral super junction thin-layer SOI-LDMOS device with surface and bulk dual channels of claim 1, wherein: the material of the body grid contact region (17) is doped polysilicon and metal.

Technical Field

The invention belongs to the technical field of semiconductors, and relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface channel and an internal channel.

Background

SOI technology can achieve dielectric isolation of power integrated circuits by introducing dielectric layers into the device. Compared with bulk silicon technology, the SOI technology has higher integration level, extremely smaller parasitic capacitance and better isolation performance. SOI technology can greatly improve the reliability of integrated circuits, and will become a key technology in the future of manufacturing chips with high integration, high reliability, high speed and low power consumption, especially for power integrated circuits. Compared with most other novel active devices such as HEMTs, HBTs and the like, the LDMOS device (SOI-LDMOS) based On the silicon-On-Insulator technology has the characteristics of better CMOS process compatibility and convenient integration, and has the advantages of high power, high gain, high linearity, high switching characteristic, good isolation performance, excellent radiation resistance and reliability, so the LDMOS device is widely concerned by industry workers, and the research taking the SOI-LDMOS as the object has very special significance. It is mainly applied to: smart Power Integrated Circuit (SPIC), Radio Frequency Integrated Circuit (RFIC), and High Voltage Integrated Circuit (HVIC).

The voltage endurance of the SOI lateral power device is determined by the smaller lateral breakdown voltage and longitudinal breakdown voltage. Generally, increasing the lateral length of the device and reducing the doping concentration of the drift region can improve the lateral voltage endurance capability of the device, but at the same time, the on-resistance of the device is increased, thereby reducing the forward on-state performance of the device. However, the buried oxide layer and the top silicon layer of the SOI device cannot be too thick, which may cause difficulty in manufacturing the device, aggravation of self-heating phenomenon of the device, and heat dissipation problems if the buried oxide layer and the top silicon layer are too thick. When the buried oxide layer and the top silicon layer of the SOI device are too thin, the longitudinal withstand voltage capability of the device is reduced because the buried oxide layer prevents the depletion region of the device from extending to the substrate, so that the substrate does not withstand voltage. The main contradiction of the device is that the specific on-resistance is specific on-resistanceOn-resistance Ron, sp and breakdown voltage BV: ron, sp ^ BV^2.5. The specific on-resistance is reduced, and meanwhile, the breakdown voltage of the device is reduced; the breakdown voltage of the device is improved, and the specific on-resistance of the device is increased. In order to better measure the overall performance index of the device, the use of Baliga figure of merit to evaluate the figure of merit FOM (configurable element) of the device has become an important performance index, i.e., FOM-BV²/Ron,sp。

In order to solve the contradiction, the invention provides a transverse super-junction thin-layer SOI-LDMOS device with a surface channel and an internal channel. Meanwhile, a grid electrode is added on a buried oxide layer of the device, the area and transconductance of a conducting channel of the device are increased, and therefore the control capability of grid voltage of the device on current is enhanced.

Disclosure of Invention

In view of the above, the present invention is directed to a lateral super junction thin layer SOI-LDMOS device having surface and bulk dual channels.

In order to achieve the purpose, the invention provides the following technical scheme:

a transverse super-junction thin-layer SOI-LDMOS device with a surface channel and an internal channel comprises a source contact region (1), a source P + region (2), a source N + region (3), a grid source isolation oxide layer (4), a surface grid oxide layer (5), a surface grid contact region (6), a field oxide layer (7), a first N-type drift region (8), a drain contact region (9), a drain N + region (10), a second N-type drift region (11), a buried oxide layer (12), a P-type buried layer (13), a substrate (14), an internal grid oxide layer (15), a P-body (16) and an internal grid contact region (17). The source electrode contact region (1) is positioned above the source electrode N + region (3) and the source electrode P + region (2), and the right side of the source electrode contact region (1) is adjacent to the left side of the grid source isolation oxide layer (4); the upper left side of the source electrode P + region (2) is contacted with the lower side of the source electrode contact region (1), the source electrode P + region (2) is also positioned in the source electrode N + region (3) and is L-shaped, and meanwhile, the rightmost side of the source electrode P + region (2) is contacted with a part of the left side of the P-body (16); the upper side of the source N + region (3) is in contact with the lower side of the source contact region (1) and the lower side of the grid source isolation oxide layer (4), the lower side of the source N + region is adjacent to the upper left side of the in-vivo grid oxide layer (15), the rightmost side of the in-vivo grid oxide layer is in contact with the left side of the P-body (16), and meanwhile, an L-shaped source P + region (2) exists in the source N + region (3); the left side of the gate-source isolation oxide layer (4) is adjacent to the right side of the source electrode contact region (1), the right side of the gate-source isolation oxide layer (4) is adjacent to the left sides of the surface gate oxide layer (5) and the surface gate electrode contact region (6), and the lower side of the gate-source isolation oxide layer is in contact with the upper right side of the source electrode N + region (3); the upper edge of the surface gate oxide layer (5) is adjacent to the lower edge of the surface gate contact region (6), the left side of the surface gate oxide layer (5) is in contact with the right lower side of the gate source isolation oxide layer (4), the right side of the surface gate oxide layer is in contact with the left lower side of the field oxide layer (7), and meanwhile, the lower edge of the surface gate oxide layer (5) is adjacent to the upper edge of the P-body (16); the lower side of the surface gate contact region (6) is in contact with the upper side of the surface gate oxide layer (5), the left side of the surface gate contact region is in contact with the upper right side of the gate source isolation oxide layer (4), and the right side of the surface gate contact region is in contact with the upper left side of the field oxide layer (7); the left side of the field oxide layer (7) is adjacent to the right sides of the surface gate oxide layer (5) and the surface gate contact region (6), the right side of the field oxide layer (7) is adjacent to the left side of the drain contact region (9), and meanwhile, the field oxide layer (7) is located above the first N-type drift region (8); the first layer of N-type drift region (8) is positioned on the upper side of the P-type buried layer (13) and the lower side of the field oxide layer (7), the left side of the first layer of N-type drift region is in contact with the right side of the P-body (16), and the right side of the first layer of N-type drift region is in contact with the left side of the drain N + region (10); the drain contact region (9) is positioned above the drain N + region (10), and the left side of the drain contact region (9) is adjacent to the right side of the field oxide layer (7); the drain N + region (10) is positioned right below the drain contact region (9), the left side of the drain N + region is in contact with the P-type buried layer (13), the right sides of the first layer N-type drift region (8) and the second layer N-type drift region (11), and the lower side of the drain N + region (10) is adjacent to the upper right side of the buried oxide layer (12); the upper side of the second layer of N-type drift region (11) is adjacent to the lower side of the P-type buried layer (13), the lower side of the second layer of N-type drift region is in contact with the upper side of the buried oxide layer (12), the left side of the second layer of N-type drift region (11) is in contact with the right side of the P-body (16), and the right side of the second layer of N-type drift region is adjacent to the left side of the drain electrode N + region (10); the lower side of the buried oxide layer (12) is adjacent to the upper side of the substrate (14), the upper side of the buried oxide layer (12) is adjacent to the lower side of the drain electrode N + region (10) and the lower side of the second layer N-type drift region (11), meanwhile, the upper left side of the buried oxide layer (12) is adjacent to the right sides of the in-vivo gate oxide layer (15) and the in-vivo gate contact region (17), and the upper left side of the buried oxide layer is in contact with the lower side of the in-vivo gate contact region (17); the P-type buried layer (13) is positioned between the first layer of N-type drift region (8) and the second layer of N-type drift region (11), the upper side of the P-type buried layer is in contact with the lower side of the first layer of N-type drift region (8), the lower side of the P-type buried layer is in contact with the upper side of the second layer of N-type drift region (11), the left side of the P-body (16) is adjacent to the right side of the P-body, and the right side of the P-body is adjacent to the left side of the; the upper side of the substrate (14) is in contact with the lower side of the buried oxide layer (12), and the substrate is positioned at the bottom of the device; the lower edge of the internal gate oxide layer (15) is in contact with the upper edge of the internal gate contact region (17), the right side of the internal gate oxide layer is in contact with the buried oxide layer (12), and meanwhile, the upper edge of the internal gate oxide layer (15) is in contact with the lower edges of the source N + region (3) and the P-body (16); the left side of the P-body (16) is in contact with the right sides of the source N + region (3) and the source P + region (2), meanwhile, the upper side of the P-body is closely adjacent to the lower side of the surface gate oxide layer (5), the lower side of the P-body is in contact with the upper right side of the internal gate oxide layer (15), and the right side of the P-body is in contact with the left sides of the P-type buried layer (13), the first N-type drift region (8) and the second N-type drift region (11); the in-body gate contact region (17) is positioned on the upper left side of the buried oxide layer (12) and the lower side of the in-body gate oxide layer (15), and the right side of the in-body gate contact region is in contact with the buried oxide layer (12).

Optionally, the P-type buried layer (13) is doped with P-type impurities with a doping concentration range of 1 × 10¹⁶～1×10¹⁷cm^-3。

Optionally, the length of the P-type covering layer (13) is 3-7.5 μm and can be adjusted, and the width of the P-type covering layer is 0.2-0.7 μm and can be adjusted.

Optionally, the material of the surface gate contact region (6) may be doped polysilicon and metal.

Optionally, the material of the body gate contact region (17) is doped polysilicon and metal.

The invention has the beneficial effects that: the invention provides a transverse super-junction thin-layer SOI-LDMOS device with a surface channel and an internal channel. Firstly, when the device is conducted in the forward direction, the area of a conducting channel of the device is increased by the internal grid electrode, the capability of injecting electrons into the N-type drift region is greatly improved, and the control capability (transconductance g) of grid voltage to current is enhanced_mIncrease), the forward conduction performance of the device is further improved; the P-type buried layer can effectively improve the doping concentration of the first N-type drift region and the second N-type drift region, so that the specific on-resistance of the device is reduced. And secondly, the P-type buried layer, the first N-type drift region and the second N-type drift region are mutually depleted during breakdown (the charges of the P region and the N region are mutually compensated, namely the fixed positive charges of the N region point to the fixed negative charges of the P region). In conclusion, the figure of merit FOM of the device is improved through the action of the internal grid and the P-type buried layer.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 1 of the present invention;

FIG. 2 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 2 of the present invention;

FIG. 3 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 3 of the present invention;

FIG. 4 is a schematic structural diagram of a thin-layer SOI-LDMOS device according to embodiment 4 of the present invention;

FIG. 5 is a comparison graph of transfer characteristic curves and transconductance of the new structure 1SOI-LDMOS device, the new structure 2SOI-LDMOS device, the conventional SOI-LDMOS device and the conventional super junction SOI-LDMOS device under forward conduction provided by the invention;

FIG. 6 is a comparison graph of output characteristic curves of the new structure 1SOI-LDMOS device, the new structure 2SOI-LDMOS device, the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device under forward conduction provided by the invention;

FIG. 7 is a comparison graph of the turn-on voltages of the new structure 1SOI-LDMOS device, the new structure 2SOI-LDMOS device, the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device provided by the present invention;

FIG. 8 shows that the doping concentrations of the first N-type drift region of the SOI-LDMOS device with the new structure 1 provided by the invention are respectively 6.0 × 10¹⁵cm^-3、8.0×10¹⁵cm^-3、1.0×10¹⁶cm^-3、1.2×10¹⁶cm^-3And 1.4X 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe variation curve of (d);

FIG. 9 shows that the doping concentrations of the second N-type drift region of the SOI-LDMOS device with the new structure 1 provided by the invention are 1.6 × 10¹⁶cm^-3、1.8×10¹⁶cm^-3、2.0×10¹⁶cm^-3、2.2×10¹⁶cm^-3And 2.4X 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe variation curve of (d);

FIG. 10 shows that the doping concentrations of the N-type drift region of the 2SOI-LDMOS device with the new structure provided by the invention are respectively 1.2 × 10¹⁵cm^-3、1.4×10¹⁵cm^-3、1.6×10¹⁶cm^-3、1.8×10¹⁶cm^-3And 2.0X 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe variation curve of (d);

FIG. 11 is a current line direction diagram of a new structure 1SOI-LDMOS device, a new structure 2SOI-LDMOS device, a conventional SOI-LDMOS device and a conventional super junction SOI-LDMOS device provided by the present invention in a forward conduction state; (a) is a traditional SOI-LDMOS; (b) the super-junction SOI-LDMOS is a traditional super-junction SOI-LDMOS; (c) is a new structure 1 SOI-LDMOS; (d) 2SOI-LDMOS with a new structure;

FIG. 12 is a distribution diagram of equipotential lines of a new structure 1SOI-LDMOS device, a new structure 2SOI-LDMOS device, a conventional SOI-LDMOS device and a conventional super-junction SOI-LDMOS device provided by the present invention under breakdown; (a) is a traditional SOI-LDMOS; (b) the super-junction SOI-LDMOS is a traditional super-junction SOI-LDMOS; (c) is a new structure 1 SOI-LDMOS; (d) 2SOI-LDMOS with a new structure;

fig. 13 is a comparison graph of two-dimensional electric field intensity at a position where Y is 0.1 μm in a breakdown state of the new structure 1SOI-LDMOS device, the new structure 2SOI-LDMOS device, the conventional SOI-LDMOS device, and the conventional super junction SOI-LDMOS device provided by the present invention;

FIG. 14 is a schematic process flow diagram of a SOI-LDMOS device with a new structure according to the present invention; (a) etching, deposition and oxidation; (b) vapor phase epitaxy; (c) for oxidation, SiO is deposited₂A protective layer; (d) to deposit metal contacts;

reference numerals: the structure comprises a source electrode contact region 1, a source electrode P + region 2, a source electrode N + region 3, a grid source isolation oxide layer 4, a surface grid oxide layer 5, a surface grid contact region 6, a field oxide layer 7, a first N-type drift region 8, a drain electrode contact region 9, a drain electrode N + region 10, a second N-type drift region 11, a buried oxide layer 12, a P-type buried layer 13, a substrate 14, an in-body grid oxide layer 15, a P-body16 and an in-body grid contact region 17.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Example 1:

as shown in FIG. 1, the invention relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel, which comprises a source contact region 1, a source P + region 2, a source N + region 3, a gate source isolation oxide layer 4, a surface gate oxide layer 5, a surface gate contact region 6, a field oxide layer 7, a first N-type drift region 8, a drain contact region 9, a drain N + region 10, a second N-type drift region 11, a buried oxide layer 12, a P-type buried layer 13, a substrate 14, an internal gate oxide layer 15, a P-body16 and an internal gate contact region 17.

The source electrode contact region 1 is positioned above the source electrode N + region 3 and the source electrode P + region 2, and the right side of the source electrode contact region 1 is adjacent to the left side of the grid source isolation oxide layer 4; the thickness was 0.2 μm and the length was 0.9. mu.m.

The upper left side of the source electrode P + region 2 is contacted with the lower side of the source electrode contact region 1, the source electrode P + region 2 is also positioned in the source electrode N + region 3 and is L-shaped, and meanwhile, the rightmost side of the source electrode P + region 2 is contacted with a part of the left side of the P-body 16; the upper left side is 0.3 μm, the upper right side is 0.4 μm, the lower side is 0.7 μm, the left side is 0.6 μm, the right lower side is 0.3 μm, the upper right side is 0.4 μm, and the concentration of doped P-type impurities is 1.0 × 10²⁰cm^-3。

The upper side of the source N + region 3 is in contact with the source contact region 1 and the lower side of the gate source isolation oxide layer 4, the lower side of the source N + region is adjacent to the upper side of the in-vivo gate oxide layer 15, the right side of the in-vivo gate oxide layer is in contact with the left side of the P-body16, and meanwhile, an L-shaped source P + region 2 exists in the source N + region 3; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with N-type impurities at a concentration of 1.0X 10²⁰cm^-3。

The left side of the gate source isolation oxide layer 4 is adjacent to the right side of the source electrode contact region 1, the right side of the gate source isolation oxide layer 4 is adjacent to the left sides of the surface gate oxide layer 5 and the surface gate electrode contact region 6, and the lower side of the gate source isolation oxide layer is in contact with the source electrode N + region 3; the thickness was 0.2 μm and the length was 0.1. mu.m.

The upper edge of the surface gate oxide layer 5 is adjacent to the lower edge of the surface gate contact region 6, the left side of the surface gate oxide layer 5 is in contact with the right lower side of the gate source isolation oxide layer 4, the right side of the surface gate oxide layer 5 is in contact with the left lower side of the field oxide layer 7, and meanwhile, the lower edge of the surface gate oxide layer 5 is adjacent to the upper edge of the P-body 16; the thickness was 0.1 μm and the length was 1.0. mu.m.

The lower side of the surface gate contact region 6 is in contact with the upper side of the surface gate oxide layer 5, the left side of the surface gate contact region is in contact with the right upper side of the gate source isolation oxide layer 4, and the right side of the surface gate contact region is in contact with the left upper side of the field oxide layer 7; polysilicon with thickness of 0.1 μm and length of 1.0 μm is doped with N-type impurity at concentration of 5.0 × 10¹⁸cm^-3。

The left side of the field oxide layer 7 is adjacent to the right sides of the surface gate oxide layer 5 and the surface gate contact region 6, the right side of the field oxide layer 7 is adjacent to the left side of the drain contact region 9, and meanwhile, the field oxide layer 7 is positioned above the first N-type drift region 8; the thickness was 0.2 μm and the length was 7.0. mu.m.

The first layer of N-type drift region 8 is positioned on the upper side of the P-type buried layer 13 and the lower side of the field oxide layer 7, the left side of the first layer of N-type drift region is in contact with the right side of the P-body16, and the right side of the first layer of N-type drift region is in contact with the left side of the drain N + region 10; it has a thickness of 0.2 μm, a length of 7.0 μm, and a concentration of doped N-type impurities of 1.0 × 10¹⁶cm^-3。

The drain contact region 9 is positioned right above the drain N + region 10, and the left side of the drain contact region 9 is adjacent to the right side of the field oxide layer 7; the thickness was 0.2 μm and the length was 1.0. mu.m.

The drain N + region 10 is positioned right below the drain contact region 9, the left side of the drain N + region is contacted with the P-type buried layer 13, the right sides of the first layer N-type drift region 8 and the second layer N-type drift region 11, and the lower side of the drain N + region 10 is adjacent to the upper right side of the buried oxide layer 12; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with N-type impurities at a concentration of 1X 10²⁰cm^-3。

The second layer of N-type drift region 1The upper side of the first layer 1 is adjacent to the lower side of the P-type buried layer 13, the lower side of the first layer 1 is in contact with the upper side of the buried oxide layer 12, and the left side and the right side of the second layer N-type drift region 17 are respectively adjacent to the right side of the P-body16 and the left side of the drain N + region 10; it has a thickness of 0.4 μm and a length of 7.0 μm, and is doped with N-type impurities at a concentration of 2.0X 10¹⁶cm^-3。

The lower side of the buried oxide layer 12 is close to the upper side of the substrate 14, the upper side of the buried oxide layer 12 is adjacent to the lower side of the drain electrode N + region 10 and the lower side of the second layer N-type drift region 11, meanwhile, the upper left side of the buried oxide layer 12 is close to the right sides of the in-vivo gate oxide layer 15 and the in-vivo gate contact region 17, and the upper left side of the buried oxide layer is in contact with the lower side of the in-vivo gate contact region 17; the thickness was 2.0 μm and the length was 10.0. mu.m.

The P-type buried layer 13 is positioned between the first N-type drift region 8 and the second N-type drift region 11, the upper side of the P-type buried layer is in contact with the lower side of the first N-type drift region 8, the lower side of the P-type buried layer is in contact with the upper side of the second N-type drift region 11, the left side of the P-body16 is adjacent to the right side of the P-body, and the right side of the P-body 10 is adjacent to the left side of the drain N; it has a thickness of 0.4 μm and a length of 7.0 μm, and is doped with P-type impurities at a concentration of 1.0X 10¹⁶cm^-3。

The upper edge of the substrate 14 is in contact with the lower edge of the buried oxide layer 12, and the upper edge of the substrate is positioned at the bottom of the device; it has a thickness of 2 μm, a length of 10.0 μm, and a concentration of doped P-type impurity of 1 × 10¹⁴cm^-3。

The lower side of the internal gate oxide layer 15 is in contact with the upper side of the internal gate contact region 17, the right side of the internal gate oxide layer is in contact with the buried oxide layer 12, and meanwhile, the upper side of the internal gate oxide layer 15 is in contact with the lower sides of the source N + region 3 and the P-body 16; the thickness was 0.1 μm and the length was 2.0. mu.m.

The left side of the P-body16 is in contact with the right sides of the source N + region 3 and the source P + region 2, meanwhile, the upper side of the P-body16 is adjacent to the lower side of the surface gate oxide layer 5, the lower side of the P-body is in contact with the upper side of the internal gate oxide layer 15, and the right side of the P-body16 is in contact with the left sides of the P-type buried layer 13, the first N-type drift region 8 and the second N-type drift region 11; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with P-type impurities at a concentration of 1.0 × 10¹⁷cm^-3。

The in-body gate contact region 17 is positioned on the upper left side of the buried oxide layer 12 and the lower side of the in-body gate oxide layer 15, the right side thereof andthe buried oxide layer 12 is contacted; polysilicon with thickness of 0.2 μm and length of 2.0 μm is doped with N-type impurity at concentration of 5.0 × 10¹⁸cm^-3。

Example 2:

as shown in FIG. 2, the invention relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel, which comprises a source contact region 1, a source P + region 2, a source N + region 3, a gate source isolation oxide layer 4, a surface gate oxide layer 5, a surface gate contact region 6, a field oxide layer 7, a P-type covering layer 8, a drain contact region 9, a drain N + region 10, an N-type drift region 11, a buried oxide layer 12, a substrate 13, a gate internal oxide layer 14, a P-body15 and an internal gate contact region 16.

The source electrode contact region 1 is positioned above the source electrode N + region 3 and the source electrode P + region 2, and the right side of the source electrode contact region 1 is adjacent to the left side of the grid source isolation oxide layer 4; the thickness was 0.2 μm and the length was 0.9. mu.m.

The upper left side of the source electrode P + region 2 is contacted with the lower side of the source electrode contact region 1, the source electrode P + region 2 is also positioned in the source electrode N + region 3 and is L-shaped, and meanwhile, the rightmost side of the source electrode P + region 2 is contacted with a part of the left side of the P-body 15; the upper left side is 0.3 μm, the upper right side is 0.4 μm, the lower side is 0.7 μm, the left side is 0.6 μm, the right lower side is 0.3 μm, the upper right side is 0.4 μm, and the concentration of doped P-type impurities is 1.0 × 10²⁰cm^-3。

The upper side of the source N + region 3 is in contact with the source contact region 1 and the lower side of the gate source isolation oxide layer 4, the lower side of the source N + region is adjacent to the upper side of the in-vivo gate oxide layer 14, the right side of the source N + region is in contact with the left side of the P-body15, and meanwhile, an L-shaped source P + region 2 is also arranged in the source N + region 3; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with N-type impurities at a concentration of 1.0X 10²⁰cm^-3。

The left side of the gate source isolation oxide layer 4 is adjacent to the right side of the source electrode contact region 1, the right side of the gate source isolation oxide layer 4 is adjacent to the left sides of the surface gate oxide layer 5 and the surface gate electrode contact region 6, and the lower side of the gate source isolation oxide layer is in contact with the source electrode N + region 3; the thickness was 0.2 μm and the length was 0.1. mu.m.

The upper edge of the surface gate oxide layer 5 is adjacent to the lower edge of the surface gate contact region 6, the left side of the surface gate oxide layer 5 is in contact with the right lower side of the gate source isolation oxide layer 4, the right side of the surface gate oxide layer 5 is in contact with the left lower side of the field oxide layer 7, and meanwhile, the lower edge of the surface gate oxide layer 5 is adjacent to the upper edge of the P-body 15; the thickness was 0.1 μm and the length was 1.0. mu.m.

The lower side of the surface gate contact region 6 is in contact with the upper side of the surface gate oxide layer 5, the left side of the surface gate contact region is in contact with the right upper side of the gate source isolation oxide layer 4, and the right side of the surface gate contact region is in contact with the left upper side of the field oxide layer 7; polysilicon with thickness of 0.1 μm and length of 1.0 μm is doped with N-type impurity at concentration of 5.0 × 10¹⁸cm^-3。

The left side of the field oxide layer 7 is adjacent to the right sides of the surface gate oxide layer 5 and the gate contact region 6, the right side of the field oxide layer 7 is adjacent to the left side of the drain contact region 9, and meanwhile, the field oxide layer 7 is positioned above the P-type covering layer 8 and on the left of the N-type drift region 11; the thickness was 0.2 μm and the length was 7.0. mu.m.

The P-type covering layer 8 is positioned below the field oxide layer 7, meanwhile, the lower side and the left side of the P-type covering layer 8 are in contact with the N-type drift region 11, and the right side of the P-type covering layer is adjacent to the upper left side of the drain electrode N + region 10; it has a thickness of 0.4 μm and a length of 6.5 μm, and is doped with P-type impurities at a concentration of 1.2 × 10¹⁶cm^-3。

The drain contact region 9 is positioned right above the drain N + region 10, and the left side of the drain contact region 9 is adjacent to the right side of the field oxide layer 7; the thickness was 0.2 μm and the length was 1.0. mu.m.

The drain N + region 10 is positioned right below the drain contact region 9, the left side of the drain N + region is contacted with the P-type covering layer 8 and the right side of the N-type drift region 11, and the lower side of the drain N + region 10 is adjacent to the upper right side of the buried oxide layer 12; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with N-type impurities at a concentration of 1X 10²⁰cm^-3。

The lower side of the N-type drift region 11 is contacted with the upper side of the buried oxide layer 12, the upper left side of the N-type drift region is contacted with the lower left side of the field oxide layer 7, meanwhile, the left side of the N-type drift region 11 is adjacent to the right side of the P-body15, the right side of the N-type drift region is contacted with the left lower side of the drain electrode N + region, the upper right side of the N-type drift region 11 is covered by the P-type covering layer 8, and the upper right side of the; it has a thickness of 1.0 μm and a length of 7.0 μm, and is doped with N-type impurities at a concentration of 1.7X 10¹⁶cm^-3。

The lower side of the buried oxide layer 12 is close to the upper side of the substrate 13, the upper side of the buried oxide layer 12 is adjacent to the lower side of the drain electrode N + region 10 and the lower side of the N-type drift region 11, meanwhile, the upper left side of the buried oxide layer 12 is adjacent to the lower side of the in-vivo gate contact region 16, and the upper left side of the buried oxide layer is in contact with the in-vivo gate oxide layer 14 and the right side of the in-vivo gate contact region 16; the thickness was 2.0 μm and the length was 10.0. mu.m.

The upper side of the substrate 13 is in contact with the lower side of the buried oxide layer 12, and the upper side of the substrate is positioned at the bottom of the device; it has a thickness of 2.0 μm, a length of 10.0 μm, and a concentration of doped P-type impurity of 1 × 10¹⁴cm^-3。

The lower side of the internal gate oxide layer 14 is in contact with the upper side of the internal gate contact region 16, the right side of the internal gate oxide layer is in contact with the buried oxide layer 12, and meanwhile, the upper side of the internal gate oxide layer 14 is in contact with the lower sides of the source N + region 3 and the P-body 15; the thickness was 0.1 μm and the length was 2.0. mu.m.

The left side of the P-body15 is in contact with the rightmost sides of the source N + region 3 and the source P + region 2, meanwhile, the upper side of the P-body15 is adjacent to the lower side of the surface gate oxide layer 5, the lower side of the P-body is in contact with the upper side of the internal gate oxide layer 14, and the right side of the P-body15 is in contact with the left side of the N-type drift region 11; it has a thickness of 1.0 μm and a length of 1.0 μm, and is doped with P-type impurities at a concentration of 1.0 × 10¹⁷cm^-3。

The in-body gate contact region 16 is positioned on the upper left side of the buried oxide layer 12 and the lower side of the in-body gate oxide layer 14, and the right side of the in-body gate contact region is in contact with the buried oxide layer 12; polysilicon with thickness of 0.2 μm and length of 2.0 μm is doped with N-type impurity at concentration of 5.0 × 10¹⁸cm^-3。

Example 3:

as shown in FIG. 3, the invention relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel, which comprises a source contact region 1, a source P + region 2, a source N + region 3, a gate source isolation oxide layer 4, a surface gate oxide layer 5, a surface gate contact region 6, a field oxide layer 7, a first N-type drift region 8, a drain contact region 9, a drain N + region 10, a second N-type drift region 11, a buried oxide layer 12, a silicon dioxide dielectric layer 13, a substrate 14, an internal gate oxide layer 15, a P-body16 and an internal gate contact region 17.

On the basis of the structure of embodiment 1, the P-type buried layer 13 in the drift region is replaced by a silicon dioxide dielectric layer 13, the upper side of the silicon dioxide dielectric layer 13 is in contact with the lower side of the first layer of N-type drift region 8, the lower side of the silicon dioxide dielectric layer is in contact with the upper side of the second layer of N-type drift region 11, the left side of the silicon dioxide dielectric layer is adjacent to the right side of the P-body16, and the right side of the silicon dioxide dielectric layer is adjacent to the left; the thickness was 0.4 μm and the length was 7.0. mu.m. The positions, thicknesses, lengths and doping concentrations of the first layer of N-type drift region 8 and the second layer of N-type drift region 11 are not changed.

Example 4:

as shown in FIG. 4, the invention relates to a transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel, which comprises a source contact region 1, a source P + region 2, a source N + region 3, a gate source isolation oxide layer 4, a surface gate oxide layer 5, a surface gate contact region 6, a field oxide layer 7, a first N-type drift region 8, a drain contact region 9, a drain N + region 10, a second N-type drift region 11, a buried oxide layer 12, a P-type buried layer 13, a substrate 14, an internal gate oxide layer 15, a P-body16, an internal gate contact region 17 and a silicon dioxide medium region 18.

On the basis of the structure of the embodiment 1, the length of the P-type buried layer 13 is changed, the left side of the P-type buried layer 13 is adjacent to the right side of the P-body16, the right side of the P-type buried layer is adjacent to the left side of the silicon dioxide dielectric region 18, the upper side of the P-type buried layer is in contact with the lower left side of the first layer of the N-type drift region 8, and the lower side of the P-type buried layer is in contact with the upper left side of the; the length is 4.0 μm, the thickness is 0.4 μm, and the concentration of doped P-type impurity is 1.7 × 10¹⁶cm^-3. The left side of the silicon dioxide dielectric region 18 is in contact with the right side of the P-type buried layer 13, the right side of the silicon dioxide dielectric region is in contact with the left side of the drain N + region 10, the upper side of the silicon dioxide dielectric region is in contact with the lower right side of the first layer of N-type drift region 8, and the upper right side of the lower second layer of N-type drift region 11 is in contact; the length was 3.0 μm and the thickness was 0.4. mu.m.

FIG. 5 is a graph of the voltage (V) at room temperature equal to 300k and the drain voltage_d) When the voltage is equal to 1V, the transfer characteristic curve and transconductance contrast diagram of the new structure 1SOI-LDMOS (the structure of which is shown in figure 1) device, the new structure 2SOI-LDMOS (the structure of which is shown in figure 2) device, the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device under forward conduction are shown. Respectively carrying out the electrical characteristics of the four devices by using sentaurus simulation softwareAnd (4) simulating, and drawing a contrast graph by using the obtained simulation data through an Origin tool. As shown in FIG. 5, the maximum transconductance value (g) of the new structure 1SOI-LDMOS_mMAX) 5.7mS/mm, and the maximum transconductance value (g) of the conventional SOI-LDMOS and the conventional super junction SOI-LDMOS_mMAX) 1.5mS/mm and 3.1mS/mm respectively, the maximum transconductance value (g) of the new structure 1SOI-LDMOS, the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS_mMAX) Compared with the traditional SOI-LDMOS transconductance maximum value (g), the transconductance of the traditional SOI-LDMOS is increased by 3.4mS/mm and 1.7mS/mm respectively_mMAX) 3.40 times of that of the traditional super-junction SOI-LDMOS transconductance maximum value (g)_mMAX) 1.64 times. In addition, the transfer characteristic curves of the SOI-LDMOS with the new structure 1 are higher than those of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS. Therefore, the grid voltage-to-current control capability of the SOI-LDMOS with the new structure is greatly improved compared with that of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS. Transconductance maximum value (g) of novel structure 2SOI-LDMOS_mMAX) The transconductance maximum value of the new structure 2SOI-LDMOS is 6.06 times that of the traditional SOI-LDMOS and 2.93 times that of the traditional super-junction SOI-LDMOS at the same time. In addition, the transfer characteristic curves of the new structure 2SOI-LDMOS are higher than those of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS. Therefore, the control of the grid voltage to the current of the novel structure 2SOI-LDMOS can be enhanced. In summary, because the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS add an internal gate in the buried oxide layer, compared with the conventional SOI-LDMOS and conventional super junction SOI-LDMOS, the area of the conductive channel of electrons is increased, thereby improving the capability of controlling the current by the gate voltage.

FIG. 6 shows a new structure 1SOI-LDMOS device (the structure of which is shown in FIG. 1), a new structure 2SOI-LDMOS device (the structure of which is shown in FIG. 2), and a conventional SOI-LDMOS device, a conventional super-junction SOI-LDMOS device at a gate voltage V_gThe output characteristic curve is 10V. According to the graph shown in FIG. 6, after the device is turned on, the drain saturation currents of the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS are both larger than the drain saturation currents of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS, because the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS are additionally provided with an internal body in a buried oxide layerThe grid electrode increases the conducting channel area of the device, and the specific on-resistance is smaller, so that the drain electrode saturation current of the device is larger. Therefore, the forward conductivity of the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS is better than that of the traditional SOI-LDMOS and the traditional super-junction SOI-LDMOS.

FIG. 7 shows the drain voltage V of the new structure 1SOI-LDMOS device (the structure is shown in FIG. 1), the new structure 2SOI-LDMOS device (the structure is shown in FIG. 2), the conventional SOI-LDMOS device and the conventional super junction SOI-LDMOS device_dGraph comparing the turn-on voltage at 5V. As shown in FIG. 7, the gate oxide thickness and the drain current I are the same_dIs 100A/cm²Meanwhile, the turn-on voltages of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device are respectively 6.25V and 5.80V. However, the starting voltage of the SOI-LDMOS device with the new structure 1 is 4.7V, and is respectively reduced by 25% and 19% compared with the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device; the starting voltage of the new structure 2SOI-LDMOS device is 4.5V, which is respectively reduced by 28% and 22% compared with the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device, because the conducting channel areas of the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device are larger, the drain current densities of the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device are larger under the same external bias voltage, and the on-resistance of the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device is smaller. Therefore, the forward conduction performance of the SOI-LDMOS device with the new structure 1 and the SOI-LDMOS device with the new structure 2 are superior to that of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device.

Table 1 below records the maximum transconductance values (g) of the four devices, respectively_mMAX) Specific on-resistance R_on,spBaliga figure of merit FOM and breakdown voltage BV. The maximum transconductance values (g) for the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device are shown in the following table_mMAX) Are both larger than the maximum transconductance value (g) of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device_mMAX) The SOI-LDMOS device with the new structure is characterized in that on the basis of the traditional device, an internal gate is added on a buried oxide layer, so that the area of a conductive channel is increased, and the control capability of the voltage of a grid electrode of the device on the current is enhanced. Specific on-resistance R of 1SOI-LDMOS device with new structure and 2SOI-LDMOS device with new structure_on,spAre all less thanSpecific on-resistance R of traditional SOI-LDMOS device and traditional super-junction SOI-LDMOS device_on,spThe effective conducting channel area of the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device is larger than that of the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device, meanwhile, a P-type covering layer exists in a drift region of the new structure 1SOI-LDMOS device and a P-type buried layer exists in a drift region of the new structure 2SOI-LDMOS device, so that the doping concentration of an N-type drift region is improved, the specific on-resistance R of the device is reduced_on,sp. The breakdown voltage of the SOI-LDMOS device with the new structure 1 and the SOI-LDMOS device with the new structure 2 is slightly reduced relative to the breakdown voltage of the traditional SOI-LDMOS device and the traditional super-junction SOI-LDMOS device. The Baliga optimal value FOM of the new structure 1SOI-LDMOS device and the new structure 2SOI-LDMOS device are both larger than the Baliga optimal value FOM of the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device.

TABLE 1 comparison of four device Properties

FIG. 8 shows the doping concentrations of the N-type drift region in the first layer of the new structure 1SOI-LDMOS (the structure is shown in FIG. 1) device are respectively 6.0 × 10¹⁵cm^-3、8.0×10¹⁵cm^-3、1.0×10¹⁶cm^-3、1.2×10¹⁶cm^-3And 1.4X 10¹⁶cm^-3And the concentration of the N-type drift region of the second layer is 2.0 × 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe change curve of (2). Referring to FIG. 8, when the doping concentration of the N-type drift region of the first layer is 8.0 × 10¹⁵cm^-3The breakdown voltage BV is 109V; when the doping concentration is more than 1.0 multiplied by 10¹⁶cm^-3At this time, the breakdown voltage BV sharply decreases. Specific on-resistance R_on,spThere is a downward trend as the doping concentration increases.

FIG. 9 shows the new structure 1SOI-LDMOS (the structure is shown in FIG. 1) device with doping concentration of 1.6 × 10 in the second N-type drift region¹⁶cm^-3、1.8×10¹⁶cm^-3、2.0×10¹⁶cm^-3、2.2×10¹⁶cm^-3And 2.4X 10¹⁶cm^-3And the concentration of the N-type drift region of the first layer is 1.0 × 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe change curve of (2). As shown in FIG. 9, when the concentration of the N-type drift region in the second layer is 1.8 × 10¹⁶cm^-3The breakdown voltage BV reaches a maximum of 109V. When the doping concentration is more than 2.0 multiplied by 10¹⁶cm^-3The breakdown voltage BV sharply decreases. Specific on-resistance R with increasing doping concentration_on,spGradually decreases.

FIG. 10 shows the doping concentrations of the N-type drift region of the new 2SOI-LDMOS (the structure is shown in FIG. 2) device with 1.2 × 10¹⁵cm^-3、1.4×10¹⁵cm^-3、1.6×10¹⁶cm^-3、1.8×10¹⁶cm^-3And 2.0X 10¹⁶cm^-3Breakdown voltage BV and specific on-resistance R_on,spThe change curve of (2). As shown in FIG. 10, when the doping concentration of the N-type drift region is 1.6 × 10¹⁶cm^-3When the breakdown voltage BV reaches a maximum of 102V, the specific on-resistance R_on,spIs 4.7 m.OMEGA.. cm². Specific on-resistance R_on,spThe doping concentration of the N-type drift region is increased and is in a descending trend, the larger the doping concentration of the N-type drift region is, the higher the specific on-resistance R is_on,spThe smaller. When the doping concentration of the N-type drift region is more than 1.6 multiplied by 10¹⁶cm^-3The breakdown voltage BV is drastically reduced.

FIG. 11 shows current line patterns of a new structure 1SOI-LDMOS device (the structure of which is shown in FIG. 1), a new structure 2SOI-LDMOS device (the structure of which is shown in FIG. 2), a conventional SOI-LDMOS device and a conventional super-junction SOI-LDMOS device in a forward conduction state. As can be seen from FIG. 11, the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS devices have two conductive channels, respectively on the surface and in the bulk; and the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device only have one conducting channel, and the conducting channels of the traditional SOI-LDMOS device and the traditional super junction SOI-LDMOS device are positioned on the surface.

FIG. 12 is an equipotential line distribution diagram of a new structure 1SOI-LDMOS device (the structure of which is shown in FIG. 1), a new structure 2SOI-LDMOS device (the structure of which is shown in FIG. 2), a conventional SOI-LDMOS device and a conventional super-junction SOI-LDMOS device. According to fig. 12, it can be seen that the breakdown voltage of the new structure 1SOI-LDMOS and the new structure 2SOI-LDMOS is reduced compared with that of the conventional SOI-LDMOS device and that of the conventional super-junction SOI-LDMOS device, and the equipotential line distribution of the conventional SOI-LDMOS device and that of the conventional super-junction SOI-LDMOS device are more uniform than those of the new structure 1SOI-LDMOS and the new structure 2 SOI-LDMOS.

Fig. 13 is a comparison graph of Y ═ 0.1 μm electric field of the new structure 1SOI-LDMOS (the structure of which is shown in fig. 1) device, the new structure 2SOI-LDMOS (the structure of which is shown in fig. 2) device, the conventional SOI-LDMOS device and the conventional super junction SOI-LDMOS device in the avalanche breakdown state. As can be seen from FIG. 13, the area enclosed by the electric field intensity curve and the X axis of the conventional SOI-LDMOS device and the conventional super-junction SOI-LDMOS device is larger than that of the SOI-LDMOS device with the new structure 1 and that of the SOI-LDMOS device with the new structure 2.

The invention provides a transverse super-junction thin-layer SOI-LDMOS device with a surface and an internal double channel, which takes a schematic diagram 1 as an example, and the main process flow of the device is shown in FIG. 14. The specific implementation method comprises the following steps: firstly, selecting an SOI substrate, etching and filling the SOI substrate, and then oxidizing by dry oxygen to form a body inner grid. And then, carrying out vapor phase epitaxy to grow a first layer of N-type drift region, a P-type buried layer and a second layer of N-type drift region, and then carrying out ion implantation and diffusion processes to respectively form a source N + region, a P-body, a source P + region and a source N + region. Then, a compact surface gate oxide layer is grown in a dry oxygen oxidation mode, a layer of heavily doped polysilicon is deposited on the surface gate oxide layer to form a surface gate, and a layer of SiO is deposited on the surface of the drift region₂The protective layer forms a field oxide layer. Finally, metal is deposited on the source electrode and the drain electrode to form good ohmic contact.

In the implementation process, according to the design requirements of specific devices, the substrate material of the transverse super-junction thin-layer SOI-LDMOS device with the surface and the internal double channels provided by the invention can be silicon carbide SiC material, and can also be silicon, gallium arsenide, indium phosphide, silicon germanium or other semiconductor materials instead of bulk silicon carbide during specific manufacturing.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.