阅读说明：本技术 极紫外光遮罩 (Extreme ultraviolet light shade ) 是由 林雲躍 于 2020-08-12 设计创作，主要内容包括：一种极紫外光遮罩,包括基板、在基板上的反射多层结构、在反射多层结构上的接着层、在接着层上的封盖层及在封盖层上的图案化吸收层。封盖层包括非晶形导电材料。(An extreme ultraviolet light mask includes a substrate, a reflective multilayer structure on the substrate, an adhesion layer on the reflective multilayer structure, a capping layer on the adhesion layer, and a patterned absorption layer on the capping layer. The capping layer includes an amorphous conductive material.)

1. An extreme ultraviolet light mask, comprising

A substrate;

a reflective multilayer structure on the substrate;

a bonding layer on the reflective multilayer structure;

a capping layer on the adhesion layer, the capping layer comprising an amorphous conductive material; and

a patterned absorber layer on the capping layer.

Technical Field

The present disclosure relates to extreme ultraviolet light masks. More particularly, the present disclosure relates to extreme ultraviolet light masks for extreme ultraviolet lithography.

Background

The semiconductor industry has experienced exponential growth. Technological advances in materials and design have resulted in several generations of Integrated Circuits (ICs), each of which has smaller and more complex circuits than the previous generation. In the course of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component or wire that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

Disclosure of Invention

An extreme ultraviolet light mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorption layer over the capping layer. The capping layer includes an amorphous conductive material.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard methods in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross-sectional view of an extreme ultraviolet light shield according to some embodiments;

FIG. 2 is a flow diagram of a method for fabricating an extreme ultraviolet light mask, according to some embodiments;

fig. 3A-3H are cross-sectional views of an euv light shield at various stages of a fabrication process, according to some embodiments.

[ notation ] to show

100 extreme ultraviolet light shade

100A pattern area

100B peripheral region

102 substrate

104 conductive layer

110 reflective multilayer structure

112 bonding layer

114 capping layer

116 absorbent layer

116P patterned absorber layer

118 anti-reflection layer

118P patterned anti-reflection layer

120 extreme ultraviolet light shade blank

122 opening (c)

124: groove

130 hard mask layer

130P patterning hard mask layer

140 photoresist layer

140P patterned photoresist layer

142 opening of the container

144 opening of

150 photoresist layer

150P patterned photoresist layer

152 opening (C)

200 method

202 step

204 step of

206 step

208 step (c)

Step 210

212 step of

214 step

216 step (c)

Detailed Description

To achieve the various features of the subject matter referred to, the following disclosure provides many different embodiments, or examples. Specific examples of components, configurations, and the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as shown. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the fabrication of Integrated Circuits (ICs), a pattern represents the fabrication of different layers of an integrated circuit using a series of reusable reticles (also referred to herein as photolithographic masks or masks) to transfer the design of each layer of the integrated circuit onto a semiconductor substrate during a semiconductor device fabrication process. As a result, any defects in the mask may be transferred to the integrated circuit, potentially severely impacting device performance. Defects of sufficient severity can render the mask completely useless, which increases cost and production time.

As the size of integrated circuits shrinks, Extreme Ultraviolet (EUV) light having a wavelength of 13.5nm is used in processes such as photolithography to enable very small patterns (e.g., nanoscale patterns) to be transferred from a mask to a semiconductor wafer. Because most materials are highly absorbing at a wavelength of 13.5nm, euv lithography uses a reflective mask that selectively reflects and absorbs euv light. The pattern formed on the extreme ultraviolet light mask is transferred to the semiconductor wafer by reflecting the extreme ultraviolet light from the reflection surface of the extreme ultraviolet light mask portion. It is important that the euv mask be as defect-free as possible, since for small feature sizes in advanced technology nodes, lithographic patterning is more sensitive to mask defects.

In some embodiments, a reflective extreme ultraviolet light mask includes a mask substrate, a reflective multilayer structure including molybdenum (Mo) layers and silicon (Si) layers alternately stacked on the mask substrate, and a patterned absorption layer on the reflective multilayer structure. A ruthenium (Ru) capping layer is disposed over the reflective multilayer structure to prevent oxidation of a top silicon layer in the reflective multilayer structure. However, during the deposition of ruthenium onto the reflective multilayer structure, the ruthenium metal tends to crystallize on the surface of the top silicon layer and/or mix with the silicon at the interface of the ruthenium capping layer and the top silicon layer, resulting in a discontinuous coverage of the ruthenium capping layer on the top silicon layer. When extreme ultraviolet light masks are used in integrated circuit fabrication, the non-continuous ruthenium capping layer results in a reduction in Critical Dimension (CD) uniformity, which in turn reduces the performance of the integrated circuit. In addition, carbon remaining from the metalorganic precursor in the euv light exposure tool may diffuse into the ruthenium capping layer and accumulate in surface portions of the ruthenium capping layer. Over time, carbon contamination causes a significant decrease in the reflectivity of the euv light shield, which adversely affects the effectiveness of the euv light shield.

In an embodiment of the present disclosure, an extreme ultraviolet light shield having improved quality and stability is provided. The extreme ultraviolet light mask includes a substrate, a reflective Multilayer (ML) structure over the substrate, an adhesion layer over the reflective multilayer structure, a ruthenium-based capping layer over the adhesion layer, a patterned absorber layer over the capping layer, and a patterned anti-reflective layer over the patterned absorber layer. The introduction of an adhesion layer between the reflective multilayer structure and the ruthenium-based capping layer helps to prevent ruthenium crystallization when ruthenium is deposited onto the reflective multilayer structure. Thus, a capping layer with continuous coverage across the reflective multilayer structure can be obtained. The adhesion layer also helps prevent ruthenium-silicon intermixing during use of the extreme ultraviolet light mask, thereby helping to improve stability of the extreme ultraviolet light mask. In some embodiments, the ruthenium-based capping layer is further doped with a dopant having a lower carbon solubility (carbon solubility) than ruthenium. Therefore, during the use of the extreme ultraviolet light shield, the accumulation of carbon in the surface portion of the ruthenium-based capping layer is reduced, which results in further increased stability of the extreme ultraviolet light shield.

Fig. 1 is a cross-sectional view of an extreme ultraviolet light mask 100 according to some embodiments of the present disclosure. Referring to fig. 1, the euv light mask 100 includes a substrate 102, a reflective multilayer structure 110 over a front surface of the substrate 102, an adhesion layer 112 over the reflective multilayer structure 110, a capping layer 114 over the adhesion layer 112, a patterned absorption layer 116P over the capping layer 114, and a patterned antireflective layer 118P over the patterned absorption layer 116P. The euv light shield 100 further includes a conductive layer 104 on a back surface of the substrate 102 opposite the front surface.

The patterned absorber layer 116P and the patterned anti-reflective layer 118P contain a pattern of openings 122 that corresponds to a circuit pattern to be formed on a semiconductor wafer. The pattern of the opening 122 is located in the pattern region 100A of the euv light mask 100, exposing the surface of the capping layer 114. The pattern area 100A is surrounded by a peripheral area 100B of the extreme ultraviolet light mask 100. The peripheral region 100B corresponds to an unpatterned region of the euv light shield 100 that is not used in an exposure process during integrated circuit fabrication. In some embodiments, the pattern area 100A of the euv light mask 100 is located in a central region of the substrate 102, and the peripheral area 100B is located in an edge region of the substrate 102. The pattern area 100A is separated from the peripheral area 100B by a trench 124. The trench 124 extends through the patterned anti-reflective layer 118P, the patterned absorbing layer 116P, the capping layer 114, the adhesion layer 112, and the reflective multilayer structure 110, exposing the front surface of the substrate 102.

In the present disclosure, by introducing the adhesion layer 112 between the capping layer 114 and the reflective multilayer structure 110, uniformity of the capping layer 114 is enhanced and carbon accumulation during use of the euv light mask 100 is reduced, enhancing quality and stability of the euv light mask 100.

Fig. 2 is a flow diagram of a method 200 for fabricating an extreme ultraviolet light mask (e.g., extreme ultraviolet light mask 100), according to some embodiments. Fig. 3A-3H are cross-sectional views of an euv light shield 100 at various stages of a fabrication process, according to some embodiments. The method 200 refers to the extreme ultraviolet light mask 100 and is discussed in detail below. In some embodiments, additional steps are performed before, during, and/or after the method 200, or some of the described steps are replaced and/or eliminated. In some embodiments, some of the features described below are replaced or removed. Those skilled in the art will appreciate that although some embodiments have been discussed with steps performed in a particular order, such steps may be performed in another logical order.

Referring to fig. 2 and 3A, the method 200 includes step 202, in which a hard mask layer 130 and a photoresist layer 140 are sequentially formed on an extreme ultraviolet light mask blank (blank)120, according to some embodiments. In some embodiments, the euv light shield blank 120 includes, from bottom to top, a substrate 102, a reflective multilayer structure 110, an adhesion layer 112, a capping layer 114, an absorption layer 116, and an anti-reflection layer 118.

The substrate 102 comprises a material having a low coefficient of thermal expansion. The low thermal expansion material helps minimize image distortion due to mask heating during use of the extreme ultraviolet light mask 100. In some embodiments, the substrate 102 comprises fused silica, fused quartz, calcium fluoride, silicon carbide,Black diamond, titanium oxide doped silicon oxide (SiO)₂/TiO₂) Or other suitable low thermal expansion material. In some embodiments, the substrate 102 has a thickness in the range of about 1mm to about 7 mm. In some cases, if the thickness of the substrate 102 is too small, the risk of cracking or bending of the euv light shield 100 increases. On the other hand, in some cases, if the thickness of the substrate 102 is too large, the weight of the extreme ultraviolet light mask 100 is unnecessarily increased.

In some embodiments, the conductive layer 104 is disposed on the back surface of the substrate 102. In some embodiments, the conductive layer 104 is in direct contact with the back surface of the substrate 102. The conductive layer 104 may provide electrostatic coupling of the extreme ultraviolet light shield 100 to an electrostatic shield chuck (chuck) (not shown) during fabrication and use of the extreme ultraviolet light shield 100. In some embodiments, the conductive layer 104 comprises chromium nitride (CrN). In some embodiments, the conductive layer 104 is formed by a deposition process, such as Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or Physical Vapor Deposition (PVD). The thickness of the conductive layer 104 is controlled such that the conductive layer 104 is optically transparent.

The reflective multilayer structure 110 is disposed over a front surface of the substrate 102 opposite the back surface. In some embodiments, the reflective multilayer structure 110 is in direct contact with the front surface of the substrate 102. The reflective multilayer structure 110 provides high reflectivity to extreme ultraviolet light. In some embodiments, the reflective multilayer structure 110 is configured to achieve a reflectance of about 60% to about 75% at wavelengths peaking at extreme ultraviolet light. In some embodiments, the reflective multilayer structure 110 includes alternating stacked layers of high index material and low index material. High refractive index materials have a tendency to scatter extreme ultraviolet light, and on the other hand, low refractive index materials have a tendency to transmit extreme ultraviolet light. Pairing these two types of materials together provides resonant reflectivity. In some embodiments, the reflective multilayer structure 110 includes alternating stacked layers of molybdenum (Mo) and silicon (Si). In some embodiments, the reflective multilayer structure 110 includes alternating layers of molybdenum and silicon, with silicon in the top layer. In some embodiments, the molybdenum layer is in direct contact with the front surface of the substrate 102. In other embodiments, the silicon layer is in direct contact with the front surface of the substrate 102. Alternatively, the reflective multilayer structure 110 comprises alternating stacked layers of molybdenum and beryllium (Be).

The thickness of each layer in the reflective multilayer structure 110 depends on the euv light wavelength and the incident angle. The thicknesses of the alternating layers in the reflective multilayer structure 110 are tuned to maximize the constructive interference of the extreme ultraviolet light reflected at each interface and to minimize the overall absorption of the extreme ultraviolet light. In some embodiments, the reflective multilayer structure 110 has a thickness in the range of about 250nm to about 350 nm. In some embodiments, the reflective multilayer structure 110 includes forty pairs of alternating layers of molybdenum and silicon. Each molybdenum/silicon pair has a thickness of about 5nm to about 7nm and a total thickness of about 300 nm.

In some embodiments, each layer in reflective multilayer structure 110 is deposited over substrate 102 and underlying layers using Ion Beam Deposition (IBD) or dc magnetron sputtering. The deposition method used helps to ensure that the reflective multilayer structure 110 has a thickness uniformity across the substrate 102 of better than about 0.85.

The layer 112 is then disposed over the reflective multilayer structure 110. In some embodiments, the sublayer 112 is in direct contact with the topmost surface of the reflective multilayer structure 110. Layer 112 then provides good adhesion for capping layer 114 to be subsequently formed thereon. Accordingly, the adhesion layer 112 helps prevent or reduce self-crystallization (self-crystallization) of the capping layer 114 during the deposition of the material of the capping layer 114, thereby making the capping layer 114 formed thereon amorphous or semi-crystalline. The adhesion layer 112 also acts as a barrier layer preventing the metal in the capping layer 114 from mixing with the silicon in the top silicon layer of the reflective multilayer structure 110 during use of the euv light mask 100. Accordingly, the stability of the extreme ultraviolet light shield 100 is improved.

In some embodiments, the adhesion layer 112 includes or is made of a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In some embodiments, the adhesion layer 112 is formed using a deposition process, such as CVD, PECVD, PVD, or Atomic Layer Deposition (ALD). In some embodiments, the adhesion layer 112 is formed by converting a surface portion of a top silicon layer in the reflective multilayer structure 110 using oxidation and/or nitridation. In some embodiments, the adhesion layer 112 comprises silicon oxide and is formed by converting a surface portion of the top layer of silicon using a thermal oxidation process or a plasma oxidation process.

The thickness of the adhesion layer 112 is controlled to ensure that the adhesion layer 112 continuously covers the underlying reflective multilayer structure 110. In some embodiments, the adhesion layer 112 has a thickness in the range of about 1nm to about 3 nm. In some cases, if the thickness of adhesion layer 112 is too small, continuous coverage of adhesion layer 112 may not be obtained. In this case, the capping layer material may still be deposited directly on the surface of the reflective multilayer structure 110, and crystallization of the capping layer material and/or mixing of the capping layer material with silicon may occur in regions of the reflective multilayer structure 110 not covered by the adhesion layer 112. Crystallization of the capping layer material and/or mixing of the capping layer material with the silicon reduces the uniformity of the capping layer 114, which adversely affects the quality of the euv light shield 100. On the other hand, in some cases, if the thickness of the adhesion layer 112 is too large, the reflectivity of the reflective multi-layer structure 110 is greatly reduced, which results in critical dimension errors in the photolithography process.

A capping layer 114 is disposed over the adhesion layer 112. In some embodiments, capping layer 114 is in direct contact with the top surface of adhesion layer 112. The capping layer 114 helps to prevent oxidation of the top silicon layer in the reflective multilayer structure 110 during fabrication and use of the euv light mask 100. In the present disclosure, because the capping layer 114 is deposited on the adhesion layer 112, which provides a stronger bond for the capping layer 114 than if the capping layer 114 is deposited directly onto the reflective multilayer structure 110, the presence of the adhesion layer 112 helps prevent the capping layer material from self-crystallizing, which results in the generation of a large number of grain boundaries and defect regions. The resulting capping layer 114 of the present disclosure has an amorphous or semi-crystalline structure. Therefore, the capping layer 114 has a smoother surface compared to the crystalline structure, which helps to improve the uniformity of the capping layer 114.

In some embodiments, capping layer 114 comprises a material that is resistant to oxidation and corrosion, and is less chemically reactive with common atmospheric gas species, such as oxygen, nitrogen, and water vapor. In some embodiments, the capping layer 114 includes a transition metal, such as ruthenium (Ru), iridium (Ir), rhodium (Rh), platinum (Pt), palladium (Pd), osmium (Os), rhenium (Re), vanadium (V), tantalum (Ta), hafnium (Hf), tungsten (W), molybdenum (Mo), zirconium (Zr), manganese (Mn), or technetium (Tc).

In some embodiments, the capping layer 114 further comprises one or more dopants having a carbon solubility less than the carbon solubility of the material of the capping layer 114. In some embodiments, the dopant has a carbon solubility that is less than the carbon solubility of the transition metal in capping layer 114. Exemplary dopants include, but are not limited to, niobium (Nb), titanium (Ti), zirconium (Zr), yttrium (Y), boron (B), and phosphorus (P). The introduction of dopants into the capping layer 114 helps prevent carbon accumulation in the capping layer 114 during use of the euv light shield 100, which improves the long-term stability of the euv light shield 100. The amount of dopant in capping layer 114 is controlled to prevent the formation of an intermetallic of the two metals that reduces the uniformity of capping layer 114. In some embodiments, the ratio of ruthenium to dopant element is controlled in the range of about 1:0 to about 2: 1. In some embodiments, the concentration of dopants in capping layer 114 is less than about 50 atomic percent (at.%). Because the dopant element typically has a density that is less than the density of ruthenium, if a dopant is incorporated into the capping layer 114, the resulting capping layer 114 has a density that is less than the bulk density of ruthenium (e.g., about 12.45 g/cm)³)。

In some embodiments, the capping layer 114 is formed using a deposition process (e.g., IBD, CVD, PVD, or ALD). In some embodiments, after the capping layer 114 is formed, dopants are introduced into the capping layer 114 by ion implantation. In some embodiments, the dopant is co-deposited with the material of capping layer 114.

An absorber layer 116 is disposed over capping layer 114. In some embodiments, the absorber layer 116 is in direct contact with the top surface of the capping layer 114. The absorption layer 116 includes a material having a high absorption coefficient in the extreme ultraviolet wavelength. In some embodiments, the absorption layer 116 comprises a material having a high absorption coefficient at a wavelength of 13.5 nm. In some embodimentsIn the absorber layer 116, chromium (Cr), chromium oxide (CrO), titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), molybdenum, aluminum copper (Al-Cu), palladium (Pd), tantalum boride (TaBN), tantalum boride oxide (TaBO), aluminum oxide (Al)₂O₃) Silver oxide (Ag)₂O) or combinations thereof, or made of the above materials. In some embodiments, the absorbent layer 116 has a single-layer structure. In some other embodiments, the absorbent layer 116 has a multi-layer structure. In some embodiments, the absorber layer 116 is formed by a deposition process (e.g., CVD, PECVD, PVD, or ALD).

An anti-reflective layer 118 is disposed over the absorbing layer 116. In some embodiments, the antireflective layer 118 is in direct contact with the top surface of the absorber layer 116. The antireflective layer 118 reduces the reflection of light from underlying layers during photolithographic patterning of the photoresist layer 140 and, thus, helps to increase the accuracy of the pattern formed in the photoresist layer 140. In some embodiments, antireflective layer 118 includes a metal oxide, such as tantalum oxide (TaO) or tantalum oxyboride (TaBO), a metal, such as ruthenium, titanium, niobium (Nb), zirconium (Zr), hafnium (Hf), platinum (Pt), or iridium (Ir). In some embodiments, the anti-reflective layer 118 is formed using a deposition process (e.g., CVD, PECVD or PVD).

The hard mask layer 130 is disposed over the anti-reflective layer 118. In some embodiments, the hard mask layer 130 is in direct contact with the antireflective layer 118. In some embodiments, the hard mask layer 130 comprises a dielectric oxide (such as silicon dioxide) or a dielectric nitride (such as silicon nitride). In some embodiments, the hard mask layer 130 is formed using a deposition process (e.g., CVD, PECVD, or PVD).

A photoresist layer 140 is disposed over the hard mask layer 130. The photoresist layer 140 includes a photosensitive material that can be patterned by irradiation with light. In some embodiments, the photoresist layer 140 includes a positive photoresist material, a negative photoresist material, or a hybrid photoresist material. In some embodiments, the photoresist layer 140 is applied to the surface of the hard mask layer 130 by a deposition process, such as spin coating.

Referring to fig. 2 and 3B, according to some embodiments, the method 200 proceeds to step 204, where the photoresist layer 140 is patterned to form a patterned photoresist layer 140P in step 204. The photoresist layer 140 is patterned by first projecting a pattern of light into the photoresist layer 140. Next, depending on whether a positive photoresist or a negative photoresist is used in the photoresist layer 140, the exposed portion or the unexposed portion of the photoresist layer 140 is removed using a photoresist developer, thereby forming a patterned photoresist layer 140P having an opening 142 patterned therein. The opening 142 exposes a portion of the hard mask layer 130. The opening 142 is located in the pattern area 100A and corresponds to the position of the pattern of the opening 122 in the euv light mask 100 (as shown in fig. 1).

Referring to fig. 2 and 3C, according to some embodiments, the method 200 proceeds to step 206 by etching the hard mask layer 130 to form the patterned hard mask layer 130P in step 206 using the patterned photoresist layer 140P as an etch mask. The portion of the hard mask layer 130 exposed by the opening 142 is etched to form an opening 144 extending through the hard mask layer 130. Opening 144 exposes a portion of antireflective layer 118. In some embodiments, the hard mask layer 130 is etched using an anisotropic etch. In some embodiments, the anisotropic etch is a dry etch (e.g., Reactive Ion Etch (RIE), a wet etch, or a combination thereof) that selectively removes the material of the hard mask layer 130 but not the material of the anti-reflective layer 118. the remaining portion of the hard mask layer 130 comprises the patterned hard mask layer 130P. if the patterned photoresist layer 140P is not completely consumed during the etching of the hard mask layer 130, the patterned photoresist layer 140P is removed from the surface of the patterned hard mask layer 130P after the etching of the hard mask layer 130, for example, using a wet strip or plasma ashing.

Referring to fig. 2 and 3D, according to some embodiments, the method 200 proceeds to step 208, where the anti-reflective layer 118 and the absorber layer 116 are etched using the patterned hard mask layer 130P as an etch mask to form the patterned anti-reflective layer 118P and the patterned absorber layer 116P, respectively, in step 208. The portions of antireflective layer 118 exposed by opening 144 and the portions of absorber layer 116 underlying the exposed portions of antireflective layer 118 are etched to form openings 122 extending through antireflective layer 118 and absorber layer 116. The opening 122 is located in the pattern area 100A of the euv light shield 100 and corresponds to a circuit pattern formed on a semiconductor wafer. The opening 122 exposes a portion of the capping layer 114. In some embodiments, the ARC layer 118 and the absorber layer 116 are etched using a single anisotropic etch process. In some embodiments, the anisotropic etch is a dry etch (e.g., RIE), a wet etch, or a combination thereof, which selectively removes the antireflective layer 118 and the absorber layer 116 material but not the capping layer 114 material. In some embodiments, two different anisotropic etch processes are used to etch the ARC layer 118 and the absorber layer 116. Each anisotropic etch may be a dry etch (e.g., RIE), a wet etch, or a combination thereof. The first etch selectively removes the material of the anti-reflective layer 118 but not the material of the absorber layer 116, and the second etch selectively removes the material of the absorber layer 116 but not the material of the capping layer 114. The remaining portion of antireflective layer 118 constitutes patterned antireflective layer 118P. The remaining portions of the absorber layer 116 constitute a patterned absorber layer 116P.

Referring to fig. 2 and 3E, according to some embodiments, the method 200 proceeds to step 210, where the patterned hard mask layer 130P is removed in step 210. In some embodiments, the patterned hard mask layer 130P is removed from the surface of the patterned anti-reflective layer 118P, for example, using an oxygen plasma or a wet etch.

Referring to fig. 2 and 3F, according to some embodiments, the method 200 proceeds to step 212, where a photoresist layer 150 is formed on the capping layer 114 and the patterned anti-reflective layer 118P in step 212. The photoresist layer 150 fills the opening 122 in the pattern area 100A of the substrate 102. In some embodiments, the photoresist layer 150 comprises a positive photoresist material, a negative photoresist material, or a hybrid photoresist material. In some embodiments, the photoresist layer 150 comprises the same material as the photoresist layer 140 in FIG. 3A. In some embodiments, photoresist layer 150 comprises a different material than photoresist layer 140. In some embodiments, photoresist layer 150 is formed by, for example, spin coating.

Referring to fig. 2 and 3G, according to some embodiments, the method 200 proceeds to step 214 where the photoresist layer 150 is patterned in step 214 to form a patterned photoresist layer 150P containing a pattern of openings 152. The opening 152 exposes a portion of the patterned anti-reflective layer 118P where the trench 124 is to be formed in the peripheral region 100B of the euv light shield 100 (as shown in fig. 1). In some embodiments, the photoresist layer 150 is exposed to a light pattern, and a photoresist developer is used to remove exposed or unexposed portions of the photoresist layer 150 to pattern the photoresist layer 150, depending on whether a positive or negative tone photoresist is used. The remaining portion of photoresist layer 150 constitutes patterned photoresist layer 150P.

Referring to fig. 2 and 3H, according to some embodiments, the method 200 proceeds to step 216 by etching the patterned anti-reflective layer 118P, the patterned absorber layer 116P, the capping layer 114, the adhesion layer 112, and the reflective multi-layer structure 110 using the patterned photoresist layer 150P as an etch mask in step 216 to form the trench 124 in the peripheral region 100B of the substrate 102. In some embodiments, the trench 124 extends into the reflective multilayer structure 110. In some embodiments, the trench 124 exposes a surface of the substrate 102.

In some embodiments, the patterned ARC layer 118P, the patterned absorber layer 116P, the capping layer 114, the adhesion layer 112, and the reflective multi-layer structure 110 are etched using a single anisotropic etch process. The anisotropic etch may be a dry etch (e.g., RIE), a wet etch, or a combination thereof, which selectively removes the materials of the patterned anti-reflective layer 118P, the patterned absorber layer 116P, the capping layer 114, the adhesion layer 112, and the reflective multi-layer structure 110, but not the material of the substrate 102. In some embodiments, the patterned ARC layer 118P, the patterned absorber layer 116P, the capping layer 114, the adhesion layer 112, and the reflective multi-layer structure 110 are etched using a plurality of different anisotropic etch processes. Each anisotropic etch may be a dry etch (e.g., RIE), a wet etch, or a combination thereof.

After the trench 124 is formed, the patterned photoresist layer 150P is removed, for example, by wet stripping or plasma ashing. Removal of the patterned photoresist layer 150P re-exposes the surface of the substrate 102 in the opening 122.

Many variations and/or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the reflective multilayer structure 110 is replaced with another reflective structure having a single-layer structure.

One aspect of the present disclosure relates to an extreme ultraviolet light mask. The EUV mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The capping layer includes an amorphous conductive material.

In some embodiments, the adhesion layer comprises silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments, the capping layer comprises amorphous ruthenium. In some embodiments, the capping layer comprises semi-crystalline ruthenium. In some embodiments, the capping layer further comprises one or more dopants having a carbon solubility less than that of the amorphous conductive material of the capping layer. In some embodiments, the dopant is selected from the group consisting of niobium, titanium, zirconium, yttrium, boron, and phosphorus. In some embodiments, the concentration of the one or more dopants in the capping layer is less than 50 atomic percent. In some embodiments, the adhesion layer has a thickness of about 1nm to about 3 nm. In some embodiments, the euv light mask further comprises a patterned antireflective layer over the patterned absorber layer.

Another aspect of the present disclosure is directed to an extreme ultraviolet light mask. The EUV mask includes a substrate, a reflective multilayer structure over the substrate, an adhesion layer over the reflective multilayer structure, a capping layer over the adhesion layer, and a patterned absorber layer over the capping layer. The adhesion layer comprises a dielectric material, and the capping layer comprises an amorphous conductive material.

In some embodiments, the adhesion layer comprises silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments, the capping layer comprises amorphous ruthenium. In some embodiments, the capping layer further comprises one or more dopants selected from the group consisting of niobium, titanium, zirconium, yttrium, boron, and phosphorus. In some embodiments, the reflective multilayer structure comprises alternating layers of molybdenum and silicon, with the topmost layer in the reflective multilayer structure being silicon. In some embodiments, the patterned absorber layer comprises chromium, chromium oxide, titanium nitride, tantalum, titanium, molybdenum, aluminum copper, palladium, tantalum boride, aluminum oxide, or silver oxide. In some embodiments, the euv light mask further comprises a patterned antireflective layer over the patterned absorber layer. In some embodiments, the patterned antireflective layer comprises tantalum oxide or tantalum oxyboride.

Yet another aspect of the present disclosure is directed to a method of forming an extreme ultraviolet light mask. The method includes depositing a reflective multilayer structure over a substrate. The method further includes forming an adhesion layer over the reflective multilayer structure. The method further includes depositing a capping layer over the adhesion layer. The capping layer includes an amorphous conductive material. The method further includes depositing an absorber layer over the capping layer. The method further includes etching the absorber layer to form a plurality of openings exposing a surface of the capping layer.

In some embodiments, the method further includes etching the absorber layer, the capping layer, and the reflective multilayer structure to form a plurality of trenches surrounding the plurality of openings in the peripheral region of the substrate. In some embodiments, the method further comprises doping the capping layer with one or more dopants.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.