阅读说明：本技术 结型场效应晶体管及其制备方法 (Junction field effect transistor and preparation method thereof ) 是由 张胜利 周戬 程子超 高洁 宋秀峰 陈翔 于 2020-10-29 设计创作，主要内容包括：本发明公开了一种结型场效应晶体管及其制备方法。所述的结型场效应晶体管包括衬底、N型二硫化钨薄膜、P型InGeTe_3薄膜、源电极、漏电极和顶栅电极,N型二硫化钨薄膜设于衬底的表面,源电极与漏电极设于N型二硫化钨薄膜表面的两端,P型InGeTe_3薄膜设于N型二硫化钨薄膜表面且位于源电极与漏电极之间,顶栅电极设于P型InGeTe_3薄膜的表面且位于源电极与漏电极之间。本发明将WS_2和InGeTe_3应用于JFET中,通过调控P型InGeTe_3薄膜的电压来实现N型二硫化钨薄膜中耗尽区的宽度,实现沟道电导的调节,确保抑制界面缺陷的产生,减少界面态对载流子输运的影响,并借助JFET没有复杂介电工程的优势,降低器件的亚阈值摆幅,提高开关比和电流密度。(The invention discloses a junction field effect transistor and a preparation method thereof. The junction field effect transistor comprises a substrate, an N-type tungsten disulfide film and a P-type InGeTe 3 A film, a source electrode, a drain electrode and a top gate electrode, wherein the N-type tungsten disulfide film is arranged on the surface of the substrate, the source electrode and the drain electrode are arranged at two ends of the surface of the N-type tungsten disulfide film, and the P-type InGeTe is 3 The film is arranged on the surface of the N-type tungsten disulfide film and is positioned between the source electrode and the drain electrode, and the top gate electrode is arranged on the P-type InGeTe 3 The surface of the film is positioned between the source electrode and the drain electrode. WS of the invention 2 And InGeTe 3 Applied to JFET (junction field effect transistor) by regulating and controlling P-type InGeTe 3 The voltage of the film realizes the width of a depletion region in the N-type tungsten disulfide film, realizes the adjustment of channel conductance, ensures that the generation of interface defects is inhibited, and reduces the boundaryThe influence of the surface state on carrier transport is avoided, the advantage of no complex dielectric engineering of a JFET is utilized, the sub-threshold swing amplitude of the device is reduced, and the switching ratio and the current density are improved.)

1. A junction field effect transistor, comprising: substrate, N-type tungsten disulfide film and P-type InGeTe₃A thin film, a source electrode, a drain electrode, and a top gate electrode.

2. The junction field effect transistor of claim 1, wherein the N-type tungsten disulfide film is disposed on the surface of the substrate, the source electrode and the drain electrode are disposed at two ends of the surface of the N-type tungsten disulfide film, and the P-type InGeTe₃The film is arranged on the surface of the N-type tungsten disulfide film, and the P-type InGeTe₃The film is positioned between the source electrode and the drain electrode; the top gate electrode is arranged on the P-type InGeTe₃The surface of the film, and the top gate electrode is located between the source electrode and the drain electrode.

3. The junction field effect transistor as in claim 1 wherein the substrate is SiO₂、Al₂O₃BN, SiNx or AlN substrate, or base material₂、Al₂O₃BN, SiNx, AlN as a substrate.

4. The junction field effect transistor according to claim 1, wherein the thickness of the N-type tungsten disulfide film is 1nm to 200nm, more preferably 1nm to 50 nm; the P type InGeTe₃The film has a thickness of 1 to 200nm, more preferably 50 to 100 nm.

5. The junction field effect transistor according to claim 1, wherein the source electrode, the drain electrode and the top gate electrode are one or a combination of Cr, Ti, Ni, Au, Pd, Pt and Ag, and have a thickness of 40nm to 100 nm.

6. The method for manufacturing a junction field effect transistor according to any one of claims 1 to 5, comprising the steps of:

preparing an N-type tungsten disulfide film on a substrate;

step (2), preparing InGeTe on PDMS₃A film;

step (3) is to use the InGeTe prepared in the step (2)₃Transferring the film to the N-type tungsten disulfide film prepared in the step (1);

step (4), the product with InGeTe prepared in step (3)₃And preparing a source electrode pattern, a drain electrode pattern and a top gate electrode pattern on the substrate of the film and the tungsten disulfide film, and carrying out metal deposition on the source electrode pattern, the drain electrode pattern and the top gate electrode pattern to obtain a source electrode, a drain electrode and a top gate electrode.

7. The preparation method according to claim 6, wherein in the step (1), the N-type tungsten disulfide film is prepared on the substrate by using a mechanical stripping method.

8. The method according to claim 6, wherein in the step (2), InGeTe is prepared on PDMS₃The method of the film comprises the following steps: a smooth surfaced PDMS film was attached to the upper surface of the slide and prepared with InGeTe obtained by mechanical stripping₃Adhesive tape of sample, adhering the adhesive tape tightly on PDMS film to make InGeTe₃Contacting the sample with PDMS film, removing the adhesive tape, InGeTe₃The thin film is attached to the PDMS film.

9. The method according to claim 6, wherein in the step (3), InGeTe is added₃The method for transferring the film to the tungsten disulfide film comprises the following steps: rotating the slide to load InGeTe₃The PDMS film of the film faces downwards, and the glass slide is arranged on the three-dimensional displacement platform; observing with microscope, InGeTe₃Aligning the thin film to the target to be transferred, gradually approaching the PDMS film through a three-dimensional displacement platform and enabling the InGeTe to be in contact with the PDMS film₃The film contacts the tungsten disulfide film while heating the substrate and gradually raising the slide to cause InGeTe₃Film separation from PDMS film, InGeTe₃The film is pressed against the tungsten disulfide film.

10. The manufacturing method according to claim 6, wherein in the step (4), the source electrode pattern, the drain electrode pattern and the top gate electrode pattern are manufactured by a method of photolithography, an electron beam exposure technique or a laser direct writing technique; and performing metal deposition by adopting an electron beam evaporation technology, a thermal evaporation technology, a magnetron sputtering technology or a pulse laser deposition technology to obtain a source electrode, a drain electrode and a top gate electrode.

Technical Field

The invention belongs to the technical field of semiconductors, relates to a junction field effect transistor and a preparation method thereof, and particularly relates to a junction field effect transistor based on InGeTe₃And a tungsten disulfide junction field effect transistor and a method of making the same.

Background

By WS₂And MoS₂The two-dimensional Transition Metal Sulfides (TMDCs) represented by the general formula have the advantages of atomic-scale thickness, adjustable band gap, no surface dangling bond and excellent mechanical properties, are considered to be semiconductor materials with great potential, and have wide application prospects in the fields of photoelectricity, microelectronics, wearable flexible devices, military information and the like. And InGeTe₃As a novel ternary material with a layered structure, the ternary material is a new star in the field of low-dimensional material research due to the excellent physical and chemical properties of the ternary material. Theoretically predicted, InGeTe₃The material is a direct semiconductor from a bulk to a single layer, and the single layer is InGeTe₃The direct band gap is about 1.41eV, the visible light absorption is strong, the electron carrier mobility is very high, and can reach 3 multiplied by 10³cm²V^-1s^-1Has wide prospect in the application fields of solar cells, photodetectors, field effect transistors and the like (J.Mater.chem.A., 2017,5(36): 19406-.

In recent years, as the silicon-based semiconductor technology is continuously advanced, the size of a transistor is close to the physical limit, and a semiconductor device faces the challenges of short channel effect, increased drain-gate leakage current and increased power consumption. Metal-oxide semiconductor field effect transistors (MOSFETs) are widely used in the electronics field due to their advantages of high impedance, high operating efficiency, good thermal stability, and the like. In practice, however, the quality of the MOSFET oxide dielectric severely limits its electrical performance and stability. In contrast, Junction Field Effect Transistors (JFETs) operate by changing the depletion region in the semiconductor channel with a reverse biased p-n junction, and therefore there is no dielectric or related problems. At the same time, the JFET has small device size, low frequency noise and high input impedanceAnd the method has the advantages of wide application prospect in the fields of integrated circuits, photoelectric detectors and the like. In the JFET, the sub-threshold swing (SS) of the JFET can be close to 60mV dec due to the fact that the capacitance from a grid electrode to a channel is far larger than that from a source electrode to the channel in the JFET^-1This also makes JFETs superior to MOSFETs for low power device applications.

At present, the literature reports that a two-dimensional material heterojunction is made into a JFET which is applied to the field of photoelectric and low-power consumption devices (Adv. Mater.,2019,1902962; ACS appl. Mater. interfaces,2018,10, 29724-. The university-extended Pyo Jin Jeon utilizes Black Phosphorus (BP) and ZnO materials to construct a heterojunction, and the prepared JFET realizes the inverter function of a logic circuit, but the switching current ratio of the JFET is only about 10⁴The subthreshold swing averages over 300mV/dec, and stability is typical (Nano Lett.,2016,16, 1293-. And June Yeong Lim subject group, et al, also at the university of Korea, based on two TMDCs materials (MoTe)₂And MoS₂) The JFET is constructed, although the mobility of the obtained device is high, and the subthreshold swing is reduced to 204mV/dec, the maximum on-off current ratio of the device is only 5 multiplied by 10⁴(NPJ 2D mater.and appl.,2018,2, 37). In the existing works, researchers make some more traditional TMDC materials and metal oxide semiconductor materials into heterojunctions to further construct JFET devices, and the exploration and innovation on material selection are lacked, and the performance of the devices is general.

Disclosure of Invention

The invention aims to provide a method based on InGeTe₃And a tungsten disulfide junction field effect transistor and a method of making the same. The invention firstly uses the two-dimensional ternary semiconductor material InGeTe without surface dangling bond₃Thin film and two-dimensional WS₂Combining the films to construct a p-n junction, and adding InGeTe₃/WS₂The heterojunction is processed into a high-performance JFET, so that the carrier mobility is improved, the subthreshold swing of the device is reduced, and the performance of the device is improved.

The technical scheme for realizing the purpose of the invention is as follows:

a junction field effect transistor comprising: substrate, N-type tungsten disulfide film and P-type InGeTe₃A thin film, a source electrode, a drain electrode, and a top gate electrode.

In the junction field effect transistor, the N-type tungsten disulfide film is arranged on the surface of the substrate, the source electrode and the drain electrode are arranged at two ends of the surface of the N-type tungsten disulfide film, and the P-type InGeTe₃The film is arranged on the surface of the N-type tungsten disulfide film, and the P-type InGeTe₃The film is positioned between the source electrode and the drain electrode; the top gate electrode is arranged on the P-type InGeTe₃The surface of the film, and the top gate electrode is located between the source electrode and the drain electrode.

In the present invention, the substrate is an insulating substrate conventionally used in the art, including but not limited to SiO₂、Al₂O₃BN, SiNx, AlN substrate, or base material₂、Al₂O₃BN, SiNx, AlN as a substrate. The substrate material is a material conventionally used in the art, including but not limited to Si or Plastic (PET).

Furthermore, the thickness of the N-type tungsten disulfide film is 1 nm-200 nm, and more preferably 1 nm-50 nm.

Further, the P type InGeTe₃The film has a thickness of 1 to 200nm, more preferably 50 to 100 nm.

Further, the source electrode, the drain electrode and the top gate electrode are the source electrode, the drain electrode and the top gate electrode which are conventionally used in the field, are one or a combination of more of Cr, Ti, Ni, Au, Pd, Pt and Ag, and have the thickness of 40 nm-100 nm.

The invention also provides a preparation method of the junction field effect transistor, which comprises the following steps:

preparing an N-type tungsten disulfide film on a substrate;

step (2), preparing InGeTe on PDMS₃A film;

step (3) is to use the InGeTe prepared in the step (2)₃Transferring the film to the N-type tungsten disulfide film prepared in the step (1);

step (4), the product with InGeTe prepared in step (3)₃And preparing a source electrode pattern, a drain electrode pattern and a top gate electrode pattern on the substrate of the film and the tungsten disulfide film, and carrying out metal deposition on the source electrode pattern, the drain electrode pattern and the top gate electrode pattern to obtain a source electrode, a drain electrode and a top gate electrode.

Specifically, in the step (1), an N-type tungsten disulfide film is prepared on the substrate by adopting a mechanical stripping method.

Specifically, in the step (2), InGeTe is prepared on PDMS₃The method of the film comprises the following steps: a smooth surfaced PDMS film was attached to the upper surface of the slide and prepared with InGeTe obtained by mechanical stripping₃Adhesive tape of sample, adhering the adhesive tape tightly on PDMS film to make InGeTe₃Contacting the sample with PDMS film, removing the adhesive tape, InGeTe₃The thin film is attached to the PDMS film.

Specifically, in the step (3), InGeTe is added₃The method for transferring the film to the tungsten disulfide film comprises the following steps: rotating the slide to load InGeTe₃The PDMS film of the film faces downwards, and the glass slide is arranged on the three-dimensional displacement platform; observing with microscope, InGeTe₃Aligning the thin film to the target to be transferred, gradually approaching the PDMS film through a three-dimensional displacement platform and enabling the InGeTe to be in contact with the PDMS film₃The film contacts the tungsten disulfide film while heating the substrate and gradually raising the slide to cause InGeTe₃Film separation from PDMS film, InGeTe₃The film is pressed against the tungsten disulfide film.

Specifically, in the step (4), a source electrode pattern, a drain electrode pattern and a top gate electrode pattern are prepared by a method of a photolithography technique, an electron beam exposure technique or a laser direct writing technique.

Specifically, in the step (4), metal deposition is performed by using an electron beam evaporation technology, a thermal evaporation technology, a magnetron sputtering technology or a pulsed laser deposition technology to obtain a source electrode, a drain electrode and a top gate electrode.

Compared with the prior art, the invention has the following advantages:

the present invention adopts transfer method to make WS without surface dangling bond₂And InGeTe₃Equal two-dimensionalThe JFET is prepared from the semiconductor, so that the generation of interface defects is prevented, the purity of an interface is ensured, the influence of an interface state on carrier transport is reduced, and the on-off ratio (more than 10) of the device is improved by virtue of the fact that the JFET does not have the advantage of complex dielectric engineering⁵) The sub-threshold swing SS (about 200mV/dec) is reduced, and the method has great advantages in the application of low-power consumption and high-performance devices.

Drawings

FIG. 1 is an InGeTe-based version of the present invention₃And a schematic view of a junction field effect transistor of tungsten disulfide; in the figure: 1. a substrate; 2. a tungsten disulfide film; 3. InGeTe₃A film; 4. a source electrode; 5. a drain electrode; 6. and a top gate electrode.

FIG. 2 is InGeTe-based alloy prepared by example₃And an optical micrograph of a tungsten disulfide junction field effect transistor;

FIG. 3 is a graph of the electrical output characteristics of the junction field effect transistor fabricated in accordance with the example;

fig. 4 is a graph of the electrical transfer characteristics of the junction field effect transistor prepared in the example.

Detailed Description

The invention is described in more detail below with reference to specific embodiments and the attached drawings.

FIG. 1 is an InGeTe-based version of the present invention₃And tungsten disulfide. The junction field effect transistor comprises: substrate layer 1, tungsten disulfide thin film layer 2, InGeTe₃A thin film layer 3, a source electrode 4, a drain electrode 5, a top gate electrode 6, a tungsten disulfide thin film layer 2 and InGeTe₃The thin film layer 3 is in van der Waals contact to form tungsten disulfide/InGeTe₃A heterojunction.

Examples

In this example, the thickness of the tungsten disulfide film is 10nm, InGeTe₃The thickness of the film was 150 nm.

In the junction field effect transistor prepared in this example, the substrate was Si/SiO₂The source electrode, the drain electrode and the top gate electrode are Cr/Au, and the thickness of the source electrode, the drain electrode and the top gate electrode is Cr: 10nm, Au: 50 nm.

The preparation process comprises the following steps:

(1) selecting a thermal oxidation silicon wafer as a substrate, firstly performing ultrasonic treatment for 5min by using ethanol, acetone and deionized water respectively, then performing heat treatment on the substrate for 1h at 300 ℃ on a heating table, standing in a dry environment and storing;

(2) preparing Sigao adhesive tape, mixing WS₂The single crystal is repeatedly torn and adhered on the SiGao adhesive tape until the surface of the adhesive tape has no obvious fluctuation, then the adhesive tape is adhered on the surface of the silicon oxide substrate and is compressed, and the adhesive tape is taken down after 6 hours, so that the needed N-type tungsten disulfide film can be obtained on the surface of the substrate.

(3) A smooth-surfaced PDMS (polydimethylsiloxane) film was attached to the upper surface of the glass slide and prepared with InGeTe obtained by mechanical peeling₃Adhesive tape of sample, adhering the adhesive tape tightly on PDMS film to make InGeTe₃Contacting the sample with PDMS film, removing the adhesive tape, InGeTe₃I.e. attached to the PDMS film.

(4) Rotating the slide to load InGeTe₃The PDMS film of the film faces downwards, and the glass slide is arranged on the three-dimensional displacement platform; observing with microscope, InGeTe₃Aligning the thin film to the target to be transferred, gradually approaching the PDMS film through a three-dimensional displacement platform and enabling the InGeTe to be in contact with the PDMS film₃The film contacts the tungsten disulfide film while heating the substrate and gradually raising the slide to cause InGeTe₃Film separation from PDMS film, InGeTe₃The film is pressed against the tungsten disulfide film.

(5) Then, a photoresist is spin-coated on the substrate, and a source electrode pattern, a drain electrode pattern, and a top gate electrode pattern are prepared using an electron beam exposure technique. And sequentially depositing Cr and Au films on the source electrode pattern, the drain electrode pattern and the top gate electrode pattern by adopting an electron beam evaporation technology. Then, the substrate evaporated with Cr and Au is put into acetone for cleaning, the photoresist is removed, the residual acetone is cleaned by isopropanol, and the substrate is dried by a nitrogen gun. Obtaining a product based on InGeTe₃And tungsten disulfide, as shown in figure 2.

The junction field effect transistor prepared in this example utilized tungsten disulfide as a channel, InGeTe₃The film is used as a gate electrode, and the electrical property of the transistor is improvedThe test can be performed, and the test results are shown in fig. 3 and 4. InGeTe-based from FIG. 3₃The transfer characteristic curve of the JFET with tungsten disulfide shows that the threshold voltage is-1.4V, the subthreshold swing is 250meV/dec, and the switching ratio is more than 10⁵. As can be seen from the output characteristic curve of the jfet of fig. 4, the device exhibits good current saturation and sharp pinch-off characteristics at the top gate voltage Vtg of 0.5V, 0V, and-0.5V. This illustrates the use of InGeTe₃The film is used as a top grid electrode, a depletion region of an N-type tungsten disulfide channel is well regulated and controlled, and the junction field effect transistor shows excellent electrical characteristics.