Voltage type phase interpolator circuit
阅读说明：本技术 一种电压型相位插值器电路 (Voltage type phase interpolator circuit ) 是由 魏来 于 2020-08-12 设计创作，主要内容包括：本发明公开了一种电压型相位插值器电路,包括：电压型相位插值器,该电压型相位插值器的电源端连接由DLL lpf控制的LDO电流管。采用DLL lpf控制的LDO电流管去控制相位插值模块的电源。只需要优化好正常工作电压、室温的相位插值器的线性度,在不同PVT时,DLL的lpf都会找到合适的工作电压去控制相位插值模块的电流,所以在不同的PVT,相位插值器都会得到比较满意的线性度。(The invention discloses a voltage type phase interpolator circuit, which comprises: and a power supply end of the voltage type phase interpolator is connected with an LDO current tube controlled by the DLL lpf. And the LDO current tube controlled by the DLL lpf is used for controlling the power supply of the phase interpolation module. Only the linearity of the phase interpolator with normal working voltage and room temperature needs to be optimized, and the lpf of the DLL can find proper working voltage to control the current of the phase interpolation module when different PVTs are used, so that the phase interpolator can obtain satisfactory linearity when different PVTs are used.)
1. A voltage-mode phase interpolator circuit, comprising: and a power supply end of the voltage type phase interpolator is connected with an LDO current tube controlled by the DLL lpf.
2. The voltage-mode phase interpolator circuit of claim 1, wherein the voltage-mode phase interpolator comprises: a first data selector, a second data selector, a first inverter, a second inverter, and a third inverter, wherein,
two input ends of the first data selector are connected with a clock signal clk0 with a phase of 0 degree and a clock signal clk180 with a phase of 180 degrees; the control terminal receives a first phase selection signal of a clock signal clk0 and a clock signal clk 180; the output end of the first inverter is connected with the input end of the first inverter and outputs a selected interpolation signal;
the control end of the first reverser receives a weight selection signal of the weight occupied by the two paths of interpolation signals output by the first data selector; the output end of the third inverter is connected with the input end of the third inverter;
the output end of the third inverter is used as the output end of the voltage type phase interpolator;
two input ends of the second data selector are connected with a clock signal clk90 with a phase of 90 degrees and a clock signal clk270 with a phase of 270 degrees; the control end receives a second phase selection signal of the clock signal clk90 and the clock signal clk 270; the output end of the second inverter is connected with the input end of the second inverter and outputs the selected interpolation signal;
the control end of the second reverser receives a weight selection signal of the weight occupied by the two paths of interpolation signals output by the second data selector; the output end is connected with the input end of the third reverser.
3. The voltage-mode phase interpolator circuit of claim 1, further comprising: a logic control unit for decoding the required phase selection signal and weight selection signal according to the input signal;
the logic control unit decodes the first input signal and outputs a first phase selection signal and a second phase selection signal;
the logic control unit decodes the output weight selection signal from the second input signal.
4. The voltage-type phase interpolator circuit of claim 1, wherein the lpf outputs the Vlpf to the LDO current pipe.
Technical Field
The invention relates to a voltage-type phase interpolator circuit.
Background
In recent years, the shift in the chip industry from low-rate data parallel connections to high-speed serial connections has been driven by the demand for chip design data throughput. In high-speed serial transmission interface circuit design, there are two basic SERDES (parallel-serial and serial-parallel converter) interfaces: a source synchronization and Clock Data Recovery (CDR) protocol. The two types of major differences are in clock, the source synchronous interface has a clock signal accompanied by data, such as MIPI _ PHY (mobile industry processor interface) is the structure; the CDR does not have a separate clock signal, but recovers the clock from the data, such as USB3/3.1(universal serial bus) or PCIE (peripheral component interconnect express) protocol, and the CDR protocol usually operates at a higher data rate and a longer transmission distance, thereby bringing a great design challenge.
Phase interpolator (phase interpolator) is an important core module in CDR design. The jitter of input data is tracked in real time by controlling the delay of a clock, so that the error rate of data reception is reduced. Since the data transmission speed is extremely fast and generally reaches Gb/s, the clock delay of each stage is often required to be designed to be in ps clock units, and therefore, the design of the phase interpolator for controlling the clock delay is a difficult point.
In a real-world design, there are many non-idealities (e.g., incompletely matched capacitive loads, noise coupling of signal lines, and PVT processes) that affect the performance of the phase interpolator. If the phase interpolator is ideal, its transfer function will coincide with
Disclosure of Invention
The invention aims to provide a voltage type phase interpolator circuit which can obtain more satisfactory linearity in different PVTs.
The technical scheme for realizing the purpose is as follows:
a voltage-mode phase interpolator circuit comprising: and a power supply end of the voltage type phase interpolator is connected with an LDO current tube controlled by the DLL lpf.
Preferably, the voltage-type phase interpolator includes: a first data selector, a second data selector, a first inverter, a second inverter, and a third inverter, wherein,
two input ends of the first data selector are connected with a clock signal clk0 with a phase of 0 degree and a clock signal clk180 with a phase of 180 degrees; the control terminal receives a first phase selection signal of a clock signal clk0 and a clock signal clk 180; the output end of the first inverter is connected with the input end of the first inverter and outputs a selected interpolation signal;
the control end of the first reverser receives a weight selection signal of the weight occupied by the two paths of interpolation signals output by the first data selector; the output end of the third inverter is connected with the input end of the third inverter;
the output end of the third inverter is used as the output end of the voltage type phase interpolator;
two input ends of the second data selector are connected with a clock signal clk90 with a phase of 90 degrees and a clock signal clk270 with a phase of 270 degrees; the control end receives a second phase selection signal of the clock signal clk90 and the clock signal clk 270; the output end of the second inverter is connected with the input end of the second inverter and outputs the selected interpolation signal;
the control end of the second reverser receives a weight selection signal of the weight occupied by the two paths of interpolation signals output by the second data selector; the output end is connected with the input end of the third reverser.
Preferably, the voltage-type phase interpolator further includes: a logic control unit for decoding the required phase selection signal and weight selection signal according to the input signal;
the logic control unit decodes the first input signal and outputs a first phase selection signal and a second phase selection signal;
the logic control unit decodes the output weight selection signal from the second input signal.
Preferably, the lpf outputs the Vlpf to the LDO current tube.
The invention has the beneficial effects that: the invention is based on a voltage type phase interpolator, and adopts an LDO current tube controlled by DLL lpf to control the power supply of a phase interpolation module. The power supply of the voltage type phase interpolator and the power supply of the delay unit of the delay phase-locked loop are adjusted simultaneously by using the output voltage of the filter of the delay phase-locked loop, so that the voltage type linear interpolator can obtain good differential nonlinearity at different process angles.
Drawings
FIG. 1 is a circuit diagram of a voltage mode phase interpolator circuit of the present invention;
FIG. 2 is a schematic diagram of the transfer function of the voltage-mode phase interpolator circuit of the present invention.
Detailed Description
The invention will be further explained with reference to the drawings.
Referring to fig. 1, the voltage-type phase interpolator circuit of the present invention includes: a voltage-type phase interpolator, whose power supply terminal is connected to an LDO (low dropout regulator)
Specifically, the voltage-type phase interpolator includes: a
Two input ends of the
The control end of the
Two input ends of the second data selector 2 are connected with a clock signal clk90 with a phase of 90 degrees and a clock signal clk270 with a phase of 270 degrees; the second phase selection signals phsel <1> & phselb <1>, phsel <1> and phselb <1> of the control end receiving the clock signal clk90 and the clock signal clk270 are a set of inverted signals, and when phsel <1> is1, clk90 is selected as the other path of interpolation signal; if phsel <1> is 0, clk270 is selected as the other interpolation signal. The output of the second data selector 2 is connected to the input of a second inverter 4. The control end of the second inverter 4 receives a weight selection signal Selb <31:0> & sel <31:0> representing the weight occupied by the two interpolation signals. The output end of the second inverter 4 is connected with the input end of the
The voltage-mode phase interpolator further comprises: the logic control unit 6 is mainly used for decoding a required phase selection signal and a weight selection signal according to an input signal. Namely: logic control unit 6 receives first input signal phase _ sel <1:0> and second input signal mixer _ sel <31:0>, decodes first input signal phase _ sel <1:0> and outputs first phase selection signal phsel <0> & phselb <0> and second phase selection signal phsel <1> & phselb <1 >; the weight selection signal Selb <31:0> & sel <31:0> is decoded and output by the second input signal mixer _ sel <31:0 >.
Every two adjacent clock signals are interpolated with each other to generate a clock signal with any phase delay between 0 degrees and 360 degrees. Where clk0/clk90/clk180/clk270 are four clocks 90 degrees out of phase (where clk0 represents a 0 degree phase clock, clk90 represents a clock 90 degrees out of phase with respect to clk0, clk180 represents a clock 180 degrees out of phase with respect to clk0, and clk270 represents a clock 270 degrees out of phase with respect to clk 0), which come from the DLL circuit. The
The power supply voltage of the voltage type phase interpolator is controlled by a core VDD (the core voltage in the general process refers to a low-voltage device) in the prior art, and the defects are that the core VDD is too low at low temperature and low voltage, the capacitance load is too large, the driving capability of the phase interpolator is insufficient, and functional failure is often caused. And under the condition of high temperature and high pressure, the core VDD is too high, the driving capability of the phase interpolator is too strong, and the phase interpolator is more easily interfered by the noise of the power voltage compared with a differential phase interpolator, so that the linearity of the phase interpolator is influenced. Now controlled by the LDO current pipe, the linearity of the phase interpolator is reduced by the interference of the supply voltage. At low temperature and low voltage, in order to output the clock signal with the same delay, lpf will be stabilized at a higher potential relative to the normal operating voltage, and more current will be supplied to the phase interpolator. At high temperature and high voltage, in order to output the clock signal with the same delay, the lpf is stabilized at a low potential relative to the normal operating voltage, thereby providing a relatively low current to the phase interpolator. Only the linearity of the phase interpolator with normal operating voltage and room temperature needs to be optimized, and when different PVTs (process, voltage and temperature, which represents the state of voltage, process angle and temperature change during process production), the lpf of the DLL finds a proper operating voltage to control the current of the phase interpolation module, so that the phase interpolator can obtain satisfactory linearity in different PVTs. The transfer function of the phase interpolator circuit of fig. 2 will be approximated from the
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.
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