阅读说明：本技术 基于延时链的阵列数据调度平衡电压调节电路及方法 (Delay chain-based array data scheduling balanced voltage regulating circuit and method ) 是由 王镇 孙煜昊 黄乐朋 沈泽昱 朱文涛 于 2020-03-18 设计创作，主要内容包括：本发明公开了一种基于延时链的阵列数据调度平衡电压调节电路及方法。属于神经网络的技术领域。本发明通过分析评估计算阵列的计算规模和存储器的数据读写规模动态地提供计算阵列和存储器的工作电压,通过由延时链组成的电压调节模块将通过延时链控制移位寄存器存储比特数,再由移位寄存器来控制PMOS和NMOS的导通比例输出恒定的电压。恒定的电压将用于计算阵列和存储器,在满足电路工作性能的前提下降低电路的功耗。(The invention discloses a delay chain-based array data scheduling balanced voltage regulating circuit and method. Belongs to the technical field of neural networks. The invention dynamically provides the working voltages of the calculation array and the memory by analyzing, evaluating and calculating the calculation scale of the calculation array and the data read-write scale of the memory, controls the storage bit number of the shift register through the delay chain through the voltage regulation module consisting of the delay chain, and controls the conduction proportion of the PMOS and the NMOS to output constant voltage through the shift register. The constant voltage is used for calculating the array and the memory, and the power consumption of the circuit is reduced on the premise of meeting the working performance of the circuit.)

1. The circuit and the method are characterized by comprising a calculation array, a memory, an array data scheduling balanced voltage adjustment and evaluation module and a delay chain-based voltage adjustment module, wherein the added array data scheduling balanced voltage adjustment and evaluation module and the delay chain-based voltage adjustment module evaluate the calculation scale of the calculation array and the reading scale of the memory to dynamically select the working voltages of the calculation array and the memory, so that the power consumption is reduced when the working performance is met.

2. The delay chain-based array data scheduling balanced voltage adjusting circuit and method as claimed in claim 1, wherein the array data scheduling balanced voltage adjusting and evaluating module reads the calculation scale of the calculation array and the data reading scale of the memory, determines whether there is a necessity of adjusting voltage, inputs the voltage to be adjusted to the delay chain-based voltage adjusting module, for example, there are convolution kernel operations with different sizes and step sizes in convolution layer operation, when the step size parameter is smaller, the data throughput is low, when the step size parameter is smaller, 0.8V voltage is selected as the working voltage of the memory, when the step size is larger and the data needs to be updated more, the array data throughput is high, the calculation array working voltage takes 1.1V, and in addition, several voltages such as 0.9V can be used for adjustment, and in addition, under different usage scenarios, wide voltage dynamic adjustment can be performed, when the real-time requirement of a user is high, the working voltage of the memory is higher; when the array data scheduling balance voltage adjusting and evaluating module is in a low-power-consumption application scene, the working voltage of the memory is adjusted to be low, the array data scheduling balance voltage adjusting and evaluating module can flexibly and dynamically adjust according to the needs of users, and user experience is improved.

3. The delay chain-based array data scheduling balanced voltage regulation circuit and method as claimed in claim 1, wherein the delay chain-based regulated voltage module is composed of a delay chain, a shift register and a PMOS and NMOS array group, and a reference voltage V is initially set_refIs precharged to VDD, the cell delay of each buffer in delay chains 1 and 2 is equal, then, since the pulse width of ENABLE signal for controlling shift register is determined by the length of delay chain, and the number of buffers in delay chain 2 is greater than that of delay chain 1, the pulse width of signal ENABLE2 is greater than that of signal ENABLE1, and the wider the pulse of ENABLE signal, the more bits of output of shift register, and therefore the number of NMOS turned on is greater than that of PMOS turned on, i.e. the discharge current controlled by NMOS switch is greater than the charge current through PMOS, so V is_refDecreases then with V_refThe delay of delay chain 1 is gradually increased, causing the pulse width of signal ENABLE1 to increase, increasing the charge current through the shift register and PMOS switch until the charge current equals the discharge current and the reference voltage will reach a constant value.

4. The array data scheduling balanced voltage adjusting circuit and method based on the delay chain are characterized by comprising a computing array, a memory, an array data scheduling balanced voltage adjusting and evaluating module and a delay chain-based voltage adjusting module; the delay chain-based array data scheduling balanced voltage regulating circuit and the method specifically comprise the following steps:

101. the array data scheduling balance voltage regulation and evaluation module reads the reading and writing scales of a calculation module of a calculation array and a memory, and the specific voltage regulation judgment process is as follows: creating a data access address relation for storing network data and convolution kernel scale; then starting to adjust the thread _ func, and judging whether the scale parameter in the network is effective and whether the voltage needing to be adjusted is necessary; transmitting the necessary voltage after judgment to a voltage regulation module based on a delay chain;

102. the array data scheduling balance voltage regulation and evaluation module outputs the calculated array voltage and the memory voltage output by the delay chain-based regulation voltage module through different delay chains to enable signals with different frequencies, under the enable signals with different frequencies, the number of bits stored in the register is different, and the different number of bits affects the starting proportion of the PMOS and NMOS groups; outputting unused voltage according to different turn-on proportions of PMOS and NMOS;

103. the voltage of the computing array and the voltage of the memory, which are output by the voltage adjusting module based on the delay chain, act on the computing array and the memory; when the computing array and the memory work under proper working voltage, the working performance of the circuit can be ensured, and the power consumption of the circuit can be reasonably controlled.

Technical Field

The invention relates to a delay chain-based array data scheduling balanced voltage adjusting circuit and method, and belongs to the field of artificial intelligence.

Background

In recent years, with the rise of artificial intelligence, a large number of multiply-add calculations and a large number of memory data read-write operations exist in an artificial intelligence chip. These add-multiply operations require reading and storing large amounts of data, which consumes a significant amount of power. If the operating voltages of the memory and the computing array are the same, the operating performance of the circuit is affected, unnecessary power consumption is generated, and therefore, an appropriate voltage is provided for reducing the power consumption.

The application provides an array data scheduling balanced voltage regulating circuit based on a delay chain and a method thereof, which can properly control the working voltages of a computational array and a memory to achieve the effects of meeting the performance and reducing the power consumption.

Disclosure of Invention

The invention aims to provide a voice feature extraction method and a reconfigurable voice feature extraction device in a multi-noise scene aiming at the defects of the background technology, which can dynamically select a voice feature extraction mode to reduce power consumption on the premise of keeping precision and solve the technical problems of low power consumption, low precision or high power consumption and high precision of the traditional voice endpoint detection module.

The invention adopts the following technical scheme for realizing the aim of the invention:

a delay chain-based array data scheduling balanced voltage regulating circuit and method are used for providing reasonable calculation array voltage and memory voltage by analyzing, evaluating and calculating the calculation scale of an array and the reading and writing scale of a memory; and after the given voltage value is verified, enabling signals with different frequencies are output through a delay chain, the bit number in the register is changed, and then the opening ratio columns of the PMOS and NMOS groups are changed, so that proper working voltage is obtained.

Further, in the array data scheduling balanced voltage adjusting method based on the delay chain, a data access and memory address relation is established for storing network data and convolution kernel scales, namely, the array calculation scale and the read-write scale of a memory are calculated.

Furthermore, in the array data scheduling balanced voltage adjusting method based on the delay chain, the thread _ func is started to be adjusted again, and whether the scale parameter in the network is effective or not is judged.

Furthermore, in the array data scheduling balanced voltage adjusting method based on the delay chain, the adjusting voltage is obtained after parameters in the network scale are analyzed, and whether the voltage needing to be adjusted is necessary or not is verified.

Furthermore, in the array data scheduling balanced voltage adjusting method based on the delay chain, the necessary voltage after judgment is transmitted to the voltage adjusting module based on the delay chain.

Further, in the array data scheduling balanced voltage adjusting method based on the delay chain, the array data scheduling balanced voltage adjusting and evaluating module outputs the calculated array voltage and the memory voltage output by the array data scheduling balanced voltage adjusting and evaluating module through different delay chains to output enable signals with different frequencies.

Furthermore, in the array data scheduling balanced voltage adjusting method based on the delay chain, because different delay chains output enable signals with different frequencies, the number of bits stored in the storage register is different.

Further, in the array data scheduling balanced voltage adjusting method based on the delay chain, registers store different bit numbers to influence the starting proportion of PMOS and NMOS groups; outputting a specified target voltage according to different starting proportions of the PMOS and the NMOS;

still further, in the delay chain-based array data scheduling balanced voltage adjusting method, a calculation array voltage and a memory voltage output by a voltage adjusting module based on a delay chain are applied to a calculation array and a memory. When the computing array and the memory work under proper working voltage, the working performance of the circuit can be ensured, and the power consumption of the circuit can be reasonably controlled.

The array data scheduling balanced voltage adjusting circuit based on the delay chain comprises:

and the calculation array and the memory are used for providing the calculation scale of the calculation array and the read-write scale of the memory, and the final proper working voltage is adopted.

The array data scheduling balance voltage regulation and evaluation module is used for analyzing, evaluating and calculating the calculation scale of the array and the read-write scale of the memory to obtain reasonable regulation voltage through a built-in algorithm, and ensuring that the regulated voltage is proper voltage through a series of verification methods.

The voltage regulating module based on the delay chain is used for regulating and evaluating the voltage value output by the array data scheduling balance voltage regulating and evaluating module through configuring the proper delay chain, and the frequencies of the enable signals output by different delay chains are different, so that the bit numbers stored in the registers are different under different enable signal frequencies, and the different bit numbers in the registers influence the starting proportion of the PMOS and NMOS groups. The voltage values output under different turn-on ratios of PMOS and NMOS are different, so that the proper voltage value can be output to a computing array and a memory for use.

By adopting the technical scheme, the invention has the following beneficial effects:

(1) aiming at different calculation scales, different voltages are adopted to improve the working performance of the calculation array, and compared with the situation of fixed voltage, the power consumption control method has the effect of controlling power consumption. If the computing array needs to process a large amount of computing operation, large voltage is adopted, and the working performance efficiency is improved; if the computational array needs to handle smaller computational operations, only a small voltage needs to be used, which can reduce the power consumption of the circuit.

(2) Aiming at different memory read-write scales, different voltages are adopted to improve the read-write efficiency of the memory, dynamically control the power consumption of the memory and meet the working performance required by the circuit.

(3) The working voltages of the computing array and the memory are dynamically matched to balance the computing and reading and writing rates. When more than read and write are calculated, the voltage of the calculation array is larger than that of the memory; when the read-write operation is larger than the calculation operand, the working voltage of the memory is higher than that of the calculation array.

Drawings

FIG. 1 is an overall architecture of the present invention.

FIG. 2 is a flow chart of voltage regulation determination according to the present invention.

Fig. 3 shows the delay chain regulation voltage of the present invention.

Fig. 4 is an overall work flow diagram of the present invention.

Detailed Description

The present invention is further illustrated by the following examples, which are intended to be purely exemplary and are not intended to limit the scope of the invention, as various equivalent modifications of the invention will occur to those skilled in the art upon reading the present disclosure and fall within the scope of the appended claims.

The array data scheduling balanced voltage adjusting circuit based on the delay chain gives out an appropriate adjusting voltage value through coordination control among built-in modules according to the calculation scale of the calculation array and the reading and writing scale of the storage. And the adjusting voltage value is adjusted by an adjusting voltage module based on a delay chain through a delay chain group, a register and a PMOS and NMOS group to output a proper voltage value to a computing array and a memory. Fig. 1 is an overall framework of the present invention.

The array data scheduling balance voltage regulation and evaluation module is used for analyzing, evaluating and calculating the calculation scale of the array and the read-write scale of the memory to obtain reasonable regulation voltage through a built-in algorithm, and ensuring that the regulated voltage is proper voltage through a series of verification methods. The specific voltage regulation judgment process is shown in fig. 2, and the array data scheduling balance voltage regulation evaluation module uses the created data access and storage address relation for storing network data and convolution kernel scale, namely calculating the array calculation scale and the read-write scale of the memory. And then starting to adjust the thread _ func and judging whether the scale parameter in the network is effective or not. And analyzing parameters in the network scale to obtain the regulated voltage, and verifying whether the voltage needing to be regulated is necessary. And transmitting the necessary voltage after judgment to a voltage regulation module based on the delay chain.

The voltage regulation module based on the delay chain, as shown in fig. 3, configures the appropriate delay chain for the voltage value output by the array data scheduling and balancing voltage regulation and evaluation module, and the frequencies of the enable signals output by different delay chains are different, so that the number of bits stored in the register is different under different frequencies of the enable signals, and the different number of bits in the register affects the turn-on ratio of the PMOS and NMOS groups. The voltage values output under different turn-on ratios of PMOS and NMOS are different, so that the proper voltage value can be output to a computing array and a memory for use.

Fig. 4 shows a circuit and a method for adjusting balanced voltage for scheduling array data based on a delay chain in this embodiment, which includes the following specific steps:

step 101: the array data scheduling balance voltage regulation and evaluation module reads the reading and writing scales of a calculation module of a calculation array and a memory, and the specific voltage regulation judgment process is as follows: creating a data access address relation for storing network data and convolution kernel scale; then starting to adjust the thread _ func, and judging whether the scale parameter in the network is effective and whether the voltage needing to be adjusted is necessary; transmitting the necessary voltage after judgment to a voltage regulation module based on a delay chain;

step 102: the array data scheduling balance voltage adjustment and evaluation module outputs the calculated array voltage and the memory voltage output by the delay chain-based adjustment voltage module through different delay chains to enable signals with different frequencies, and the number of bits stored in the register is different under the enable signals with different frequencies. Different bit numbers affect the starting proportion of the PMOS and NMOS groups; outputting unused voltage according to different turn-on proportions of PMOS and NMOS;

step 103: the voltage of the computing array and the voltage of the memory, which are output by the voltage adjusting module based on the delay chain, act on the computing array and the memory; when the computing array and the memory work under proper working voltage, the working performance of the circuit can be ensured, and the power consumption of the circuit can be reasonably controlled.