Split gate non-volatile floating gate flash memory based on two transistor fin field effect transistors and method of manufacturing the same
阅读说明:本技术 基于双晶体管鳍式场效晶体管的***栅极非易失性浮动栅极闪存存储器及其制造方法 (Split gate non-volatile floating gate flash memory based on two transistor fin field effect transistors and method of manufacturing the same ) 是由 S·乔尔巴 C·德科贝尔特 Z·冯 J·金 X·刘 N·多 于 2019-01-23 设计创作,主要内容包括:本发明公开了一种非易失性存储器单元,该非易失性存储器单元形成在半导体衬底上,该半导体衬底具有上表面,该上表面具有向上延伸的鳍片,该向上延伸的鳍片具有相对的第一侧表面和第二侧表面。第一电极和第二电极与该鳍片的第一部分和第二部分电气接触。该鳍片的沟道区包括在该鳍片的该第一部分和该第二部分之间延伸的该第一侧表面和该第二侧表面的部分。浮动栅极沿着该沟道区的该第一部分的该第一侧表面延伸,其中该浮动栅极中没有一个部分沿着该第二侧表面延伸。字线栅极沿着该沟道区的第二部分的该第一侧表面和该第二侧表面延伸。控制栅极设置在该浮动栅极上方。擦除栅极具有第一部分和第二部分,该第一部分与该浮动栅极横向相邻设置,该第二部分竖直地设置在该浮动栅极上方。(A non-volatile memory cell is formed on a semiconductor substrate having an upper surface with an upwardly extending fin having opposing first and second side surfaces. First and second electrodes are in electrical contact with the first and second portions of the fin. The channel region of the fin includes portions of the first side surface and the second side surface extending between the first portion and the second portion of the fin. Floating gates extend along the first side surface of the first portion of the channel region, wherein none of the floating gates extend along the second side surface. Word line gates extend along the first and second side surfaces of the second portion of the channel region. A control gate is disposed over the floating gate. The erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically above the floating gate.)
1. A non-volatile memory cell, comprising:
a semiconductor substrate having an upper surface with upwardly extending fins including first and second side surfaces opposite one another;
a first electrode in electrical contact with a first portion of the fin;
a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
a floating gate extending along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, and wherein no portion of the floating gate extends along the second side surface;
a word line gate extending along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
A control gate disposed over and insulated from the floating gate;
an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically above and insulated from the floating gate.
2. The non-volatile memory cell of claim 1, wherein no conductive gate is disposed along and insulated from a portion of the second side surface opposite a portion of the first side surface along which the floating gate extends.
3. The non-volatile memory cell of claim 1, wherein the word line gate comprises a metallic material, and wherein the word line gate is insulated from the first and second side surfaces by a high-K insulating material.
4. The non-volatile memory cell of claim 3, wherein the floating gate, the control gate, and the erase gate each comprise a polysilicon material.
5. The non-volatile memory cell of claim 4, wherein the first electrode and the second electrode each comprise a metallic material.
6. The non-volatile memory cell of claim 1, wherein the upper surface of the substrate comprises an upwardly extending second fin comprising a third side surface and a fourth side surface opposite one another, and wherein at least a portion of the floating gate is disposed between the fin and the second fin.
7. The non-volatile memory cell of claim 1, wherein the control gate and the erase gate are each disposed vertically above the fin.
8. The non-volatile memory cell of claim 1, wherein the first portion and the second portion of the fin each have a width that is greater than a width of the channel region of the fin.
9. The non-volatile memory cell of claim 1, wherein the first portion and the second portion of the fin each have a height that is greater than a height of the channel region of the fin.
10. The non-volatile memory cell of claim 1, wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.
11. The non-volatile memory cell of claim 1, wherein the floating gate has a rectangular vertical cross-section.
12. The non-volatile memory cell of claim 1, wherein the floating gate has a U-shaped vertical cross-section.
13. The non-volatile memory cell of claim 12, wherein the control gate comprises a lower portion that extends into the U-shaped vertical cross-section of the floating gate.
14. A method of forming a non-volatile memory cell, the method comprising:
forming a trench into an upper surface of a semiconductor substrate such that the upper surface includes an upwardly extending fin including first and second side surfaces opposite one another;
forming a first electrode in electrical contact with a first portion of the fin;
forming a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
Forming a floating gate extending along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, and wherein no portion of the floating gate extends along the second side surface;
forming a word line gate extending along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
forming a control gate disposed over and insulated from the floating gate;
an erase gate is formed having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically above and insulated from the floating gate.
15. The method of claim 14, wherein no conductive gate is disposed along and insulated from a portion of the second side surface opposite a portion of the first side surface along which the floating gate extends.
16. The method of claim 14, wherein the word line gate comprises a metallic material, and wherein the word line gate is insulated from the first and second side surfaces by a high-K insulating material.
17. The method of claim 14, wherein the floating gate, the control gate, and the erase gate each comprise a polysilicon material.
18. The method of claim 17, wherein the first electrode and the second electrode each comprise a metallic material.
19. The method of claim 14, wherein the upper surface of the substrate comprises upwardly extending second fins comprising third and fourth side surfaces opposite one another, and wherein at least a portion of the floating gate is disposed between the fins and the second fins.
20. The method of claim 14, wherein the control gate and the erase gate are each disposed vertically over the fin.
21. The method of claim 14, wherein the first portion and the second portion of the fin each have a width and a height that are greater than a width and a height, respectively, of the channel region of the fin.
22. The method of claim 14, wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.
23. The method of claim 14, wherein the floating gates have a rectangular vertical cross-section.
24. The method of claim 14, wherein the floating gate has a U-shaped vertical cross-section.
25. The method of claim 24, wherein the control gate includes a lower portion that extends into the U-shaped vertical cross section of the floating gate.
Technical Field
The invention relates to a non-volatile flash memory cell array.
Background
Non-volatile memory devices are well known in the art. For example, a split gate memory cell is disclosed in U.S. patent 5,029,130 (which is incorporated herein by reference for all purposes). The memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of a substrate extending between source and drain regions. Various combinations of voltages are applied to the control gate, source, and drain to program the memory cell (by injecting electrons into the floating gate), erase the memory cell (by removing electrons from the floating gate), and read the memory cell (by measuring or detecting the conductivity of the channel region under the floating gate to determine the programmed state of the floating gate).
The configuration and number of gates in the nonvolatile memory cells can vary. For example, U.S. patent 7,315,056 (which is incorporated herein by reference for all purposes) discloses a memory cell that additionally includes a program/erase gate over a source region. U.S. Pat. No. 7,868,375, which is incorporated herein by reference for all purposes, discloses a memory cell additionally including an erase gate over a source region and a coupling gate over a floating gate. See also U.S. Pat. nos. 6,747,310, 7,868,375, 9,276,005, and 9,276,006 (which are also incorporated herein by reference for all purposes).
Finfet-type structures have been proposed because the problem of shrinking the lithographic dimensions and thus the channel width affects all semiconductor devices. In a finfet-type structure, a fin-shaped member of semiconductor substrate material connects a source region to a drain region. The fin member has a top surface and two opposing side surfaces. Then, current from the source region to the drain region may flow along the top surface and both side surfaces. Thus, by "folding" the channel region into two side surfaces, the surface width of the channel region can be increased, thus increasing current without sacrificing more semiconductor real estate, thereby reducing the "footprint" of the channel region. Non-volatile memory cells using such finfet transistors have been disclosed. Some examples of prior art finfet non-volatile memory structures include us patents 7,423,310, 7,410,913, 8,461,640, and 9,634,018. However, these prior art finfet structures have disclosed using floating gates as stacked gate devices, or using trapping materials, or using SRO (silicon rich oxide) or using nano-crystalline silicon to store charge, or using other memory cell configurations that are too simple for memory cells with more than 2 gates or too complex for the number of gates in question.
The inventors have discovered a number of problems when scaling down the size of memory cells. Ultra-thin polysilicon or amorphous silicon film deposition and doping techniques are complex and often suffer from under-and non-uniform doping and structural non-uniformity. Ballistic electron transport in ultra-thin polysilicon floating gates causes programming problems (difficulty in trapping hot electrons in ultra-thin floating gates). The integration of the control gate on top of the floating gate results in a thick polysilicon stack that presents serious process integration challenges for advanced CMOS technology (CMP planarization step and subsequent advanced photolithography steps used in high-K metal gate process flows). The capacitive coupling between adjacent floating gates increases significantly with horizontal scaling. This leads to strong cross talk effects and requires complex management by design (the read current of a cell becomes dependent on the charge state of the neighboring cell). Scaling of flat floating gate memory cells is limited by the reduction in read current associated with transistor width scaling. Lower read currents impose penalties on access times and require complex design techniques to meet high access time specifications. The flat floating gate architecture does not allow for effective control of sub-threshold leakage of the floating gate and select transistor at advanced technology nodes, resulting in high background leakage from unselected cells sharing the same bit line as the selected cell.
Disclosure of Invention
The above problem is solved by a non-volatile memory cell comprising: a semiconductor substrate having an upper surface with upwardly extending fins including first and second side surfaces opposite one another; a first electrode in electrical contact with a first portion of the fin; a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin; a floating gate extending along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, and wherein no portion of the floating gate extends along the second side surface; a word line gate extending along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces; a control gate disposed over and insulated from the floating gate; and an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically above and insulated from the floating gate.
A method of forming a non-volatile memory cell, the method comprising: forming a trench into an upper surface of a semiconductor substrate such that the upper surface includes an upwardly extending fin including first and second side surfaces opposite one another; forming a first electrode in electrical contact with a first portion of the fin; forming a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin; and forming a floating gate extending along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein none of the floating gates extends partially along the second side surface; forming a word line gate extending along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces; forming a control gate disposed over and insulated from the floating gate; and forming an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically above and insulated from the floating gate.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
Drawings
Fig. 1A-19A are side cross-sectional views (along the row direction) showing steps of forming a split-gate non-volatile memory cell of the present invention.
Fig. 1B-19B are side cross-sectional views illustrating the logic region of the substrate during steps of forming the split-gate non-volatile memory cell of the present invention.
Fig. 5C-19C are side cross-sectional views (along the column direction) showing steps of forming the split-gate non-volatile memory cell of the present invention.
Fig. 5D is a plan view showing the direction of the views of fig. 5A and 5C.
Fig. 15D-19D are side cross-sectional views (along the column direction) showing steps of forming the split-gate non-volatile memory cell of the present invention.
Fig. 20A and 20B are partial perspective views of a split gate non-volatile memory cell of the present invention.
Fig. 21A-25A are side cross-sectional views (along the row direction) showing steps in forming an alternative embodiment of a split-gate non-volatile memory cell of the present invention.
Fig. 21B-25B are side cross-sectional views illustrating the logic region of the substrate during steps in forming an alternative embodiment of the split-gate non-volatile memory cell of the present invention.
Fig. 21C-25C are side cross-sectional views (along the column direction) showing steps to form an alternative embodiment of a split-gate non-volatile memory cell of the present invention.
Figure 25D is a side cross-sectional view (along the column direction) showing the final step in forming an alternative embodiment of the split-gate non-volatile memory cell of the present invention.
Fig. 26A is a side sectional view (along the column direction) showing the memory cell unit of the first embodiment.
Fig. 26B is a side sectional view (in the column direction) showing a memory cell unit of the second embodiment.
Fig. 27A is a top view showing a memory cell unit of the first embodiment.
Fig. 27B is a top view showing a memory cell unit of the second embodiment.
Detailed Description
The embodiments described below effectively address scaling issues specific to conventional split gate memories. In particular, the split-gate memory cell of the present invention includes two transistors that are compatible with the mainstream finfet CMOS fabrication flow. The two transistors are connected in series. Each transistor is formed on two adjacent silicon fins. The first transistor (referred to as a wordline or select transistor) has a finfet architecture in which an HKMG gate electrode wraps around one of the silicon fins. A second transistor, referred to as a floating gate transistor, has a polysilicon floating gate interposed between two silicon fins. The floating gate transistor operates in a fully depleted SOI-like mode in which the ultra-thin channel is electrically controlled by the floating gate on only one side of the silicon fin that serves as the channel. The floating gate transistor has a split gate architecture (separate control gate and erase gate), allowing for improved endurance and reliability. This architecture allows for efficient control of cell leakage (from both selected and unselected cells) while maintaining reasonable floating gate physical dimensions and addressing main memory cell scalability challenges (high-K metal gate integration, read current scaling, floating gate cross talk and isolation, and selected and unselected cell leakage control). There are two disclosed embodiments. The first embodiment is implemented using a box-shaped floating gate. The second implementation is implemented using U-shaped floating gates, allowing improved control gate coupling to the floating gates to improve programming efficiency.
The formation of the first embodiment is illustrated in fig. 1A-19A, 5C-19C, 5D, and 15D-19D (which depict the formation of memory cells in a memory region of a substrate) and 1B-19B (which depict the formation of logic devices in a peripheral region (also referred to as a logic region) of the same substrate). The process begins by forming a silicon dioxide (oxide)
An etch is performed to remove the exposed portions of the
One or more etches are performed to remove those portions of the
The
After the photoresist is removed, an
A photoresist is formed over the structure and patterned, leaving only photoresist strips in the memory areas. An etch is performed to remove the exposed portions of the hard mask 56, leaving strips of hard mask 56 extending in the row/horizontal direction. After photoresist removal, an oxide deposition and etch are performed to form oxide spacers 58 against the remaining hard mask material strips. A photoresist 60 is formed over the structure and patterned to cover only one of the spacers (for each memory cell) positioned over the
After the photoresist is removed, a SiCN etch is performed to remove the exposed portions of the
After photoresist removal, polysilicon etch and oxide etch are used to remove
Nitride is formed over the structure and then CMP planarized to cover the top of
Fig. 20A and 20B show perspective views of the final structure of a single memory cell having a floating gate transistor and a word line transistor formed along one of the
It should be understood that although the figures herein show a single memory cell, multiple memory cells are formed end-to-end along
The control gate is preferably n + type polysilicon (or amorphous silicon), covers a portion of the floating gate, and is isolated from the floating gate and the top of the fin by a dielectric (a silicon oxide-nitride-oxide stack or the like). The erase gate is preferably n + type polysilicon (or amorphous silicon) and overlies the remainder of the floating gate and is isolated from the floating gate by a tunnel oxide. On one side, the erase gate is isolated from the control gate by silicon oxide or by silicon oxide/nitride/oxide spacers. On the other side, the erase gate extends over the floating gate, forming a wrap-around corner shape (i.e., notch 48a) for erase operation by the efficient corner-improved fowler-nordheim tunneling mechanism. The word line gate is preferably a metal (including tungsten and/or a work function adjusting metal) covering a second portion of the finfet channel region on both side surfaces of the fin. The metal word line gate and the underlying fin portion form a word line transistor. The finfet architecture of the wordline transistors allows for improved control of sub-threshold leakage current from unselected cells sharing the same column, and improved high temperature read performance and associated memory partitioning.
The memory cell architecture allows for reasonable physical size of the floating gate, simplifies processing, and addresses problems associated with ballistic transport and ultra-thin polysilicon deposition processes. Furthermore, embedding at least some of the floating gates between fins solves the associated isolation and cross-talk issues while optimizing the gate stack topology for high-K metal gate integration and providing a way for further cell size scaling.
The formation of the second embodiment is illustrated in fig. 21A-25A, 21B-25B, 21C-25C, and 25D. The process starts with the same structure of fig. 5A to 5C. An oxide etch is performed to remove those portions of the
A photoresist is formed over the structure and patterned to leave exposed
It is to be understood that the present invention is not limited to the embodiments described above and shown herein, but encompasses any and all variations within the scope of any claims supported thereby. For example, reference to the invention herein is not intended to limit the scope of any claims or claim terms, but rather only to one or more features that may be covered by one or more claims. The above-described examples of materials, processes, and values are illustrative only and should not be construed as limiting any claim. For example, the floating gate may be formed of amorphous silicon instead of polysilicon. In addition, not all method steps need be performed in the exact order illustrated. Finally, a single layer of material may be formed as multiple layers of such or similar materials, or vice versa.
It should be noted that as used herein, the terms "above … …" and "above … …" both inclusively include "directly on … …" (with no intervening material, element, or space disposed therebetween) and "indirectly on … …" (with intervening material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space disposed therebetween) and "indirectly adjacent" (intermediate material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intermediate material, element, or space disposed therebetween) and "indirectly mounted to" (intermediate material, element, or space disposed therebetween), and "electrically connected to" includes "directly electrically connected to" (no intermediate material or element therebetween that electrically connects the elements together) and "indirectly electrically connected to" (intermediate material or element therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intervening materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials/elements therebetween.
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