阅读说明：本技术 高度缩放的线性GaN HEMT结构 (Highly scaled linear GaN HEMT structure ) 是由 文贞顺 安德里亚·科林 J·C·王 亚当·J·威廉姆斯 于 2018-12-12 设计创作，主要内容包括：一种晶体管包括衬底、耦合到衬底的沟道层、耦合到沟道层的源极、耦合到沟道层的漏极、以及在源极与漏极之间耦合到沟道层的栅极。栅极在靠近沟道层之处具有小于50纳米的长度尺寸,并且沟道层包括至少第一GaN层和在第一GaN层上的第一缓变AlGaN层。(A transistor includes a substrate, a channel layer coupled to the substrate, a source coupled to the channel layer, a drain coupled to the channel layer, and a gate coupled to the channel layer between the source and the drain. The gate has a length dimension of less than 50 nanometers proximate to the channel layer, and the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.)

1. A transistor, the transistor comprising:

a substrate;

a channel layer coupled to the substrate;

a source coupled to the channel layer;

a drain coupled to the channel layer; and

a gate coupled to the channel layer between the source and the drain;

wherein the gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

2. The transistor of claim 1 wherein the channel layer further comprises a recombination channel comprising:

the at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

A second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

3. The transistor of claim 2, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

4. The transistor of claim 1, further comprising:

an AlGaN barrier layer on the channel layer.

5. The transistor of claim 1, further comprising:

a back barrier layer between the substrate and the channel layer.

6. The transistor of claim 1 wherein the transistor is,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

7. A transistor, the transistor comprising:

a substrate;

a channel layer coupled to the substrate;

a source coupled to the channel layer;

a drain coupled to the channel layer;

a first gate coupled to the channel layer between the source and the drain; and

a second gate coupled to the channel layer between the first gate and the drain;

Wherein the first gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

8. The transistor of claim 7 wherein the channel layer further comprises a recombination channel comprising:

the at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

9. The transistor of claim 8, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

10. The transistor of claim 7, further comprising:

an AlGaN barrier layer on the channel layer.

11. The transistor of claim 7, further comprising:

a back barrier layer between the substrate and the channel layer.

12. The transistor of claim 7, wherein the transistor is,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

13. The transistor of claim 7, wherein the transistor is,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is a Direct Current (DC) gate for reducing Rds and Cgd nonlinearity.

14. A method of providing a transistor, the method comprising:

providing a substrate;

providing a channel layer coupled to the substrate;

providing a source coupled to the channel layer;

providing a drain coupled to the channel layer; and

providing a gate coupled to the channel layer between the source and the drain;

wherein the gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

15. The method of claim 14, further comprising:

providing a composite channel comprising:

the at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

A second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

16. The method of claim 15, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

17. The method of claim 14, further comprising:

an AlGaN barrier layer provided on the channel layer.

18. The method of claim 14, further comprising:

a back barrier layer provided between the substrate and the channel layer.

19. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

20. A method of providing a transistor, the method comprising:

providing a substrate;

providing a channel layer coupled to the substrate;

providing a source coupled to the channel layer;

providing a drain coupled to the channel layer;

providing a first gate coupled to the channel layer between the source and the drain; and

Providing a second gate coupled to the channel layer between the first gate and the drain;

wherein the first gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

21. The method of claim 20, further comprising:

providing a composite channel comprising:

the at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

22. The method of claim 21, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

23. The method of claim 20, further comprising:

an AlGaN barrier layer provided on the channel layer.

24. The method of claim 20, further comprising:

a back barrier layer provided between the substrate and the channel layer.

25. The method of claim 20, wherein the first and second portions are selected from the group consisting of,

Wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

26. The method of claim 20, wherein the first and second portions are selected from the group consisting of,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is a Direct Current (DC) gate for reducing Rds and Cgd nonlinearity.

[ technical field ] A method for producing a semiconductor device

The present disclosure relates to GaN High Electron Mobility Transistors (HEMTs).

[ background of the invention ]

In general, OIP3/P is intercepted in terms of the output third order _DCThe linearity figure of merit (LFOM) of the transistor. Most existing semiconductor technologies are limited to 10dB of LFOM. Exceptions include: LFOM is-50 dB doped channel GaAs MESFET as described in the following reference 1, which is incorporated herein by reference; LFOM is a 128dB graded channel GaAs MESFET after load matching as described in the following reference 2, which is incorporated herein by reference; and LFOM is a 41dB double (i.e., front and back) pulse doped InP HEMT, as described in the following reference 3, which is incorporated herein by reference. These LFOM improvements result from the transistor structure having a distributed doping profile, resulting in g_mAnd C_gsThe non-linearity of (a) is reduced. Unfortunately, these GaAs MESFETs have degraded channel mobility, transconductance, and noise figure, all of which limit their practical use in low noise and high linearity receiver applications. The double-pulse doped InP HEMT can provide high f at millimeter wave (mmW) frequencies_T/f_maxAnd low noise, but their LFOM's due to their low breakdown voltageRapidly degrading above-20 dBm power level. This degradation limits their use in receiver applications with high peak-to-average power ratios (e.g., 10.6 for Wideband Code Division Multiple Access (WCDMA), 12 for Orthogonal Frequency Division Multiplexing (OFDM) and in-band interference). Due to the non-linearity of transconductance and base-collector capacitance, LFOM in the highest HBT devices reported is-11 dB for GaAs HBTs, as described in the following reference 4, which is incorporated herein by reference. These HBT devices also typically have higher noise figure than HEMT devices. The reported LFOM for conventional GaN HEMTs as described in the following reference 5, incorporated by reference herein, GaN FINFETs as described in the following reference 6, incorporated by reference herein, and carbon nanotube FETs as described in the following reference 7, incorporated by reference herein, is less than 10 dB.

Recently, it has been reported that GaN FETs with graded AlGaN channels show promising linearization g at gate voltages_mBut no measured linearity data is reported and the reported device transconductance is low, 93mS/mm or 159mS/mm, as described in references 8 and 9, which are incorporated herein by reference below. These devices also have low mobility (524 cm)²/Vs)。

Most importantly, the channel temperature rises to 0.5I_dsThe best LFOM for prior art semiconductor technology is obtained nearby at-0.2I_dsThe best noise figure is obtained near the bias point. Therefore, the device linearity versus noise figure of prior art transistors is inevitably compromised.

A composite channel GaN HEMT is described in the following reference 10, incorporated herein by reference, and has been shown to improve the access resistance of a dual channel GaN heterostructure. However, the authors describe removing the top channel within the channel region while maintaining the double channel in the source and drain ohmic regions, which makes the active channel region of the device effectively the active channel region of a signal channel GaN HEMT.

[ REFERENCE ] to

The following references are hereby incorporated by reference as if fully set forth.

Chu, j.huang, w.struble, g.jackson, n.pan, m.j.schindler and y.tajima, "a highlyline MESFET", IEEE MTT-S Digest, 1991.

P.k.ikalainen, l.c.witkowski and k.r.varian, "Low noise, Low DC powerlinear FET", Microwave Conference, 1992.

Hur, k.y.hur, k.t.hetzler, r.a.mctaggart, d.w.vye, p.j.lemonias and w.e.hoke, "Ultralinear double pulsed AlInAs/GaInAs/InP HEMTs", Electronics Letters, volume 32, page 1516, 1996.

M.Iwamoto, P.M.Asbeck, T.S.Low, C.P.Hutchinson, J.B.Scott, A.Cognata, X.Qin, L.H.Camnitz and D.C.D' Avanzo, "Linear characteristics of GaAs HBTs and flame of collector design", IEEE Trans.microwave characteristics and technology, Vol.48, p.2377, 2000.

J. moon, m.micovic, a.kurdoghlian, r.janke, p.hashimoto, w. -S, Wong and l.mccray, "linear of low microwave noise AlGaN/GaN HEMTs", electronics letters, volume 38, page 1358, 2002.

K.Zhang, Y.Kong, G.Zhu, J.Zhou, X.Yu, C.Kong, Z.Li and T.Chen, "High-linearity AlGaN/GaN FinFETs for microwave power applications", IEEE electronic device Letters, Vol.38, p.615, 2017.

Y.Cao, G.J.Brady, H.Gui, C.rutherglen, M.S.Arnold and C.Zhou, "radio frequency transfer using aligned semiconductor manufacturing carbon n nanotubes with current-gain cut frequency and maximum oscillation frequency raw tissue reader which is 70GHz", ACS Nano, Vol.10, p.6782, 2016.

S. rajan et al, Applied Physics Letters, volume 84, page 1591, 2004.

P.park et al, Applied Physics Letters, volume 100, page 063507, 2012.

T.palacios et al, IEEE trans.electron Devices, vol 53, page 562, 2006.

J.S.Moon et al, IEEE Electron Dev.Lett.,37, 272-.

J. S. Moon et al, 2016IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR),5-7 (2016).

There is a need for an improved gan hemt having a high linearity quality factor (LFOM) with reduced spectral distortion, which is important to meet the demanding spectral efficiency requirements in wireless communications. Embodiments of the present disclosure meet these and other needs.

[ summary of the invention ]

In a first embodiment disclosed herein, a transistor includes a substrate, a channel layer coupled to the substrate, a source coupled to the channel layer, a drain coupled to the channel layer, and a gate coupled to the channel layer between the source and the drain, wherein the gate has a gate length dimension of less than 50 nanometers proximate to the channel layer, and wherein the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

In another embodiment disclosed herein, a transistor includes a substrate, a channel layer coupled to the substrate, a source coupled to the channel layer, a drain coupled to the channel layer, a first gate coupled to the channel layer between the source and the drain, and a second gate coupled to the channel layer between the first gate and the drain, wherein the first gate has a gate length dimension of less than 50 nanometers proximate to the channel layer, and wherein the channel layer includes at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

In yet another embodiment disclosed herein, a method of providing a transistor includes: providing a substrate; providing a channel layer coupled to a substrate; providing a source coupled to the channel layer; providing a drain coupled to the channel layer; and providing a gate coupled to the channel layer between the source and the drain, wherein the gate has a gate length dimension of less than 50 nanometers proximate to the channel layer, and wherein the channel layer comprises at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

In yet another embodiment disclosed herein, a method of providing a transistor includes: providing a substrate; providing a channel layer coupled to a substrate; providing a source coupled to the channel layer; providing a drain coupled to the channel layer; providing a first gate coupled to the channel layer between the source and the drain; and providing a second gate coupled to the channel layer between the first gate and the drain, wherein the first gate has a gate length dimension of less than 50 nanometers proximate to the channel layer, and wherein the channel layer comprises at least a first GaN layer and a first graded AlGaN layer on the first GaN layer.

These and other features and advantages will become more apparent from the following detailed description and the accompanying drawings. In the drawings and specification, reference numerals indicate various features, and like reference numerals refer to like features throughout the drawings and specification.

[ description of the drawings ]

Fig. 1A shows a scaled linear GaN HEMT structure according to the present disclosure having a dual-gate structure with a Radio Frequency (RF) gate and a Direct Current (DC) gate, and fig. 1B shows a scaled linear GaN HEMT structure according to the present disclosure having a single gate;

in accordance with the present disclosure, fig. 2A, 2B, 2C, 2D, 2E, 2F, and 2G illustrate a comparison of the structure and performance of a conventional GaN HEMT device, as illustrated in fig. 2A and 2B, and a graded-channel GaN HEMT structure, as illustrated in fig. 2C, 2D, and 2E, with fig. 2C, 2D, and 2E illustrating a greatly reduced G-voltage over a wide range of gate voltages compared to conventional GaN HEMT devices_mNon-linearity, and fig. 2F and 2G show the graded profile and thickness of the graded channel;

in accordance with the present disclosure, fig. 3A shows a graded and composite channel GaN HEMT structure, and fig. 3B and 3C show plots of carrier density versus depth and characteristics for a top channel, a bottom channel, and a double composite channel, respectively;

In accordance with the present disclosure, fig. 4A shows a SEM image of a fabricated double-gate GaN HEMT device having the structure depicted in fig. 1A with a 40nm RF gate length within 1.2 μm source-drain spacing for the X-band, fig. 4B shows measured S parameters of single and double gates showing Rds improvement and Cgd reduction, and fig. 4C shows calculated Rds for the disclosed device layout, given by the sum of Rds for a 40nm RF gate and Rds for a 150nm DC gate.

[ detailed description ] embodiments

In the following description, numerous specific details are set forth in order to provide a thorough description of various specific embodiments disclosed herein. However, it will be understood by those skilled in the art that the presently claimed invention may be practiced without all of the specific details discussed below. In other instances, well-known features have not been described in order not to obscure the invention.

The present disclosure describes GaN HEMT devices having a graded and/or composite channel structure and either a single gate structure or a dual gate structure on top of the channel structure. These GaN HEMT devices can also have very short gate lengths. These GaN HEMT devices have applications including linear amplifiers, such as power amplifiers and low noise amplifiers. The device of the present disclosure provides linear RF/MW/millimeter wave signal amplification with greatly reduced spectral distortion, which is important to meet the demanding spectral efficiency requirements in wireless communications.

The graded channel and composite channel structures of the present disclosure may achieve high LFOM at low current, receiver dependent bias conditions where the noise figure is optimized.

As described in references 8 and 9 above, a graded channel GaN FET structure has been shown to have linearization g over a range of gate voltages_m. However, their device transconductance is low, 93mS/mm and 159mS/mm, respectively, and their graded channel GaN heterostructures have about 524cm²Low mobility of/Vs. The present disclosure describes a graded channel GaN HEMT with optimized front and back barrier structures to maintain vertical scaling of the channel doping and mobility.

Also, as described in reference 10 above, the use of a dual channel GaN heterostructure has been used to improve the access resistance. In the described device embodiments, the top channel of the heterostructure is removed in the channel region of the active device while preserving the dual channel structure in the source and drain ohmic regions. Thus, the effective active channel region is the active channel region of a single-channel GaN HEMT. The present disclosure utilizes a dual-channel GaN heterostructure via g_mThe non-linearity cancellation improves linearity rather than access resistance.

In accordance with the present disclosure, fig. 1A shows a dual-gate linear GaN HEMT device with a channel layer 10 that is either a scaled graded channel layer or a graded and composite channel layer. The double gate device has an RF gate 12 and a DC gate 14 on top of the channel 10. The ohmic contacts 16 and 18 under the source and drain electrodes 20 and 22, respectively, may be regrown n + GaN as shown in figure 1A. The ohmic contacts 16 and 18 may have a thickness of 50nm, for example, as shown in FIG. 1A. For example, it may be Al _0.30Ga_0.70The barrier layer 24 of N may be located over an AlN layer 26 on the channel layer 10. May be Al_0.04Ga_0.96A back barrier layer 28 of N may be between the substrate 30 and the channel layer 10. The surface of the device may be passivated with a dielectric layer 32, which may be SiNx.

In accordance with the present disclosure, fig. 1B shows a single gate linear GaN HEMT device with a channel 10 that is either a scaled graded channel layer or a graded and composite channel layer. The single gate device has one RF gate 12 on top of the channel layer 10. The ohmic contacts 16 and 18 under the source and drain electrodes 20 and 22, respectively, may be regrown n + GaN as shown in figure 1B. For example, it may be Al_0.30Ga_0.70The barrier layer 24 of N may be located over an AlN layer 26 on the channel layer 10. May be Al_0.04Ga_0.96A back barrier layer 28 of N may be between the substrate 30 and the channel layer 10. The surface of the device may be passivated with a dielectric layer 32, which may be SiNx.

The GaN HEMT device disclosed in fig. 1A and 1B may utilize a scaled graded channel layer or graded and composite channel layer 10 and achieve linearity FOM (LFOM-OIP 3/P) by significantly scaling the dual-gate transistor architecture to very short gate lengths 13 in the case of fig. 1A_DC) The revolutionary progress of. With these key device innovations, the high linearity mmW GaN HEMT device of the present disclosure can simultaneously achieve improved OIP3/P that is difficult to achieve in prior art transistors _DCLow noise figure and high gain.

Key innovations shown in the GaN HEMT devices of fig. 1A and 1B include: epitaxial GaN HEMT channel structures, graded channel structures including polarization doping to control saturation velocity and charge distribution, these structures designed g_mDistribute and minimize g_mAnd C_gsNon-linearity without degrading channel mobility; multiple channels are vertically stacked into a composite channel GaN HEMT structure to further design g at low quiescent current density near the receiver bias point_mA degree of non-linearity; and vertically scaling the new graded composite channel structure to give a high g of greater than 700mS/mm_mThis is different from conventional MESFET structures.

The GaN HEMT device of fig. 1A and 1B has a laterally scaled gate structure that includes a short scaling length 13 of the RF gate 12 to improve noise figure and gain without Rds diffusion. The scaled gate 12 has a narrow portion of length 13, which may be only 40 to 50 nanometers, and is typically less than or equal to 50 nanometers. In addition, the GaN HEMT device of fig. 1A includes a DC gate 14 that forms a dual gate architecture to reduce Rds and Cgd non-linearities that can be a problem in short gate length devices.

Fig. 2A, 2B, 2C, 2D, and 2E show a comparison of the structure and performance of the conventional GaN HEMT device shown in fig. 2A and 2B with the structure and performance of the graded-channel GaN HEMT structure shown in fig. 2C, 2D, and 2E. The prior art device is optimized for high frequencies and has a maximum LFOM of 10dB with an Ids of about 700 mA/mm. The graded channel GaN HEMT structure of the present disclosure has significantly reduced g over a wide range of gate voltages compared to prior art GaN HEMT devices _mAnd (4) non-linearity. LFOM at about 450mA/mm I for the graded channel devices of the present disclosure_dsThe lower may have an LFOM greater than 20 dB.

Fig. 2C shows one embodiment of the structure of the GaN HEMT graded channel layer 10. The graded channel layer 10 shown in fig. 2C has an AlGaN graded channel layer 40 on a GaN layer 42, and the thickness of the GaN layer 42 may be 340 angstroms. The graded channel layer 40 may be Al with a thickness d_xGa_1-xAnd N is added. FIG. 2D shows for x_maxCharge density versus depth of 14% and d 60 angstroms or 6 nanometers. FIGS. 2F and 2G show the graded profile of the graded channelFor the thickness d. Al (Al)_xGa_1-xThe graded profile of the N graded channel layer 40 may vary from x-0 to x across the thickness d of the graded channel layer 40_max0.1 or may vary from x to x in the thickness d of the graded channel layer 40_max0.3. The thickness d of the graded channel layer 40 may be up to 60 angstroms or 6 nanometers or less than a maximum of 60 angstroms or 6 nanometers.

X may increase linearly with increasing thickness d, as shown in fig. 2F, or x may be proportional to the square root of d, as shown in fig. 2G. For example, x may be equal to 0.3 × d^1/2/(6nm)^1/2. These are Al_xGa_1-xA non-limiting example of a graded profile of the N graded channel layer 40.

For example, it may be Al_0.27Ga_0.73N or Al_0.3Ga_0.7The schottky barrier layer 24 of N may be above the graded channel layer 10 and may have a thickness of 90 angstroms. The AlN layer 26 may be between the schottky barrier layer 24 and the graded channel layer 10 and may be approximately 7 angstroms thick, as shown in fig. 2C.

For example, it may be Al_0.04Ga_0.96A back barrier 28 of N may be between GaN layer 42 and substrate 30 as shown in fig. 2C.

Such as show V_ddFig. 2E of modeled device performance for 3V, g_mFlat over a large bias range, with a relatively high peak g of 430mS/mm_m。g_mTo V_gsIs g_m”＝d²g_m/dV_gs ²G of_mNon-linearity, second derivative or curvature at V_gsnear-1.4V near zero as shown in fig. 2E.

Fig. 3A shows a GaN HEMT graded and composite channel GaN HEMT structure, while fig. 3B shows a graph of modeled GaN HEMT band structure. Fig. 3A shows a GaN HEMT with a graded and composite channel layer 10 comprising two graded channels 50 and 52 in a vertically stacked composite structure for optimizing low static I down to about 250mA/mm level_dsG is given below_mDegree of non-linearity (g)_m”＝d²g_m/dV_gs ²). The graded and composite channel layer 10 improves Noise Figure (NF) and LFOM by reducing Direct Current (DC) power consumption. The graded and composite channel 10 has two different superimposed threshold voltages (V)_th). G of the top graded channel 50_mG of bottom channel 52_mLinear superposition of (2) results in a low I_dsG around the level_mThe non-linearity is nearly cancelled as shown in fig. 3C. FIG. 3C shows g_mAt lower static I _dsLower and I_dsAll close to zero in range. By changing the g slowly_m"a plurality of slowly-varying channels are combined into a composite channel structure, and g can be expanded_mIs minimized to low V_gsAnd a range of static ids.

Al_0.3Ga_0.7The nbozter barrier layer 24 may be above the graded channel layer 50 and may, for example, have a thickness of approximately 80 to 90 angstroms. The AlN layer may be between the schottky barrier layer 24 and the graded channel layer 50 and may be approximately 7 angstroms thick, as shown in fig. 3A.

For example, it may be Al_0.04Ga_0.96A back barrier 28 of N may be between the GaN layer 62 and the substrate 30 as shown in fig. 3A.

Each of the graded channel layers 50 and 52 may have a composition similar to the graded channel 10 described above with respect to fig. 2C.

Having Al with a thickness of about 50 angstroms on an AlN layer with a thickness of about 7 angstroms_0.3Ga_0.7An N-layer Si-doped layer 53 may be located between the graded channel 50 and the graded channel 52. The purpose of the Si doped layer 53 between the graded channels 50 and 52 is to bring the conduction band below the fermi level so that electrons are available to the next graded channel. There may be multiple sets of graded channels, Si doped layers, and graded channels. Adjacent graded channels are preferably separated by a Si doped layer 53.

In fig. 3A, reference numerals 2, 3, and 4 at interfaces between the AlN layer 26 and the graded channel 50, between the graded portion 60 of the graded channel 50 and the GaN layer 62 of the graded channel 50, and between the graded channel 50 and the Si-doped layer 53, respectively, correspond to reference numerals 2, 3, and 4 shown in fig. 3B, which depicts carrier density versus device depth.

Fig. 4A shows an SEM image of a fabricated double-gate GaN HEMT device of the device of fig. 1A with a 40nm RF gate length within a 1.2 μm source-drain spacing for X-band operation. Fig. 4B shows the measured S parameters for a Single Gate (SG) device and a Double Gate (DG) device, showing the improvement in Rds and the reduction in Cgd. Fig. 4C shows the calculated Rds for the device layout, given by the sum of the Rds for the 40nm RF gate and the Rds for the 150nm DC gate. The dual-gate device shown in fig. 1A mitigates Rds and Cgd nonlinearity, especially in short gate length devices, and fig. 4C shows the Rds value for short gate length GaN devices. At V_ddUnder 3V, L_g40nm and L_gRds at 150nm was 15 ohm-mm and 35 ohm-mm, respectively. The Rds of a dual gate device is the sum of the Rds of the DC gate and the RF gate. Therefore, the total Rds is 50 ohm-millimeters, which is a desired design goal for Rds. By increasing the DC gate length, Rds can easily be further increased. The fabrication of a dual gate GaN HEMT device has been described in reference 11 above. As shown in fig. 4C, Rds can be increased from 15 ohm-mm for a 40nm single gate GaN HEMT to 50 ohm-mm for a dual gate GaN HEMT, and LFOM can be further enhanced by 2-3 dB.

Having now described the invention in accordance with the requirements of the patent statutes, those skilled in the art will understand how to make changes and modifications to the invention to meet the specific requirements or conditions thereof. Such changes and modifications can be made without departing from the scope and spirit of the present invention as disclosed herein.

For purposes of illustration and disclosure, the foregoing detailed description of exemplary and preferred embodiments has been presented as required by the law. It is not intended to be exhaustive or to limit the invention to the precise form described, but only to enable others skilled in the art to understand how the invention may be adapted for a particular use or embodiment. The possibilities of modifications and variations will be apparent to a person skilled in the art. The description of the exemplary embodiments is not intended to be limiting, and these embodiments may have included tolerances, feature sizes, specific operating conditions, engineering specifications, etc., and may vary from implementation to implementation or from prior art to prior art, and no limitation should be implied therefrom. The applicant has made this disclosure in relation to the current state of the art, but advances are also contemplated and future adaptations may take these into account, i.e. in accordance with the current state of the art at the time. It is intended that the scope of the invention be defined by the written claims and equivalents, if applicable. Reference to claim elements in the singular is not intended to mean "one and only one" unless explicitly so stated. Furthermore, no element, component, method, or process step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, method, or process step is explicitly recited in the claims. None of the elements of the claims herein are to be construed under the provisions of section six, section 112, of 35u.s.c. unless the element is specifically recited using a shorter than "means for … …", and none of the methods or process steps herein are to be construed under these provisions unless the step is specifically recited using the phrase "including step … …".

Concept

At least the following concepts are also presented herein:

concept 1. a transistor, comprising:

a substrate;

a channel layer coupled to a substrate;

a source coupled to the channel layer;

a drain coupled to the channel layer; and

a gate coupled to the channel layer between the source and the drain;

wherein the gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein, the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

Concept 2. the transistor according to concept 1, wherein the channel layer further comprises a recombination channel comprising:

at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

Concept 3. the transistor according to concept 2, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

Concept 4. the transistor according to concept 1, 2 or 3, further comprising:

an AlGaN barrier layer on the channel layer.

Concept 5. the transistor according to concept 1, 2, 3, or 4, further comprising:

A back barrier layer between the substrate and the channel layer.

Concept 6. transistors according to concept 1, 2, 3, 4 or 5,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer, or from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

The thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

Concept 7. a transistor, comprising:

a substrate;

a channel layer coupled to a substrate;

a source coupled to the channel layer;

a drain coupled to the channel layer;

a first gate coupled to the channel layer between the source and the drain; and

a second gate coupled to the channel layer between the first gate and the drain;

wherein the first gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein, the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

Concept 8 the transistor according to concept 7, wherein the channel layer further comprises a recombination channel comprising:

at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

A Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

Concept 9 the transistor according to concept 8, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

Concept 10. the transistor according to concept 7, 8 or 9, further comprising:

an AlGaN barrier layer on the channel layer.

Concept 11 the transistor according to concept 7, 8, 9, or 10, further comprising:

a back barrier layer between the substrate and the channel layer.

Concept 12. transistors according to concept 7, 8, 9, 10 or 11,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer, or from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

The thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

Concept 13, a transistor according to concept 7, 8, 9, 10, 11 or 12,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is for reducing R_dsAnd C_gdA non-linear Direct Current (DC) gate.

Concept 14 a method of providing a transistor, the method comprising:

providing a substrate;

providing a channel layer, the channel layer coupled to a substrate;

Providing a source coupled to the channel layer;

providing a drain coupled to the channel layer; and

providing a gate coupled to the channel layer between the source and the drain;

wherein the gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein, the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

Concept 15. the method according to concept 14, further comprising:

providing a composite channel, the composite channel comprising:

at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

a second graded AlGaN layer on the second GaN layer.

Concept 16 the method according to concept 15, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

Concept 17. the method according to concept 14, 15 or 16, further comprising:

an AlGaN barrier layer provided on the channel layer.

Concept 18. the method according to concept 14, 15, 16 or 17, further comprising:

a back barrier layer is provided between the substrate and the channel layer.

Concept 19. according to the method of concepts 14, 15, 16, 17 or 18,

wherein the first graded AlGaN layer includes Al _xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer, or from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

The thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

Concept 20 a method of providing a transistor, the method comprising:

providing a substrate;

providing a channel layer, the channel layer coupled to a substrate;

providing a source coupled to the channel layer;

providing a drain coupled to the channel layer;

providing a first gate coupled to the channel layer between the source and the drain; and

providing a second gate coupled to the channel layer between the first gate and the drain;

wherein the first gate has a gate length dimension of less than 50 nanometers proximate the channel layer; and is

Wherein, the channel layer includes:

at least a first GaN layer; and

a first graded AlGaN layer on the first GaN layer.

Concept 21. the method according to concept 20, further comprising:

providing a composite channel, the composite channel comprising:

at least a first GaN layer;

a first graded AlGaN layer on the first GaN layer;

a Si doped layer on the first graded AlGaN layer;

a second GaN layer on the Si doped layer; and

A second graded AlGaN layer on the second GaN layer.

Concept 22 the method according to concept 21, wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

Concept 23. the method according to concept 20, 21 or 22, further comprising:

an AlGaN barrier layer provided on the channel layer.

Concept 24. the method according to concept 20, 21, 22 or 23, further comprising:

a back barrier layer is provided between the substrate and the channel layer.

Concept 25. according to the method of concepts 20, 21, 22, 23 or 24,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer, or from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

The thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

Concept 26, the method according to concept 20, 21, 22, 23, 24 or 25,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is a Direct Current (DC) gate for reducing the Rds and Cgd non-linearity.

The claims (modification according to treaty clause 19)

1. A transistor, the transistor comprising:

a substrate;

a channel layer coupled to the substrate, the channel layer comprising a recombination channel comprising:

A first graded channel; and

a second graded channel on the first graded channel;

a source coupled to the channel layer;

a drain coupled to the channel layer; and

a first gate coupled to the channel layer between the source and the drain;

wherein the first graded channel has a first g_mA degree of non-linearity;

wherein the second graded channel has a length equal to the first g_mDifferent degree of non-linearitySecond g_mA degree of non-linearity; and is

Wherein g of the second graded channel_mG of the first graded channel_mIs linearly superposed on the I of the transistor_dsIn the range to almost cancel the g of the transistor_mAnd (4) non-linearity.

2. The transistor of claim 1,

the first graded channel includes:

a first GaN layer; and

a first graded AlGaN layer on the first GaN layer; and is

The second graded channel includes:

a second GaN layer; and

a second graded AlGaN layer on the second GaN layer.

3. The transistor of claim 2, further comprising:

a Si doped layer between the first graded channel and the second graded channel;

wherein the Si doped layer comprises:

An AlN layer; and

an AlGaN layer on the AlN layer.

4. The transistor of claim 1, further comprising:

an AlGaN barrier layer on the channel layer; and

a back barrier layer between the substrate and the channel layer.

5. The transistor of claim 1 wherein the transistor is,

wherein the first graded channel has a first threshold voltage; and is

Wherein the second graded channel has a second threshold voltage different from the first threshold voltage.

6. The transistor of claim 2 wherein the transistor is,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

7. The transistor of claim 4, wherein the AlGaN barrier layer comprises Al_0.30Ga_0.70N。

8. The transistor of claim 4 wherein the transistor is,

wherein the back barrier layer comprises Al_0.04Ga_0.96N。

9. The transistor of claim 1, further comprising:

a second gate coupled to the channel layer between the first gate and the drain.

10. The transistor of claim 9, further comprising:

An AlGaN barrier layer on the channel layer; and

a back barrier layer between the substrate and the channel layer.

11. The transistor of claim 1, wherein the first gate has a gate length dimension proximate the channel layer of less than 50 nanometers.

12. The transistor of claim 1 wherein the transistor is,

wherein a linearity figure of merit of the transistor is greater than 20 dB.

13. The transistor of claim 9, wherein the transistor is,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is a Direct Current (DC) gate for reducing Rds and Cgd nonlinearity.

14. A method of providing a transistor, the method comprising:

providing a substrate;

providing a channel layer coupled to the substrate, the channel layer comprising a recombination channel comprising:

a first graded channel; and

a second graded channel on the first graded channel;

providing a source coupled to the channel layer;

providing a drain coupled to the channel layer; and

providing a first gate coupled to the channel layer between the source and the drain;

wherein the first graded channel has a first g _mA degree of non-linearity;

wherein the second graded channel has a length equal to the first g_mSecond g with different non-linearity_mA degree of non-linearity; and is

Wherein g of the second graded channel_mThe g of the first graded channel_mIs linearly superposed on the I of the transistor_dsAlmost cancelling out g of the transistor in range_mAnd (4) non-linearity.

15. The method of claim 14, wherein,

the first graded channel includes:

a first GaN layer; and

a first graded AlGaN layer on the first GaN layer; and is

The second graded channel includes:

a second GaN layer; and

a second graded AlGaN layer on the second GaN layer.

16. The method of claim 15, further comprising:

a Si doped layer between the first graded channel and the second graded channel;

wherein the Si doped layer comprises:

an AlN layer; and

an AlGaN layer on the AlN layer.

17. The method of claim 14, further comprising:

an AlGaN barrier layer provided on the channel layer; and

a back barrier layer provided between the substrate and the channel layer.

18. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein the first graded channel has a first threshold voltage; and is

Wherein the second graded channel has a second threshold voltage different from the first threshold voltage.

19. The method of claim 15, wherein the first and second light sources are selected from the group consisting of,

wherein the first graded AlGaN layer includes Al_xGA_1-xN；

Wherein x varies from 0 to 0.1 over the thickness of the first graded AlGaN layer or varies from 0 to 0.3 over the thickness of the first graded AlGaN layer; and is

Wherein the thickness of the first graded AlGaN layer is 6 nanometers or less than 6 nanometers.

20. The method of claim 17, wherein the AlGaN barrier layer comprises Al_0.30Ga_0.70N。

21. The method of claim 17, wherein the back barrier comprises Al_0.04Ga_0.96N。

22. The method of claim 14, further comprising:

providing a second gate coupled to the channel layer between the first gate and the drain.

23. The method of claim 22, further comprising:

an AlGaN barrier layer provided on the channel layer; and

a back barrier layer provided between the substrate and the channel layer.

24. The method of claim 14, wherein,

the first gate has a gate length dimension of less than 50 nanometers proximate the channel layer.

25. The method of claim 14, wherein the first and second light sources are selected from the group consisting of,

wherein a linearity figure of merit of the transistor is greater than 20 dB.

26. The method of claim 22, wherein the first and second portions are selected from the group consisting of,

wherein the first gate is a Radio Frequency (RF) gate; and is

Wherein the second gate is a Direct Current (DC) gate for reducing Rds and Cgd nonlinearity.