Avalanche robustness LDMOS
阅读说明:本技术 雪崩鲁棒性ldmos (Avalanche robustness LDMOS ) 是由 S.L.涂 V.库什纳 E.范恩 于 2019-03-22 设计创作,主要内容包括:一种半导体设备包括形成在衬底上方的有源区。所述有源区包括FET和二极管。所述FET包括一个或多个FET指。每个FET指包括FET源极区、FET漏极区和横向FET栅极电极。所述二极管包括一个或多个二极管指。所述二极管指中的每一个包括电耦合到所述FET源极区的二极管阳极区、电耦合到所述FET漏极区的二极管阴极区以及电耦合到所述二极管阳极区并与所述横向FET栅极电极电隔离的横向二极管栅极电极。所述FET指为所述半导体设备的有源指,并且所述二极管指为所述半导体设备的虚设指。所述二极管被配置为钳位跨所述FET漏极区和所述FET源极区产生的最大电压。(A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage generated across the FET drain region and the FET source region.)
1. A semiconductor apparatus, comprising:
A substrate;
an active region comprising a FET and a diode formed over the substrate;
one or more FET fingers of the FET formed in the active region and having a FET source region, a FET drain region, and a lateral FET gate electrode; and
one or more diode fingers of the diode formed in the active region and having a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode;
wherein:
the one or more FET fingers of the FET are active fingers of the semiconductor device and the one or more diode fingers of the diode are dummy fingers of the semiconductor device; and is
The diode is configured to clamp a maximum voltage generated across the FET drain region and the FET source region.
2. The semiconductor device of claim 1, wherein:
a lateral distance between the lateral FET gate electrode and the FET drain region is greater than a lateral distance between the lateral diode gate electrode and the diode cathode region; and is
A target breakdown voltage of the diode is configured based on the lateral distance between the lateral diode gate electrode and the diode cathode region.
3. The semiconductor device of claim 1, further comprising:
a resistor electrically coupling the lateral diode gate electrode to the diode anode region.
4. The semiconductor device of claim 1, further comprising:
a FET shielding structure electrically coupled to the FET source region and laterally overlapping at least a portion of the lateral FET gate electrode; and
a diode shield structure electrically coupled to the diode anode region and laterally overlapping at least a portion of the lateral diode gate electrode.
5. The semiconductor device of claim 1, further comprising:
a FET shielding structure electrically coupled to the FET source region and laterally overlapping at least a portion of the lateral FET gate electrode; and
a truncated diode shield structure electrically coupled to the diode anode region and not laterally overlapping any portion of the lateral diode gate electrode.
6. The semiconductor device of claim 1, further comprising:
a buried electrical insulator layer between the substrate and the active region, the buried electrical insulator layer extending laterally under the one or more FET fingers and the one or more diode fingers.
7. The semiconductor device of claim 6, further comprising:
an electrical insulator barrier layer between the one or more FET fingers and the one or more diode fingers, the electrical insulator barrier layer extending from a top surface of the buried electrical insulator layer into the active region.
8. The semiconductor device of claim 1, wherein:
the semiconductor device has greater than or equal to ten active fingers for each diode finger that includes a diode.
9. The semiconductor device of claim 1, wherein:
the FET further comprises an FET body region and an FET buried well region;
the diode further comprises a diode body region and a diode buried well region;
the FET source region, the FET drain region, and the diode cathode region are of a first conductivity type; and is
The FET body region, the FET buried well region, the diode body region, the diode buried well region, and the diode anode region are of a second conductivity type.
10. The semiconductor device of claim 9, wherein:
the breakdown voltage of the diode is configured by the distance between the diode cathode region and the diode body region.
11. The semiconductor device of claim 9, wherein:
a lateral distance between the FET drain region and the lateral FET gate electrode is greater than a lateral distance between the diode cathode region and the lateral diode gate electrode.
12. The semiconductor device of claim 9, wherein:
the lateral distance between the FET drain region and the FET buried well region is greater than the lateral distance between the diode cathode region and the diode buried well region.
13. The semiconductor device of claim 9, wherein:
the doping depth, concentration and lateral extent of the FET drain region are substantially the same as the doping depth, concentration and lateral extent of the diode cathode region;
the doping depth, concentration and lateral extent of the FET body region are substantially the same as the doping depth, concentration and lateral extent of the diode body region;
the FET buried well region has a doping concentration substantially the same as the diode buried well region; and is
The doping depth, concentration and lateral extent of the FET source region are different from the doping depth, concentration and lateral extent of the diode anode region.
14. A semiconductor apparatus, comprising:
a substrate;
an active region formed over the substrate, the active region including one or more active fingers and one or more diode fingers, wherein:
each active finger comprises an active lateral gate electrode, a plurality of first active doped regions of a first conductivity type and one or more second active doped regions of a second conductivity type;
each diode finger comprises a diode lateral gate electrode, one or more first diode doped regions of the first conductivity type and one or more second diode doped regions of the second conductivity type;
each active finger includes a region more doped to the first conductivity type than the diode finger;
the active fingers include the same number of regions doped to the second conductivity type as the diode fingers;
the active lateral gate electrode is electrically isolated from the diode lateral gate electrode;
the diode lateral gate electrode is electrically coupled to a diode region in the second diode doping region;
The one or more diode fingers are dummy fingers of the semiconductor device; and is
The one or more diode fingers are configured to clamp a maximum voltage developed across two of the first active doped regions.
15. The semiconductor apparatus of claim 14, further comprising:
a resistor electrically coupling the diode lateral gate electrode to a diode doping region of the second diode doping region.
16. The semiconductor device of claim 14, wherein:
a first one of the first active doped regions is electrically coupled to a first one of the first diode doped regions; and is
A second one of the first active doped regions is electrically coupled to a second one of the second diode doped regions.
17. The semiconductor apparatus of claim 14, further comprising:
an active finger shield structure electrically coupled to an active dopant region of the first active dopant region and laterally overlapping at least a portion of the active lateral gate electrode; and
a truncated diode shield structure electrically coupled to the diode doping region of the second diode doping region and not laterally overlapping any portion of the diode lateral gate electrode.
18. A method for forming a semiconductor device, the method comprising:
providing a substrate;
forming an active region over the substrate, the active region comprising one or more active fingers and one or more diode fingers;
forming a FET within one or more of the active fingers, the FET having a FET source region, a FET drain region, and a lateral FET gate electrode;
forming a diode within one or more of the diode fingers, the diode having a diode anode region, a diode cathode region, and a lateral diode gate electrode;
electrically coupling the FET source region to the diode anode region;
electrically coupling the FET drain region to the diode cathode region; and
electrically coupling the lateral diode gate electrode to the diode anode region;
wherein:
the one or more diode fingers are dummy fingers of the semiconductor device;
the lateral FET gate electrode is electrically isolated from the lateral diode gate electrode; and is
The diode is configured to clamp a maximum voltage generated across the FET drain region and the FET source region.
19. The method of claim 18, further comprising:
electrically coupling the lateral diode gate electrode to the diode anode region using a resistor.
20. The method of claim 18, wherein:
the FET further comprises an FET body region and an FET buried well region;
the diode anode region further comprises a diode body region and a diode buried well region;
the FET source region, the FET drain region, and the diode cathode region are of a first conductivity type; and is
The FET body region, the FET buried well region, the diode body region, and the diode buried well region are of a second conductivity type.
21. The method of claim 20, wherein:
the doping depth, concentration and lateral extent of the FET drain region are substantially the same as the doping depth, concentration and lateral extent of the diode cathode region;
the doping depth, concentration and lateral extent of the FET body region are substantially the same as the doping depth, concentration and lateral extent of the diode body region;
the FET buried well region has a doping concentration substantially the same as the diode buried well region; and is
The doping depth, concentration and lateral extent of the FET source region are different from the doping depth, concentration and lateral extent of the diode anode region.
22. The method of claim 21, wherein:
the breakdown voltage of the diode is configured by the distance between the diode cathode region and the diode body region.
23. The method of claim 21, wherein:
a lateral distance between the FET drain region and the lateral FET gate electrode is greater than a lateral distance between the diode cathode region and the lateral diode gate electrode.
24. The method of claim 21, wherein:
the lateral distance between the FET drain region and the FET buried well region is greater than the lateral distance between the diode cathode region and the diode buried well region.
Background
Metal oxide field effect transistors (MOSFETs) generally include a gate electrode, a source region, a drain region, and a body region. The source and drain regions are of a first conductivity type and the body region is of a second conductivity type. In some MOSFET devices, the first conductivity type is n-type and the second conductivity type is p-type. In other MOSFET devices, this relationship is reversed. When the MOSFET device is in an on-state in response to an applied gate voltage, a channel region is formed in the body region under the gate and between the drain region and the source region. Current flows in the channel region. When the MOSFET device is in the off-state, the channel region is not present and thus current will not flow between the drain and source regions. However, if a reverse bias voltage exceeding the breakdown voltage is applied across the drain and source regions of the MOSFET, a large uncontrolled current flows between the source and drain regions regardless of whether a voltage is applied to the gate electrode. As the reverse bias voltage increases above the breakdown voltage, an avalanche breakdown event may occur. During an avalanche breakdown event, the current flowing through the MOSFET increases at an increased rate and may quickly exceed the maximum current rating of the MOSFET. Thus, the MOSFET is often damaged or destroyed completely.
Lateral diffusion MOSFETs (ldmos) are a type of MOSFET that additionally include a lateral Lightly Doped Drain (LDD) region to increase the breakdown voltage of the semiconductor device compared to that of a typical MOSFET. The LDD regions are of the same conductivity type as the body regions, but are doped to different concentrations. Although LDMOS devices may have increased breakdown voltages compared to MOSFETs, avalanche breakdown events may still occur if the reverse bias voltage exceeds the breakdown voltage of the LDMOS device.
Disclosure of Invention
In some embodiments, a semiconductor device includes a substrate and an active region. The active region includes a FET and a diode formed over the substrate. The FET includes one or more FET fingers formed in the active region, each FET finger having a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers formed in the active region, each diode finger having a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The one or more FET fingers of the FET are active fingers of the semiconductor device, and the one or more diode fingers of the diode are dummy fingers (dummyfinger) of the semiconductor device. The diode is configured to clamp a maximum voltage generated across the FET drain region and the FET source region.
In some embodiments, a semiconductor device includes a substrate and an active region formed over the substrate. The active region includes one or more active fingers and one or more diode fingers. Each active finger includes an active lateral gate electrode, two or more first active doped regions of a first conductivity type and one or more second active doped regions of a second conductivity type. Each diode finger includes a diode lateral gate electrode, one or more first diode doped regions of the first conductivity type, and one or more second diode doped regions of the second conductivity type. Each active finger includes a region more doped to the first conductivity type than the diode finger. The active fingers include the same number of regions doped to the second conductivity type as the diode fingers. The active lateral gate electrode is electrically isolated from the diode lateral gate electrode. The diode lateral gate electrode is electrically coupled to a diode region in the second diode doping region. The one or more diode fingers are dummy fingers of the semiconductor device. The one or more diode fingers are configured to clamp a maximum voltage developed across two of the first active doped regions.
In some implementations, a method for forming a semiconductor includes providing a substrate and forming an active region over the substrate. The active region includes one or more active fingers and one or more diode fingers. A FET is formed within one or more of the active fingers. The FET includes an FET source region, an FET drain region, and a lateral FET gate electrode. A diode is formed within one or more of the diode fingers. The diode includes a diode anode region, a diode cathode region, and a lateral diode gate electrode. The FET source region is electrically coupled to the diode anode region. The FET drain region is electrically coupled to the diode cathode region. The lateral diode gate electrode is laterally coupled to the diode anode region. The one or more diode fingers are dummy fingers of the semiconductor device. The lateral FET gate electrode is electrically isolated from the lateral diode gate electrode. The diode is configured to clamp a maximum voltage generated across the FET drain region and the FET source region.
Drawings
Fig. 1 is a simplified elevation view of a portion of a prior art multi-fingered semiconductor device.
Fig. 2 is a simplified elevation view of a portion of a multi-fingered semiconductor device according to some embodiments.
Fig. 3 is a simplified cross-sectional view of an exemplary LDMOS structure in an active finger of a multi-finger semiconductor device according to some embodiments.
Fig. 4-6 are simplified cross-sectional views of exemplary diode structures in dummy fingers of a multi-finger semiconductor device according to some embodiments.
Fig. 7-9 are simplified cross-sectional views of a multi-fingered semiconductor device according to some embodiments.
Fig. 10A-10B are graphs of exemplary experimental results measured using exemplary embodiments disclosed herein.
Detailed Description
Avalanche breakdown may occur in an LDMOS device when the reverse bias voltage generated across the source and drain regions of the LDMOS exceeds the breakdown voltage level of the LDMOS device. When avalanche breakdown occurs, the LDMOS may be damaged or destroyed. One approach to mitigate the risk of avalanche breakdown events is to implement a reverse biased diode in parallel with the LDMOS device. In such embodiments, the cathode region of the diode is electrically coupled to the drain region of the LDMOS device and the anode region of the diode is electrically coupled to the source region of the LDMOS device. The diode is configured to have a target (e.g., desired) diode breakdown voltage level that is less than the breakdown voltage that would cause an avalanche breakdown event to occur in the LDMOS device. The diode conducts a substantial amount of current when the reverse bias voltage exceeds the breakdown voltage of the diode. This current flow reduces or eliminates the reverse bias voltage across the LDMOS device. The LDMOS is prevented from an avalanche breakdown event due to the reduction or elimination of the reverse bias voltage across the LDMOS.
In the exemplary embodiments and methods described herein, it may be advantageous for one or more diodes to be monolithically integrated with one or more LDMOS devices on a common substrate of a semiconductor device. A semiconductor device includes one or more active fingers and one or more dummy fingers (dummy fingers are sometimes also referred to as termination fingers). In some embodiments, a dummy finger is a finger of the multi-finger semiconductor device adjacent to a termination perimeter (e.g., outer perimeter) of the semiconductor device. In some embodiments, there are a plurality of fingers near a termination perimeter of the semiconductor device, the plurality of fingers configured as dummy fingers. In some implementations, a dummy finger is a finger of a multi-finger semiconductor device whose control node (e.g., gate electrode) is not electrically coupled to a corresponding control node (e.g., gate electrode) of an active finger of the semiconductor device. In some embodiments, the LDMOS device is formed within one or more of the active fingers and the diode is formed within one or more of the dummy fingers. The diodes are electrically coupled in parallel with an LDMOS device formed in one or more active fingers of the semiconductor device. One or more diodes formed in the dummy finger are configured to have a breakdown voltage level that is lower than a reverse bias voltage level that would trigger an avalanche event in the LDMOS formed in the active finger. Therefore, it is advantageous to reuse the area of the semiconductor that is normally wasted by the dummy fingers as one or more diodes to extend and protect the lifetime of the LDMOS formed in the active fingers. In addition, since the dummy fingers are similar to the active fingers, the process flow for manufacturing the semiconductor device is advantageously simplified as compared to the process flow for monolithically integrating dissimilar semiconductor devices.
Fig. 1 shows a simplified prior art front view of a multi-fingered semiconductor device 100. Semiconductor device 100 generally includes two or more active fingers 102 and two or more dummy fingers 104. LDMOS devices are formed in the active fingers 102, as alternating source regions S2-3And a gate electrode G2-4And a drain region D2-3As shown. A metallization layer (not shown) may be used to electrically couple corresponding regions of the active fingers 102 together, as schematically illustrated. For example, the metallization layer may connect the gate electrodes G of the active fingers 1022-4Are electrically coupled together; another metallization layer may connect the source regions S of the active fingers 1022-3Are electrically coupled together; and so on. Dummy fingers 104 are generally positioned near an outer periphery of semiconductor device 100 to minimize the outer peripheral effect of the process flow for forming semiconductor device 100. Dummy finger 104 includes alternating source regions S1-nAnd a gate electrode G1-nAnd a drain region D1-nThey are similar to the corresponding regions of the active fingers 102 with some exceptions. For example, a region of dummy finger 104 may not be electrically coupled to a corresponding region (e.g., G) within active finger 1021Usually with G2Electrically isolated).
Fig. 2 illustrates a simplified front view of a
LDMOS devices are formed in the
One or more regions of
As shown, the surface area of
Fig. 3 is a simplified cross-sectional view of an
When a sufficient gate voltage is applied to the
Fig. 4 is a simplified cross-sectional view of an exemplary diode 404 formed in
Active region 414 generally includes a region of the first conductivity type and a region of the second conductivity type in accordance with respective ones of
The target breakdown voltage of the diode 404 (e.g., a desired breakdown voltage selected at design time) is configured to be less than the breakdown voltage of the
In some embodiments, the gate electrode 428 is electrically shorted to the anode contact region 423 by a metal. Electrically shorting gate electrode 428 to anode contact region 423 advantageously prevents the formation of a conductive channel in diode 404, thereby reducing leakage current at high frequency operation of the semiconductor device. In other embodiments, resistor 444 couples gate electrode 428 to anode contact region 423. During an electrostatic discharge event, transient current flow through resistor 444 will cause a voltage drop that inverts the region under gate electrode 428 and forms a conductive channel. By coupling gate electrode 428 to anode contact region 423 through resistor 444, the trigger voltage of diode 404 is advantageously reduced as compared to embodiments of diode 404 in which gate electrode 428 is electrically shorted to anode contact region 423. In addition, avalanche robustness of the diode 404 is advantageously improved because the conductive channel is formed by inversion.
As previously described, the diode 404 is electrically coupled in parallel to the
Fig. 5 is a simplified cross-sectional view of an
Fig. 6 is a simplified cross-sectional view of an
Fig. 7 illustrates a simplified front view of a multi-fingered semiconductor device 700 according to some embodiments. Semiconductor device 700 generally includes a substrate 710, a buried insulator layer 712, and an active region 714. Active region 714 generally includes one or more active fingers 702 and one or more dummy fingers 704. As shown, a protection diode is formed in dummy finger 704 and an LDMOS device is formed in active finger 702. In the implementation shown, an insulating barrier 746 electrically isolates the active fingers 702 from the dummy fingers 704. In some implementations, the insulator barrier region 746 is a Shallow Trench Isolation (STI) region. In other embodiments, the insulator barrier region is a deep trench isolation region (DTI). An electrical connection in a third dimension, schematically shown with a dashed line 762, electrically couples the cathode region (C) of the diode to the drain region (D) of the LDMOS device, and an electrical connection in a third dimension, schematically shown with a dashed line 764, electrically couples the anode region (a) of the diode to the source region (S) of the LDMOS device.
Fig. 8 illustrates a simplified front view of a multi-fingered semiconductor device 800 according to some embodiments. The semiconductor device 800 generally includes a substrate 810, a buried insulator layer 812, and an active region 814. The active area 814 generally includes one or more active fingers 802 and one or more dummy fingers 804. As shown, a protection diode is formed in dummy finger 804 and an LDMOS device is formed in active finger 802. In the embodiment shown, the insulating barrier region 846 electrically isolates adjacent LDMOS devices formed in the active fingers 802, as well as electrically isolates the active fingers 802 from the dummy fingers 804. An electrical connection in a third dimension, schematically shown with dashed line 862, couples the cathode region (C) of the diode to the drain region (D) of the LDMOS device, and an electrical connection in a third dimension, schematically shown with dashed line 864, electrically couples the anode region (a) of the diode to the source region (S) of the LDMOS device.
Fig. 9 illustrates a simplified front view of a multi-fingered semiconductor device 900 according to some embodiments. Semiconductor device 900 generally includes a substrate 910, a buried insulator layer 912, and an active region 914. The active area 914 generally includes one or more active fingers 902 interleaved with one or more dummy fingers 904. As shown, a protection diode is formed in dummy finger 904 and an LDMOS device is formed in active finger 902. In the embodiment shown, insulating barrier region 946 electrically isolates an LDMOS device formed in active finger 802 from an adjacent diode formed in dummy finger 904. An electrical connection in a third dimension, schematically shown with dashed line 962, couples the cathode region (C) of the diode to the drain region (D) of the LDMOS device, and an electrical connection in a third dimension, schematically shown with dashed line 964, electrically couples the anode region (a) of the diode to the source region (S) of the LDMOS device.
Fig. 10A-10B are simplified
Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example has been provided by way of explanation of the present technology, and not limitation of the present technology. Indeed, while the present disclosure has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment, can be used with another embodiment to yield a still further embodiment. It is therefore intended that the present subject matter cover all such modifications and variations as come within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.
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