阅读说明：本技术 显示装置 (Display device ) 是由 金建佑 金得钟 李东炫 崔德永 于 2020-04-28 设计创作，主要内容包括：提供了一种显示装置。所述显示装置包括第一信号线和第二信号线、第一信号垫和第二信号垫以及与第一信号线和第二信号线叠置的垫绝缘层。第一信号垫包括中间导电图案和上导电图案,中间导电图案与第一信号线的端部部分叠置并且连接到第一信号线的端部部分,上导电图案位于中间导电图案上,上导电图案穿过垫绝缘层被暴露。中间导电图案包括第一部分和第二部分,第一部分与第一信号线的端部部分叠置,第二部分位于第一信号线的端部部分与第二信号线的端部部分之间且从第一部分延伸。上导电图案连接到中间导电图案的第二部分。(A display device is provided. The display device includes first and second signal lines, first and second signal pads, and a pad insulating layer overlapping the first and second signal lines. The first signal pad includes a middle conductive pattern overlapping and connected to an end portion of the first signal line, and an upper conductive pattern on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion overlapping the end portion of the first signal line and a second portion located between the end portion of the first signal line and the end portion of the second signal line and extending from the first portion. The upper conductive pattern is connected to the second portion of the middle conductive pattern.)

1. A display device, the display device comprising:

a substrate layer;

a plurality of electronic components on the base layer;

a plurality of signal lines electrically connected to the plurality of electronic components;

a plurality of signal pads, each of the plurality of signal pads connected to a corresponding signal line among the plurality of signal lines; and

an insulating layer is disposed on the pad and has a first insulating layer,

wherein each of the plurality of signal pads comprises: a first conductive pattern overlapping and contacting an end portion of the corresponding signal line; a second conductive pattern on the first conductive pattern, the second conductive pattern overlapping and contacting the first conductive pattern; and a third conductive pattern on the second conductive pattern, the third conductive pattern overlapping and contacting the second conductive pattern,

wherein one of the first conductive pattern and the second conductive pattern comprises: a first portion overlapping the end portion of the corresponding signal line; and a second portion located between the end portion of the corresponding signal line and an end portion of another signal line adjacent to the corresponding signal line among the plurality of signal lines, the second portion extending from the first portion, and

wherein:

the pad insulating layer overlaps the plurality of electronic elements, the plurality of signal lines, and the first conductive pattern;

the pad insulating layer has a pad contact hole exposing at least a portion of the second conductive pattern; and is

The third conductive pattern is connected to the second conductive pattern through the pad contact hole.

2. The display device according to claim 1, wherein the third conductive pattern is positioned within the pad contact hole in a plan view.

3. The display device according to claim 1, further comprising:

a first insulating layer on the end portion of the corresponding signal line; and

a second insulating layer on the first conductive pattern,

wherein:

the first insulating layer has a first contact hole exposing the end portion of the corresponding signal line;

the first conductive pattern is connected to the end portion of the corresponding signal line through the first contact hole;

the second insulating layer has a second contact hole exposing the first conductive pattern; and is

The second conductive pattern is connected to the first conductive pattern through the second contact hole.

4. The display device according to claim 3, wherein the first conductive pattern includes the first portion and the second portion, and

the second contact hole overlaps the second portion of the first conductive pattern in a plan view.

5. The display device according to claim 3, wherein:

the second conductive pattern includes the first portion and the second portion;

the second contact hole overlaps the first portion of the second conductive pattern and the first conductive pattern in a plan view; and is

The pad contact hole overlaps the second portion of the second conductive pattern.

6. The display device according to claim 1, further comprising:

a first insulating layer;

a second insulating layer;

a third insulating layer; and

a fourth insulating layer formed on the first insulating layer,

wherein:

each of the first, second, third, and fourth insulating layers is positioned under the pad insulating layer,

the plurality of electronic elements include an upper electrode, a transistor, and a light emitting element connected to the transistor,

the transistor includes an active region, a gate on the active region, a source extending from one side of the active region, and a drain extending from the other side of the active region,

the first insulating layer covers the active region, the source electrode and the drain electrode,

the second insulating layer is located on the first insulating layer and covers the gate,

the third insulating layer is on the second insulating layer and covers the upper electrode, and

the fourth insulating layer covers the third insulating layer.

7. The display device according to claim 6, wherein the end portion is located in the same layer as that of the gate electrode or the upper electrode.

8. The display device according to claim 6, wherein the first conductive pattern is on the third insulating layer, and the second conductive pattern is on the fourth insulating layer.

9. The display device of claim 6, wherein the pad insulating layer comprises an organic layer comprising: a first portion located between the end portion of the corresponding signal line and the end portion of the other signal line; and a second portion overlapping the transistor and

wherein a thickness of the first portion of the organic layer is in a range from 45% to 55% of a thickness of the second portion of the organic layer.

10. The display device according to claim 6, wherein each of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer comprises an inorganic layer, and wherein

Wherein the pad insulating layer includes an organic layer.

11. The display device of claim 1, further comprising a thin film encapsulation layer and an input sensor,

wherein:

the plurality of electronic elements include light emitting elements;

the thin film packaging layer is positioned on the pad insulating layer and covers the light-emitting element; and is

The input sensor is located on the thin film encapsulation layer, and the input sensor comprises a sensing electrode.

12. The display device according to claim 11, wherein the plurality of signal lines include a first signal line connected to the light-emitting element and a second signal line connected to the sense electrode.

13. The display device according to claim 1, wherein the plurality of signal lines include a plurality of portions on different layers.

14. The display device according to claim 1, wherein:

the plurality of signal pads includes a first signal pad and a second signal pad;

the first signal pads form a first pad row;

the second signal pads form a second pad row different from the first pad row; and is

The second signal pads are in a staggered arrangement relative to the first signal pads.

15. The display device of claim 14, wherein the second signal pad is closer to an edge of the substrate layer than the first signal pad, and

a signal line connected to one of the second signal pads among the plurality of signal lines overlaps the second portion of the corresponding first signal pad among the first signal pads.

16. The display device according to claim 14, wherein an end portion of a signal line connected to one of the second signal pads among the plurality of signal lines is located on a layer different from a layer where an end portion of a signal line connected to one of the first signal pads among the plurality of signal lines is located.

17. The display device according to claim 1, further comprising:

a circuit board electrically connected to the plurality of signal pads; and

an anisotropic conductive film configured to bond the plurality of signal pads to the circuit board.

18. A display device, the display device comprising:

a first signal line;

a second signal line;

a first signal pad connected to the first signal line;

a second signal pad connected to the second signal line; and

a pad insulating layer overlapping the first signal line and the second signal line,

wherein the first signal pad includes:

an intermediate conductive pattern overlapping an end portion of the first signal line, the intermediate conductive pattern being connected to the end portion of the first signal line; and

an upper conductive pattern on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer,

wherein the intermediate conductive pattern includes a first portion overlapping the end portion of the first signal line and a second portion between the end portion of the first signal line and an end portion of the second signal line, the second portion extending from the first portion, and

wherein the upper conductive pattern is connected to the second portion of the middle conductive pattern.

19. The display device according to claim 18, wherein the upper conductive pattern does not overlap each of the end portion of the first signal line and the end portion of the second signal line.

20. A display device, the display device comprising:

a substrate layer including a display region and a non-display region;

a first switching transistor on the display area;

a second switching transistor on the display area;

a first signal line connected to the first switching transistor;

a second signal line connected to the second switching transistor;

a first signal pad connected to the first signal line;

a second signal pad connected to the second signal line; and

a pad insulating layer overlapping the first switching transistor, the second switching transistor, the first signal line, and the second signal line,

wherein each of the first and second signal pads includes:

an intermediate conductive pattern overlapping an end portion of a corresponding signal line among the first and second signal lines, the intermediate conductive pattern being electrically connected to the end portion of the corresponding signal line; and

an upper conductive pattern on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer,

wherein the pad insulating layer has a pad contact hole exposing a portion of the intermediate conductive pattern, the pad contact hole overlapping the end portion of the corresponding signal line, and

wherein the upper conductive pattern is connected to the intermediate conductive pattern through the pad contact hole, and the upper conductive pattern is positioned within the pad contact hole in a plan view.

21. The display device of claim 20, wherein the pad insulating layer comprises an organic layer comprising: a first portion between the first signal pad and the second signal pad; and a second portion overlapping with the first switching transistor and

wherein a thickness of the first portion of the organic layer is in a range from 60% to 80% of a thickness of the second portion of the organic layer.

22. The display device of claim 20, wherein the pad insulating layer comprises a first organic layer, at least one inorganic layer on the first organic layer, and a second organic layer on the at least one inorganic layer,

wherein the first organic layer comprises: a first portion between the first signal pad and the second signal pad; and a second portion overlapping with the first switching transistor and

wherein a thickness of the first portion of the first organic layer is in a range from 45% to 55% of a thickness of the second portion of the first organic layer.

23. The display device according to claim 20, wherein the pad insulating layer comprises at least one inorganic layer and an organic layer on the at least one inorganic layer, and

wherein an upper surface of a portion of the organic layer between the first and second signal pads is higher than an uppermost end portion of the upper conductive pattern.

Technical Field

An aspect of one or more exemplary embodiments of the present disclosure relates to a display device. One or more exemplary embodiments of the present disclosure relate to a pad area of a display device.

Background

Various display devices for multimedia devices such as televisions, mobile phones, tablet computers, navigation devices, and game devices are being developed. The display device includes a keyboard or a mouse as an input device. In addition, the display device includes an input sensor such as a touch panel as an input device.

The display device includes a display panel and a circuit board. The display panel is connected to the main board via a circuit board.

The above information disclosed in this background section is for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not form the prior art.

Disclosure of Invention

One or more exemplary embodiments of the present disclosure are directed to a display device including a signal pad having reduced defects.

According to one or more exemplary embodiments, a display device includes: a substrate layer; a plurality of electronic components on the base layer; a plurality of signal lines electrically connected to the electronic components; a plurality of signal pads, each signal pad connected to a corresponding signal line among the plurality of signal lines; and a pad insulating layer. Each signal pad includes: a first conductive pattern overlapping and contacting an end portion of the corresponding signal line; a second conductive pattern on the first conductive pattern, the second conductive pattern overlapping and contacting the first conductive pattern; and a third conductive pattern on the second conductive pattern, the third conductive pattern overlapping and contacting the second conductive pattern. One of the first conductive pattern and the second conductive pattern includes: a first portion overlapping with an end portion of the corresponding signal line; and a second portion located between an end portion of the corresponding signal line and an end portion of another signal line adjacent to the corresponding signal line among the signal lines, the second portion extending from the first portion. The pad insulating layer overlaps the electronic element, the signal line, and the first conductive pattern, and has a pad contact hole exposing at least a portion of the second conductive pattern. The third conductive pattern is connected to the second conductive pattern through the pad contact hole.

In an exemplary embodiment, the third conductive pattern may be positioned within the pad contact hole in a plan view.

In an exemplary embodiment, the display device may further include: a first insulating layer on end portions of the corresponding signal lines; and a second insulating layer on the first conductive pattern. The first insulating layer may have first contact holes exposing end portions of the corresponding signal lines; the first conductive pattern may be connected to an end portion of the corresponding signal line through the first contact hole; the second insulating layer may have a second contact hole exposing the first conductive pattern; and the second conductive pattern may be connected to the first conductive pattern through the second contact hole.

In an exemplary embodiment, the first conductive pattern may include a first portion and a second portion, and the second contact hole may overlap the second portion of the first conductive pattern in a plan view.

In an exemplary embodiment, the second conductive pattern may include a first portion and a second portion; the second contact hole may overlap the first portion of the second conductive pattern and the first conductive pattern in a plan view; and the pad contact hole may overlap with the second portion of the second conductive pattern.

In an exemplary embodiment, the display device may further include: a first insulating layer; a second insulating layer; a third insulating layer; and a fourth insulating layer. Each of the first, second, third, and fourth insulating layers may be positioned under the pad insulating layer, the plurality of electronic elements may include an upper electrode, a transistor, and a light emitting element connected to the transistor, the transistor may include an active region, a gate electrode positioned on the active region, a source electrode extending from one side of the active region, and a drain electrode extending from the other side of the active region, the first insulating layer may cover the active region, the source electrode, and the drain electrode, the second insulating layer may be positioned on the first insulating layer and may cover the gate electrode, the third insulating layer may be positioned on the second insulating layer and may cover the upper electrode, and the fourth insulating layer may cover the third insulating layer.

In an exemplary embodiment, the end portion may be located in the same layer as that of the gate or the upper electrode.

In an exemplary embodiment, the first conductive pattern is on the third insulating layer, and the second conductive pattern is on the fourth insulating layer.

In an exemplary embodiment, the pad insulating layer may include an organic layer including a first portion between the end portion of the corresponding signal line and the end portion of the other signal line and a second portion overlapping the transistor, and a thickness of the first portion of the organic layer may be in a range from about 45% to about 55% of a thickness of the second portion of the organic layer.

In an exemplary embodiment, each of the first, second, third, and fourth insulating layers may include an inorganic layer, and the pad insulating layer may include an organic layer.

In an exemplary embodiment, the display device may further include a thin film encapsulation layer and an input sensor. The electronic element may include a light emitting element; the thin film encapsulation layer may be on the pad insulating layer and may cover the light emitting element; and an input sensor may be located on the thin film encapsulation layer, the input sensor including a sensing electrode.

In an exemplary embodiment, the signal line may include a first signal line connected to the light emitting element and a second signal line connected to the sensing electrode.

In an exemplary embodiment, the signal line may include a plurality of portions located on different layers.

In an exemplary embodiment, the signal pad may include a first signal pad and a second signal pad; the first signal pads may form a first pad row; the second signal pads may form a second pad row different from the first pad row; and the second signal pads may be in a staggered arrangement relative to the first signal pads.

In an exemplary embodiment, the second signal pads may be closer to an edge of the base layer than the first signal pads, and a signal line connected to one of the second signal pads among the signal lines may overlap with a second portion of a corresponding one of the first signal pads.

In an exemplary embodiment, an end portion of a signal line connected to one of the second signal pads among the signal lines may be located on a different layer from a layer on which the end portion of the signal line connected to one of the first signal pads is located.

In an exemplary embodiment, the display device may further include: a circuit board electrically connected to the signal pad; and an anisotropic conductive film configured to bond the signal pad to the circuit board.

According to one or more exemplary embodiments, a display device includes: a first signal line; a second signal line; a first signal pad connected to the first signal line; a second signal pad connected to a second signal line; and a pad insulating layer overlapping the first signal line and the second signal line. The first signal pad includes: an intermediate conductive pattern overlapping an end portion of the first signal line, the intermediate conductive pattern being connected to the end portion of the first signal line; and an upper conductive pattern on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The middle conductive pattern includes a first portion overlapping the end portion of the first signal line and a second portion between the end portion of the first signal line and the end portion of the second signal line, the second portion extending from the first portion, and the upper conductive pattern is connected to the second portion of the middle conductive pattern.

In an exemplary embodiment, the upper conductive pattern may not overlap each of the end portion of the first signal line and the end portion of the second signal line.

According to one or more exemplary embodiments, a display device includes: a substrate layer including a display region and a non-display region; a first switching transistor on the display area; a second switching transistor on the display area; a first signal line connected to the first switching transistor; a second signal line connected to the second switching transistor; a first signal pad connected to the first signal line; a second signal pad connected to a second signal line; and a pad insulating layer overlapping the first switching transistor, the second switching transistor, the first signal line, and the second signal line. Each of the first and second signal pads includes: an intermediate conductive pattern overlapping an end portion of a corresponding signal line among the first and second signal lines, the intermediate conductive pattern being electrically connected to the end portion of the corresponding signal line; and an upper conductive pattern on the middle conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The pad insulating layer has a pad contact hole exposing a portion of the middle conductive pattern, the pad contact hole overlapping an end portion of the corresponding signal line, the upper conductive pattern being connected to the middle conductive pattern through the pad contact hole, the upper conductive pattern being positioned within the pad contact hole in a plan view.

In an exemplary embodiment, the pad insulating layer may include an organic layer including a first portion between the first and second signal pads and a second portion overlapping the first switching transistor, and a thickness of the first portion of the organic layer may be in a range from about 60% to about 80% of a thickness of the second portion of the organic layer.

In an exemplary embodiment, the pad insulating layer may include a first organic layer, at least one inorganic layer on the first organic layer, and a second organic layer on the at least one inorganic layer. The first organic layer may include a first portion between the first signal pad and the second signal pad and a second portion overlapping the first switching transistor. The thickness of the first portion of the first organic layer may be in a range from about 45% to about 55% of the thickness of the second portion of the first organic layer.

In an exemplary embodiment, the pad insulating layer may include at least one inorganic layer and an organic layer on the at least one inorganic layer, and an upper surface of a portion of the organic layer between the first and second signal pads may be higher than an uppermost end portion of the upper conductive pattern.

According to the above, since the upper conductive pattern is disposed between the end portion of the corresponding signal line and the end portion of the adjacent signal line, the uppermost pattern of the signal pad may not overlap the end portion of the corresponding signal line. The upper conductive pattern is disposed lower than an upper surface of the pad insulating layer when viewed in a cross-sectional view. The portion of the pad insulating layer overlapping the end portion of the corresponding signal line has a function of a stopper to prevent or substantially prevent the upper conductive patterns from being short-circuited with each other.

By adjusting the thickness of the portion of the pad insulating layer disposed between the end portions of the signal lines, the upper conductive patterns can be prevented or substantially prevented from being short-circuited with each other. The portion of the pad insulating layer has a function of a stopper. By controlling the stacked structure of the pad insulating layer or adjusting the thickness of the organic layer, a stopper that prevents or substantially prevents the upper conductive patterns from being short-circuited with each other is formed by the pad insulating layer.

Drawings

The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting example embodiments, with reference to the accompanying drawings, in which:

fig. 1 is a perspective view illustrating a display device according to an exemplary embodiment of the present disclosure;

fig. 2 is a sectional view illustrating a display device according to an exemplary embodiment of the present disclosure;

fig. 3 is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 4A and 4B are plan views illustrating a display panel according to one or more exemplary embodiments of the present disclosure;

fig. 5A is an enlarged cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

fig. 5B is an enlarged cross-sectional view illustrating an upper insulating layer according to an exemplary embodiment of the present disclosure;

FIG. 6A is a cross-sectional view illustrating an input sensing layer according to an exemplary embodiment of the present disclosure;

FIG. 6B is a plan view illustrating an input sensing layer according to an exemplary embodiment of the present disclosure;

6C-6D are partial cross-sectional views illustrating an input sensing layer according to an exemplary embodiment of the present disclosure;

fig. 7A is a partial plan view illustrating a pad area according to an exemplary embodiment of the present disclosure;

fig. 7B to 7D are sectional views taken along line I-I' of fig. 7A;

fig. 8A is a partial plan view illustrating a pad area according to an exemplary embodiment of the present disclosure;

FIG. 8B is a cross-sectional view taken along line II-II' of FIG. 8A;

FIG. 8C is a cross-sectional view taken along line III-III' of FIG. 8A;

FIG. 9 is a cross-sectional view illustrating a pad area according to an exemplary embodiment of the present disclosure;

fig. 10A is a partial plan view illustrating a pad area according to an exemplary embodiment of the present disclosure; and

fig. 10B to 10E are sectional views taken along line IV-IV' of fig. 10A.

Detailed Description

Hereinafter, example embodiments will be described in more detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects and features of the inventive concepts to those skilled in the art. Accordingly, processes, elements, and techniques may not be described that are not necessary for a complete understanding of the aspects and features of the inventive concepts by one of ordinary skill in the art. Like reference numerals refer to like elements throughout the drawings and written description unless otherwise specified, and thus the description thereof may not be repeated.

In the drawings, the thickness, proportion, size, and relative size of elements, layers, and regions may be exaggerated and/or simplified for clarity. Spatially relative terms such as "below … …," "below … …," "below," "under," "… …," "above … …," "on," and the like may be used herein for ease of explanation to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below … …" and "below … …" can encompass both an orientation of above and below. The device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the inventive concept.

It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of … …" follows a list of elements, the entire list of elements is modified over and above the list of individual elements.

As used herein, the terms "substantially," "about," and the like are used as approximate terms and not as degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. Further, when describing embodiments of the inventive concept, the use of "may" mean "one or more embodiments of the inventive concept. As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilize" and variations thereof, respectively. Furthermore, the term "exemplary" is intended to mean exemplary or illustrative.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a perspective view illustrating a display device DD according to an exemplary embodiment of the present disclosure. Fig. 2 is a cross-sectional view illustrating a display device DD according to an exemplary embodiment of the present disclosure.

As shown in fig. 1, the display device DD displays an image IM at (e.g., through) the display surface DD-IS. The display surface DD-IS may be parallel or substantially parallel to a plane defined by the first and second orientation axes DR1 and DR 2. The third direction axis DR3 indicates a normal direction of the display surface DD-IS (e.g., a thickness direction of the display device DD).

The front (or upper) surface and the rear (or lower) surface of each member or each unit described below are distinguished from each other by the third direction axis DR 3. However, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are merely exemplary. Hereinafter, the first direction, the second direction, and the third direction correspond to directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are assigned the same reference numerals as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR 3.

In an exemplary embodiment of the present disclosure, the display device DD includes a flat display surface. However, the present disclosure is not limited thereto. For example, in another exemplary embodiment, the display device DD may include a curved display surface. In another example, the display device DD may include a three-dimensional display surface. The three-dimensional display surface may include a plurality of display regions indicating directions different from each other, for example, a polygonal cylindrical display surface.

In an exemplary embodiment, the display device DD may be a rigid display device, but the present disclosure is not limited thereto. For example, in another exemplary embodiment, the display device DD may be a flexible display device DD. The flexible display device DD may comprise a foldable display device or a bending type display device which may be partially bent.

For convenience, the display device DD is shown in fig. 1 as a part of a mobile phone terminal as a representative example. Although not shown in the drawings, one or more of an electronic module, a camera module, and/or a power module, which may be mounted on a main board, may be disposed on a stand or a case together with the display device DD to form a mobile phone terminal. However, the present disclosure is not limited thereto, and the display device DD according to various embodiments of the present disclosure may be applied to large electronic articles such as televisions, monitors, and the like, and/or medium and small electronic articles such as tablet computers, vehicle navigation units (e.g., vehicle navigation devices), game units (e.g., game consoles), smart watches, and the like.

As shown in fig. 1, the display surface DD-IS includes an image area DD-DA at which the image IM IS displayed (e.g., through the image area DD-DA), and a bezel area DD-NDA defined adjacent to the image area DD-DA (e.g., around the periphery of the image area DD-DA). The image IM is not displayed at or through the bezel region DD-NDA. Fig. 1 shows an icon image as a representative example of the image IM.

As shown in fig. 1, the image area DD-DA may have a quadrangular shape or a substantially quadrangular shape. The expression "substantially quadrangular shape" as used in the present specification may mean not only a quadrangular shape as mathematically defined, but also a quadrangular shape defining a curve boundary instead of vertices at or in a vertex region (or corner region).

The bezel region DD-NDA may surround the image region DD-DA (e.g., may be around the periphery of the image region DD-DA), but the present disclosure is not limited thereto. The image area DD-DA and the bezel area DD-NDA may have various suitable shapes. The bezel area DD-NDA may be defined at only one side of the image area DD-DA. Depending on the combination between the display device DD and other components of the electronic device, the bezel area DD-NDA may not be exposed to the outside.

Fig. 2 shows a cross-section defined by the second direction DR2 and the third direction DR 3. The components of the display device DD are schematically shown to illustrate their stacked relationship.

The display device DD according to an exemplary embodiment of the present disclosure may include a display panel DP, an input sensor ISL, an anti-reflector RPP, and a window WP. At least some components of the display panel DP, the input sensor ISL, the anti-reflector RPP, and the window WP may be formed through a continuous process, or may be attached to each other by an adhesive member (e.g., an adhesive or an adhesive layer). The adhesive member ADS may be a transparent adhesive member (e.g., a transparent adhesive layer) such as a Pressure Sensitive Adhesive (PSA) film, an Optically Clear Adhesive (OCA) film, an Optically Clear Resin (OCR), etc. The adhesive member described hereinafter may include an adhesive or a pressure sensitive adhesive. In exemplary embodiments of the present disclosure, the anti-reflector RPP and/or the window WP may be omitted or replaced with other components.

As shown in fig. 2, among the input sensor ISL, the anti-reflector RPP, and the window WP, the input sensor ISL may be formed together with the display panel DP through a continuous process and may be directly disposed on the display panel DP. As used in this disclosure, the expression "component B is disposed directly on component a" means that there is no intervening element (such as, for example, a separate adhesive layer or adhesive member) between component "B" and component "a". For example, the component "B" may be formed on the surface of the substrate provided by the component "a" by a continuous process after the component "a" is formed.

In an exemplary embodiment, the anti-reflector RPP and the window WP may be a "panel" type component and the input sensor ISL may be a "layer" type component. As used in this disclosure, a "panel" type assembly includes a substrate layer (e.g., a synthetic resin film, a composite film, a glass substrate, etc.) that provides a surface of the substrate, while for a "layer" type assembly, the substrate layer may be omitted. In other words, a component referred to as a "layer" type component may be disposed on a surface of a substrate provided by another component. In another exemplary embodiment, the anti-reflector RPP and the window WP may be a "layer" type component.

The display panel DP generates an image, and the input sensor ISL obtains coordinate information of an external input (e.g., a touch event). Although not separately shown, the display device DD according to an exemplary embodiment of the present disclosure may further include a protective member disposed on a lower surface of the display panel DP. The protective member and the display panel DP may be bonded to each other by an adhesive member.

The display panel DP according to the exemplary embodiment of the present disclosure may be a light emitting type display panel, but the present disclosure is not limited thereto. For example, the display panel DP may include or may be an organic light emitting display panel or a quantum dot light emitting display panel. The panels are different from each other according to the material of the light emitting element. The light emitting layer of the organic light emitting display panel may include an organic light emitting material. The light emitting layer of the quantum dot light emitting display panel may include quantum dots and/or quantum rods. Hereinafter, the organic light emitting display panel will be described as a representative example of the display panel DP.

The anti-reflector RPP reduces the reflectivity of external light incident thereon from above the window WP. An anti-reflector RPP according to an exemplary embodiment of the present disclosure may comprise a retarder and a polarizer. The retarder may be a film type retarder or a liquid crystal coated type retarder, and may include a half-wave retarder (e.g., a λ/2 retarder) and/or a quarter-wave retarder (e.g., a λ/4 retarder). The polarizer may be a film-type polarizer or a liquid crystal-coated polarizer. The film-type retarder and/or polarizer may include a stretched-type synthetic resin film, and the liquid crystal-coated retarder and/or polarizer may include liquid crystals oriented in a certain arrangement (e.g., a predetermined arrangement). The polarizer and/or retarder may further include a protective film. The retarder and/or polarizer or protective film may be defined as a base layer of the anti-reflector RPP.

The anti-reflector RPP according to an exemplary embodiment of the present disclosure may comprise a color filter. The color filters may have an arrangement (e.g., a predetermined arrangement). The arrangement of the color filters may be determined by considering emission colors of pixels included in the display panel DP. The anti-reflector RPP may also comprise a black matrix arranged adjacent to the color filter.

An anti-reflector RPP according to an exemplary embodiment of the present disclosure may comprise a destructive interference structure. For example, the destructive interference structure may include a first reflective layer and a second reflective layer that may be disposed at (e.g., disposed on or in) different layers from one another. The first and second reflected lights respectively reflected by the first and second reflective layers may be destructively interfered, and thus, the reflectivity of external light may be reduced.

Window WP according to an exemplary embodiment of the present disclosure includes a base layer WP-BS and a light blocking pattern WP-BZ. The base layer WP-BS may comprise a glass substrate and/or a synthetic resin film. The substrate layer WP-BS can comprise a single layer structure or a multilayer structure. For example, the base layer WP-BS can include two or more films bonded to each other by a bonding member.

The light shield patterns WP-BZ partially overlap the base layer WP-BS. The light shielding patterns WP-BZ are disposed on the rear surface of the substrate layer WP-BS, and the light shielding patterns WP-BZ define or substantially define a bezel area DD-NDA of the display device DD. The region where the light shielding patterns WP-BZ are not disposed (e.g., the region where the light shielding patterns WP-BZ are not disposed or the region on which the light shielding patterns WP-BZ are not disposed) may define an image region DD-DA of the display device DD. In the case of the window WP, a region in which the light shielding patterns WP-BZ are disposed may be defined as a light shielding region, and a region in which the light shielding patterns WP-BZ are not disposed may be defined as a transmission region.

The light shielding patterns WP-BZ may have a multi-layered structure. The multi-layered structure may include a colored layer and an achromatic (e.g., black) light-shielding layer. The colored layer and the non-colored light shield layer may be formed through a deposition process, a printing process, and/or a coating process. Although not shown in the figures, the window WP can also include a functional coating disposed on the front surface of the substrate layer WP-BS. The functional coating may include one or more of an anti-fingerprint layer, an anti-reflective layer, and/or a hard coat layer.

Fig. 3 is a cross-sectional view illustrating the display panel DP according to an exemplary embodiment of the present disclosure. Fig. 4A and 4B are plan views illustrating a display panel DP according to one or more exemplary embodiments of the present disclosure.

Referring to fig. 3, the display panel DP includes a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and an upper insulating layer TFL. The display region DP-DA and the non-display region DP-NDA, which may correspond to the image region DD-DA and the bezel region DD-NDA shown in fig. 1, respectively, may be defined at the display panel DP (e.g., defined in or on the display panel DP). As used in this disclosure, the expression "one region/portion corresponds to another region/portion" denotes regions/portions that overlap each other, and is not limited to regions/portions having the same size and/or the same shape as each other.

The base layer BL may include at least one synthetic resin film. The base layer BL may include a glass substrate, a metal substrate, and/or an organic/inorganic composite substrate.

The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines and pixel drive circuits.

The display element layer DP-OLED includes at least one organic light emitting diode as a light emitting element. The display element layer DP-OLED may further include an organic layer, such as a pixel defining layer, for example.

The upper insulating layer TFL includes a plurality of thin layers. Some of the thin layers (e.g., at least one of the thin layers) of the upper insulating layer TFL may improve optical efficiency, and some of the thin layers (e.g., at least one of the thin layers) of the upper insulating layer TFL may protect the organic light emitting diode. The upper insulating layer TFL will be described in more detail below.

As shown in fig. 4A and 4B, the display panel DP includes a driving circuit GDC, a plurality of signal lines (hereinafter, referred to as "signal lines") SGL, a plurality of signal pads (hereinafter, referred to as "signal pads") DP-PD and ISL-PD, and a plurality of pixels (hereinafter, referred to as "pixels") PX.

The drive circuit GDC includes a scan drive circuit. The scan driving circuit generates a plurality of scan signals (hereinafter, referred to as "scan signals"), and outputs (e.g., sequentially outputs) the scan signals to a plurality of scan lines (hereinafter, referred to as "scan lines") GL. The scan driving circuit may also output other control signals to the driving circuit of the pixel PX.

The scan driving circuit may include a plurality of transistors, and the transistors may be formed through the same or substantially the same process (e.g., a Low Temperature Polysilicon (LTPS) process, a Low Temperature Poly Oxide (LTPO) process, etc.) as that of the driving circuit of the pixel PX.

The signal line SGL includes a scanning line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the scanning lines GL is connected to a corresponding pixel among the pixels PX, and each of the data lines DL is connected to a corresponding pixel among the pixels PX. The power line PL is connected to the pixel PX. The control signal line CSL supplies a control signal to the scan driving circuit.

In an exemplary embodiment, the signal lines SGL may further include auxiliary lines SSL. The auxiliary line SSL may be a signal line connected to the input sensor ISL (e.g., refer to fig. 2). However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the auxiliary lines SSL may be omitted.

The signal line SGL may include a plurality of portions disposed at (e.g., disposed on or in) different layers from each other. For example, fig. 4A shows a data line DL including four portions P1, P2, P3, and P4 and an auxiliary line SSL including two portions P10 and P20. The four portions P1, P2, P3, and P4 of the data line DL may be connected to each other via a contact hole CNT, and the two portions P10 and P20 of the auxiliary line SSL may be connected to each other via the contact hole CNT. The first portion P10 of the auxiliary line SSL may be connected to a signal line of the input sensor ISL (e.g., refer to fig. 6B) via a contact hole CNT.

The signal pads DP-PD and ISL-PD may include a first signal pad (e.g., a first-type signal pad) DP-PD connected to the data line DL, the power line PL, and the control signal line CSL, and a second signal pad (e.g., a second-type signal pad) ISL-PD connected to the auxiliary line SSL. The first and second signal pads DP-PD and ISL-PD may be disposed adjacent to each other at a pad area NDA-PA (e.g., in or on the pad area NDA-PA) defined at a portion of the non-display area DP-NDA (e.g., defined in or on a portion of the non-display area DP-NDA). The stack structure and/or material of the first signal pad DP-PD may be the same as or substantially the same as (e.g., may not be distinguished from) the stack structure and/or material of the second signal pad ISL-PD, and the first signal pad DP-PD and the second signal pad ISL-PD may be formed by the same or substantially the same process.

The display region DP-DA may be defined as a region where the pixels PX are arranged (e.g., arranged therein or thereon). The plurality of electronic devices may be disposed at (e.g., in or on) the display region DP-DA. The electronic device may include an organic light emitting diode that may be disposed at each pixel PX (e.g., disposed in or on each pixel PX) and a pixel driving circuit connected to the organic light emitting diode. The driver circuit GDC, the signal line SGL, the signal pads DP-PD and ISL-PD, and the pixel driver circuit may be included at (e.g., included in or on) the circuit element layer DP-CL (e.g., as shown in fig. 3).

The pixel PX may include, for example, a first transistor T1, a second transistor T2, a capacitor CP, and an organic light emitting diode OLED. However, the present disclosure is not limited thereto, and for example, the pixel PX may include various suitable pixel circuit structures including at least a switching transistor and a driving transistor. The first transistor T1 is connected to the scan line GL and the data line DL. The organic light emitting diode OLED receives a power voltage supplied through the power line PL.

Fig. 4A also shows a circuit board PCB connected to the display panel DP. The circuit board PCB may be a rigid circuit board or a flexible circuit board.

The timing control circuit TC may be disposed on the circuit board PCB to control the operation of the display panel DP. An input sensing circuit ISL-C may be provided on the circuit board PCB to control the input sensor ISL. Each of the timing control circuit TC and the input sensing circuit ISL-C may be mounted on a circuit board PCB in the form of an integrated chip. In an exemplary embodiment of the present disclosure, the timing control circuit TC and the input sensing circuit ISL-C may be mounted on a circuit board PCB in one integrated chip form. The circuit board PCB may include a circuit board pad PCB-P electrically connected to the signal pads DP-PD and ISL-PD. Although not shown in the figures, the circuit board PCB may further comprise signal lines connecting the circuit board pad PCB-P to the timing control circuit TC and/or the input sensing circuit ISL-C. In some embodiments, circuit board pad PCB-P may be an output pad, and circuit board PCB may further include an input pad.

The signal pads DP-PD and ISL-PD of the display panel DP may be electrically connected to the circuit board pads PCB-P of the circuit board PCB by a conductive member such as an anisotropic conductive film ACF. However, the present disclosure is not limited thereto, and in another exemplary embodiment, the anisotropic conductive film ACF may be replaced by conductive balls.

As shown in fig. 4B, the display panel DP according to an exemplary embodiment of the present disclosure may further include a chip mounting region NDA-TC defined at (e.g., defined in or on) the non-display region DP-NDA. The timing control circuit TC (for example, refer to fig. 4A) may be mounted on the chip mounting area NDA-TC in a chip form.

The first chip pad TC-PD1 and the second chip pad TC-PD2 may be disposed at (e.g., in or on) the chip mounting region NDA-TC. The first chip pad TC-PD1 may be connected to the data line DL, and the second chip pad TC-PD2 may be connected to the first signal pad DP-PD via the input signal line SIL. Terminals of the timing control circuit TC may be connected to the first chip pad TC-PD1 and the second chip pad TC-PD 2. The data line DL may be electrically connected to the signal pad DP-PD via the timing control circuit TC. In an exemplary embodiment of the present disclosure, at least one line among the control signal line CSL and the power line PL may be connected to the timing control circuit TC.

The display panel DP shown in fig. 4A and 4B may be partially bent. In this case, portions of the non-display region DP-NDA may be bent with respect to a bending axis parallel or substantially parallel to the second direction DR 2. The bending axis may be defined to overlap the third portion P3 of the data line DL and the first portion P10 of the auxiliary line SSL.

Fig. 5A is an enlarged cross-sectional view illustrating the display panel DP according to an exemplary embodiment of the present disclosure. Fig. 5B is an enlarged cross-sectional view illustrating the upper insulating layer TFL according to an exemplary embodiment of the present disclosure.

Referring to fig. 5A, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layer, the semiconductor layer, and the conductive layer may be formed through a coating process and a deposition process. The insulating layer, the semiconductor layer, and the conductive layer may be patterned (e.g., selectively patterned) by a photolithography process. The semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed by the above-described method.

The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. The base layer BL may have a multilayer structure. For example, the base layer BL may have a three-layer structure including a synthetic resin layer, an adhesive layer, and a synthetic resin layer (e.g., another synthetic resin layer). In more detail, the synthetic resin layer may include or may be a polyimide-based resin layer, but the present disclosure is not limited thereto. The synthetic resin layer may include, for example, at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and/or a perylene resin. In addition, the base layer BL may include a glass substrate, a metal substrate, and/or an organic/inorganic composite substrate.

At least one inorganic layer may be formed on the upper surface of the base layer BL. The inorganic layer may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be provided as a plurality of layers. The inorganic layer may form a barrier layer and/or a buffer layer. In an exemplary embodiment, as shown in fig. 5A, the display panel DP includes a buffer layer BFL.

The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked on each other (e.g., alternately stacked on each other).

The semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, but the present disclosure is not limited thereto. The semiconductor pattern may include amorphous silicon or a metal oxide.

Fig. 5A shows a part of the semiconductor pattern, and the semiconductor pattern may also be disposed in another region of the pixel PX when viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP). The semiconductor pattern may be arranged throughout the pixels PX in a certain pattern (or rule). For example, the semiconductor pattern may have different electrical characteristics according to whether it is doped or not. The semiconductor pattern may include a doped region and an undoped region. The doped region may be doped with an N-type dopant or a P-type dopant. For example, if one or more of the first and second transistors T1 and T2 (see, e.g., fig. 4A) includes a P-type transistor, the P-type transistor includes a doped region of the semiconductor pattern doped with P-type dopants.

The doped regions of the semiconductor pattern may have a conductivity greater than that of the undoped regions. The doped regions of the semiconductor pattern may function as or substantially function as electrodes or signal lines. The undoped region of the semiconductor pattern may correspond or substantially correspond to an active region (or channel) of the transistor. In other words, a portion of the semiconductor pattern may include or may be an active region of a transistor, another portion of the semiconductor pattern may include or may be a source or a drain of the transistor, and another portion of the semiconductor pattern may be a connection electrode or a connection signal line.

As shown in fig. 5A, the source S1, the active region a1, and the drain D1 of the first transistor T1 may be formed using a semiconductor pattern, and the source S2, the active region a2, and the drain D2 of the second transistor T2 may be formed using a semiconductor pattern. The sources S1 and S2 and the drains D1 and D2 extend in opposite directions from the active regions a1 and a2 in the cross-sectional view. Fig. 5A shows a portion of the connection signal line SCL formed using a semiconductor pattern. Although not separately shown, the connection signal line SCL may be connected to the drain D2 of the second transistor T2 when viewed in a plan view.

The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 overlaps (e.g., commonly overlaps) the pixels PX (e.g., refer to fig. 4A and 4B) and covers the semiconductor pattern. The first insulating layer 10 may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an exemplary embodiment, as shown in fig. 5A, the first insulating layer 10 may include or may be a single silicon oxide layer. The insulating layer of the circuit element layer DP-CL (described in more detail below) may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the materials described above.

The gates G1 and G2 are disposed on the first insulating layer 10. The gate G1 may be part of a metal pattern. The gates G1 and G2 overlap the active regions a1 and a2, respectively. The gates G1 and G2 may act as a mask during a doping process of the semiconductor pattern.

The second insulating layer 20 is disposed on the first insulating layer 10 to cover the gates G1 and G2. The second insulating layer 20 overlaps (e.g., commonly overlaps) the pixels PX (e.g., refer to fig. 4A and 4B). The second insulating layer 20 may include an inorganic layer and/or an organic layer, and may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, as shown in fig. 5A, the second insulating layer 20 may be a single silicon oxide layer.

The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G2 of the second transistor T2. The upper electrode UE may be part of a metal pattern. A portion of the gate G2 and the upper electrode UE overlapping the portion of the gate G2 may define a capacitor CP (e.g., refer to fig. 4A). However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the upper electrode UE may be omitted.

The third insulating layer 30 is disposed on the second insulating layer 20 to cover the upper electrode UE. In an exemplary embodiment, as shown in fig. 5A, the third insulating layer 30 may be a single silicon oxide layer, but the present disclosure is not limited thereto, and the third insulating layer 30 may have another suitable single-layer structure or multi-layer structure. The first connection electrode CNE1 may be disposed on the third insulation layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 extending through (e.g., penetrating through) the first, second, and third insulating layers 10, 20, and 30.

The fourth insulating layer 40 is disposed on the third insulating layer 30. The fourth insulating layer 40 may include or may be a single silicon oxide layer. The fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may include or may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 extending through (e.g., penetrating) the fourth and fifth insulating layers 40 and 50.

The sixth insulating layer 60 is disposed on the fifth insulating layer 50 to cover the second connection electrode CNE 2. The sixth insulating layer 60 may include or may be an organic layer. The first electrode AE is disposed on the sixth insulating layer 60. The first electrode AE is connected to the second connection electrode CNE2 through a contact hole CNT-3 extending through (e.g., penetrating through) the sixth insulating layer 60. The opening OP is defined by the pixel defining layer PDL. At least a portion of the first electrode AE is exposed through the opening OP of the pixel defining layer PDL.

As shown in fig. 5A, the display area DP-DA may include a light-emitting area PXA and a non-light-emitting area NPXA disposed adjacent to the light-emitting area PXA. For example, the non-light-emitting area NPXA may surround the light-emitting area PXA (e.g., may be around the periphery of the light-emitting area PXA). In an exemplary embodiment, the light emitting region PXA is defined to correspond to a portion of the first electrode AE exposed through the opening OP.

The hole control layer HCL may be disposed (e.g., disposed in common) at the light-emitting area PXA and the non-light-emitting area NPXA (e.g., disposed in common) on or in the light-emitting area PXA and the non-light-emitting area NPXA). The hole control layer HCL may include a hole transport layer and/or a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed at an area corresponding to the opening OP (e.g., disposed in or on the area corresponding to the opening OP). For example, the light emitting layer EML may be formed at each of the pixels PX (e.g., formed in or on each of the pixels PX) after being divided into a plurality of sections.

The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may comprise an electron transport layer and/or an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed (e.g., commonly formed) at a plurality of pixels PX (e.g., in or on the plurality of pixels PX) using an open mask. The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have a single integral form, and may be disposed (e.g., commonly disposed) at (e.g., in or on) a plurality of pixels PX (e.g., refer to fig. 4A).

As shown in fig. 5A and 5B, an upper insulating layer TFL is disposed on the second electrode CE. The upper insulating layer TFL may include a plurality of thin films. As shown in fig. 5B, in an exemplary embodiment, the upper insulating layer TFL may include a cap layer CPL and a thin film encapsulation layer TFE. The thin film encapsulation layer TFE may include a first inorganic layer IOL1, an organic layer OL, and a second inorganic layer IOL 2.

The cap layer CPL is disposed on the second electrode CE, and may be in contact with the second electrode CE. The cap layer CPL comprises an organic material. First inorganic layer IOL1 is disposed on and may be in contact with cap layer CPL. The organic layer OL is disposed on the first inorganic layer IOL1 and may be in contact with the first inorganic layer IOL 1. The second inorganic layer IOL2 is disposed on the organic layer OL and may be in contact with the organic layer OL.

The cap layer CPL may protect the second electrode CE from a subsequent process (e.g., a sputtering process), and may improve the light emitting efficiency of the organic light emitting diode OLED. The cap layer CPL has a refractive index greater than the refractive index of the first inorganic layer IOL 1.

The first and second inorganic layers IOL1 and IOL2 may protect the display element layer DP-OLED from moisture and/or oxygen, and the organic layer OL may protect the display element layer DP-OLED from foreign substances (e.g., such as dust particles). Each of the first and second inorganic layers IOL1, IOL2 may include one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In exemplary embodiments of the present disclosure, the first and second inorganic layer IOLs 1 and 2 may include a titanium oxide layer or an aluminum oxide layer. The organic layer OL may include an acrylic organic layer, but the present disclosure is not limited thereto.

In exemplary embodiments of the present disclosure, an inorganic layer (e.g., LiF layer) may also be disposed between the cap layer CPL and the first inorganic layer IOL 1. In this case, the inorganic layer (e.g., LiF layer) may improve the light emitting efficiency of the organic light emitting diode OLED.

Fig. 6A is a cross-sectional view illustrating an input sensor ISL according to an exemplary embodiment of the present disclosure. Fig. 6B is a plan view illustrating an input sensor ISL according to an exemplary embodiment of the present disclosure. Fig. 6C and 6D are partial sectional views illustrating an input sensor ISL according to an exemplary embodiment of the present disclosure.

As shown in fig. 6A, the input sensor ISL may include a first insulating layer (hereinafter, referred to as a "first input insulating layer") ISL-IL1, a first conductive layer ISL-CL1, a second insulating layer (hereinafter, referred to as a "second input insulating layer") ISL-IL2, a second conductive layer ISL-CL2, and a third insulating layer (hereinafter, referred to as a "third input insulating layer") ISL-IL 3. The first input insulating layer ISL-IL1 may be disposed (e.g., disposed directly) on the upper insulating layer TFL. However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the first input insulating layer ISL-IL1 may be omitted.

Each of the first and second conductive layers ISL-CL1 and ISL-CL2 may have a single layer structure or a multi-layer structure in which a plurality of layers are stacked on each other in the third direction DR 3. The conductive layer having a multi-layer structure may include at least two layers among the transparent conductive layer and the metal layer. The conductive layer having a multi-layer structure may include metal layers having metals different from each other. The transparent conductive layer may include, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), Indium Tin Zinc Oxide (ITZO), PEDOT, metal nanowires, and/or graphene. The metal layer may comprise, for example, molybdenum, silver, titanium, copper, aluminum, and/or alloys thereof. For example, each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 may have a three-layer structure of titanium/aluminum/titanium. The metal having relatively high durability and low reflectivity may be an outer layer (e.g., one or more outer layers) and the metal having relatively high electrical conductivity may be an inner layer (e.g., an intervening layer, an intermediate layer, or multiple intermediate layers).

Each of the first conductive layer ISL-CL1 and the second conductive layer ISL-CL2 includes a plurality of patterns. Hereinafter, the first conductive layer ISL-CL1 will be described as including a first pattern, and the second conductive layer ISL-CL2 will be described as including a second pattern. Each of the first and second patterns may include a sensing electrode and a signal line connected to the sensing electrode.

Each of the first, second, and third input insulating layers ISL-IL1, ISL-IL2, and ISL-IL3 may include an inorganic layer or an organic layer. For example, in an exemplary embodiment, the first and second input insulating layers ISL-IL1 and ISL-IL2 may include or may be inorganic layers. The inorganic layer may include, for example, at least one of aluminum oxide, titanium oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The third input insulating layer ISL-IL3 may include or may be an organic layer. The organic layer may include, for example, at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

As shown in fig. 6B, the input sensor ISL includes a first electrode group EG1, a second electrode group EG2, and a signal line group connected to the first electrode group EG1 and the second electrode group EG 2. In an exemplary embodiment, as shown in fig. 6B, the input sensor ISL including two signal line groups SG1 and SG2 is shown as a representative example. The input sensor ISL may include sensing and line areas ISL-DA and ISL-NDA corresponding to the display and non-display areas DP-DA and DP-NDA of the display panel DP, respectively. The sensing region ISL-DA may be defined as a region where the first and second electrode groups EG1 and EG2 are disposed (e.g., disposed therein or thereon). The first signal line group SG1 and the second signal line group SG2 are disposed in the line region ISL-NDA.

In an exemplary embodiment, the input sensor ISL may include a capacitive type touch sensor, but the present disclosure is not limited thereto. One of the first electrode group EG1 and the second electrode group EG2 receives a driving signal, and the other of the first electrode group EG1 and the second electrode group EG2 outputs a sensing signal corresponding to a change in capacitance between the first electrode group EG1 and the second electrode group EG 2.

In an exemplary embodiment, the driving period may be divided into a first driving period and a second driving period. In this case, the input sensor ISL may be driven in the above-described manner during the first driving period, and the input sensor ISL may be driven in the opposite manner to the above-described manner during the second driving period. For example, during the first driving period, one of the first and second electrode groups EG1 and EG2 may receive a driving signal, and the other of the first and second electrode groups EG1 and EG2 may output a sensing signal. During the second driving period, the other one of the first and second electrode groups EG1 and EG2 may receive the driving signal, and the one of the first and second electrode groups EG1 and EG2 may output the sensing signal.

The first electrode group EG1 includes a plurality of first sensing electrodes IE1-1 through IE 1-10. The first electrode group EG1 including ten first sensing electrodes IE1-1 to IE1-10 is shown as a representative example, but the present disclosure is not limited to the number of first sensing electrodes shown in fig. 6B. First sensing electrodes IE1-1 through IE1-10 have a shape that extends in second direction DR 2. The second electrode group EG2 includes a plurality of second sensing electrodes IE2-1 through IE 2-8. The second electrode group EG2 including eight second sensing electrodes IE2-1 to IE2-8 is shown as a representative example, but the present disclosure is not limited to the number of second sensing electrodes shown in fig. 6B. Second sensing electrodes IE2-1 through IE2-8 have a shape that extends in first direction DR 1. Second sensing electrodes IE2-1 through IE2-8 have a length greater than the length of first sensing electrodes IE1-1 through IE 1-10.

The first signal line group SG1 may include the same or substantially the same number of signal lines as the number of first sense electrodes IE1-1 through IE 1-10. The signal line of the first signal line group SG1 may be connected to at least one of both ends of each of the first sense electrodes IE1-1 to IE 1-10. The second signal line group SG2 may include the same or substantially the same number of signal lines as the number of second sense electrodes IE2-1 through IE 2-8. The signal line of the second signal line group SG2 may be connected to at least one of both ends of each of the second sense electrodes IE2-1 to IE 2-8.

The signal lines of the first signal line group SG1 may be connected to some of the auxiliary lines SSL (e.g., refer to fig. 4A) disposed at one side of the pad region NDA-PA via the contact holes CNT. The signal lines of the second signal line group SG2 may be connected to some of the auxiliary lines SSL (e.g., refer to fig. 4A) disposed at the other side of the pad region NDA-PA via the contact holes CNT.

The contact hole CNT extends through (e.g., penetrates through) the insulating layer disposed between the signal line of the first signal line group SG1 and the auxiliary line SSL. For example, the contact hole CNT may extend through (e.g., penetrate through) the first and second input insulating layers ISL-IL1 and ISL-IL2 and some of the first to sixth insulating layers 10 to 60 of the input sensor ISL.

Each of first sense electrodes IE1-1 through IE1-10 may include a plurality of sensor portions SP1 and a plurality of bridge portions CP 1. The plurality of sensor portions SP1 may be connected by a plurality of bridge portions CP 1. Each of second sense electrodes IE2-1 through IE2-8 may include a plurality of first portions SP2 and a plurality of second portions CP 2. At least two of the plurality of first portions SP2 may be disposed such that each of the plurality of second portions CP2 is located between the first portions SP 2.

Fig. 6C shows a cross-sectional view taken along line X-X' of fig. 6B. Fig. 6C shows an example in which the bridge portion CP1 crosses the second portion CP 2. In an exemplary embodiment, the bridge portion CP1 may correspond to a bridge pattern. However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the second portion CP2 may correspond to a bridge pattern.

Referring to fig. 6A to 6C, a bridge portion CP1 is formed using a first conductive layer ISL-CL1, and a sensor portion SP1, a first portion SP2, and a second portion CP2 are formed using a second conductive layer ISL-CL 2. The sensor portion SP1 may be connected to the bridge portion CP1 through a contact hole CNT-IL2 extending through (e.g., penetrating) the second input insulating layer ISL-IL 2.

In an exemplary embodiment, as shown in fig. 6C, the bridge portion CP1 may cross the second portion CP2, but the present disclosure is not limited thereto. For example, each of the bridging portions CP1 may be modified to have a curved form with a shape "Λ" corresponding to a V-like shape rotated about 180 degrees and/or a curved form with a V-like shape "V" so as not to overlap with the second portion CP 2. The bridging portion CP1 in the form of a curve having the shape "Λ" and/or a curve having the shape "v" may overlap the first portion SP2 when viewed in a plan view.

According to an exemplary embodiment, the signal lines of the first and second signal line groups SG1 and SG2 include at least one of portions disposed in the same or substantially the same layer as that of the first sensing electrodes IE1-1 to IE1-10 and portions disposed in the same or substantially the same layer as that of the second sensing electrodes IE2-1 to IE 2-8.

Fig. 6D shows a cross-sectional view taken along line XI-XI' of fig. 6B. The tenth signal line SG1-10 among the first signal line group SG1 is shown as a representative example. The first signal line group SG1 includes at least a portion disposed in the same or substantially the same layer as that of the second sense electrodes IE2-1 to IE 2-8. The signal lines of the first signal line group SG1 and the second signal line group SG2 may further include a portion formed using the first conductive layer ISL-CL1 (for example, refer to fig. 6A).

Fig. 7A is a partial plan view illustrating a pad area NDA-PA of a display panel DP according to an exemplary embodiment of the present disclosure. Fig. 7B to 7D are sectional views taken along the line I-I' of fig. 7A. Hereinafter, redundant description of components and/or configurations identical or substantially identical to those described with reference to fig. 1 to 6D may not be repeated.

Fig. 7A to 7D show the first signal pad DP-PD as a representative example, but the second signal pad ISL-PD may have the same or substantially the same structure and/or arrangement as the first signal pad DP-PD.

The first signal pads DP-PD may be arranged at certain intervals (e.g., regular intervals) in the second direction DR 2. The portion of the data line DL shown in fig. 7A may correspond to the fourth portion P4 of the data line DL shown in fig. 4A. The end portion DL-E of the data line DL may have a relatively large width when compared to the width of the line portion DL-S. The width may be defined as a length (e.g., shortest length) in the second direction DR 2. However, the present disclosure is not limited thereto, and in another exemplary embodiment of the present disclosure, the end portion DL-E may have the same or substantially the same width as that of the line portion DL-S without being distinguished from the line portion DL-S. In fig. 7A, the contact hole CNT is shown as a representative example of a plurality of contact holes.

Referring to fig. 7B, an end portion DL-E of the data line DL is disposed on the second insulating layer 20. The end portion DL-E of the data line DL is disposed in the same or substantially the same layer as that of the upper electrode UE shown in fig. 5A. The structure is the same as or substantially the same as the structure in which the fourth portion P4 of the data line DL shown in fig. 4A is disposed in the same or substantially the same layer as that of the upper electrode UE. The first and third parts P1 and P3 of the data line DL shown in fig. 4A may be disposed in the same or substantially the same layer as that of the second connection electrode CNE2 shown in fig. 5A, and the second part P2 of the data line DL may be disposed in the same or substantially the same layer as that of the upper electrode UE.

The first conductive pattern CL1 is disposed on the third insulating layer 30 and overlaps the end portion DL-E. The first conductive pattern CL1 is in contact with (or electrically connected to) the end portion DL-E through the first contact hole CNT1 extending (e.g., penetrating) through the third insulating layer 30.

The first conductive pattern CL1 includes a first portion CL-P1 overlapping the end portion DL-E and a second portion CL-P2 extending from the first portion CL-P1. The second portion CL-P2 is disposed between an end portion DL-E of the corresponding data line DL and an end portion DL-E of another data line DL adjacent to (e.g., closest to) the corresponding data line DL.

In fig. 7A and 7B, the second section CL-P2 is defined by a section extending to the left of the first section CL-P1. In an exemplary embodiment, the first conductive pattern CL1 may further include a portion extending to the right of the first portion CL-P1 and not overlapping the end portion DL-E. The portion extending to the right of the first section CL-P1 may be defined as a third section. However, a portion (e.g., the third portion) where the contact hole cannot secure a sufficient contact area may be omitted.

The second portion CL-P2 may be defined by a portion that does not overlap with the end portion DL-E of the corresponding data line DL. The second portion CL-P2 of the signal pad DP-PD shown on the right side of fig. 7B is disposed between the two end portions DL-E of the two data lines DL shown in fig. 7B.

The second conductive pattern CL2 is disposed on the fourth insulating layer 40. The second conductive pattern CL2 contacts the second portion CL-P2 through the second contact hole CNT2 extending through (e.g., penetrating through) the fourth insulating layer 40. The second contact hole CNT2 does not overlap with the end portion DL-E when viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP).

The sixth insulating layer 60 is disposed on the fourth insulating layer 40. The third contact holes CNT3 and CNT30 are defined through the sixth insulating layer 60 to expose the second conductive pattern CL 2. Fig. 7B shows two kinds of third contact holes CNT3 and CNT30 as representative examples. The third contact hole CNT3 shown on the left side of fig. 7B and the third contact hole CNT30 shown on the right side of fig. 7B may be formed through processes different from each other. For example, the contact structure shown on the left side of fig. 7B may be obtained by forming the first input insulating layer ISL-IL1 after forming the third contact hole CNT 3. The contact structure shown on the right side of fig. 7B may be obtained by forming the third contact hole CNT30 through the first input insulating layer ISL-IL1 and the sixth insulating layer 60 after forming the sixth insulating layer 60 and the first input insulating layer ISL-IL 1.

In more detail, the contact structure shown on the left side of fig. 7B can be obtained by: depositing a first input insulating layer ISL-IL1 after forming the third contact hole CNT 3; and forming a fourth contact hole CNT4 passing through the first input insulating layer ISL-IL1 to expose the second conductive pattern CL 2.

The third and fourth contact holes CNT3 and CNT4 shown on the left side of fig. 7B and the third contact hole CNT30 shown on the right side of fig. 7B are shown for one pad region NDA-PA, but the present disclosure is not limited thereto. For example, in various exemplary embodiments, the contact structure in the pad region NDA-PA may be formed to have the same or substantially the same structure as that of the contact structure shown on the left side of fig. 7B or the contact structure shown on the right side of fig. 7B.

Referring to a sectional view of the pad region NDA-PA shown in fig. 7B and a sectional view of the display region DP-DA shown in fig. 5A, the stacked structures of the insulating layers are different from each other. For example, the fifth insulating layer 50 may not be disposed in the pad region NDA-PA. Therefore, even if the second connection electrode CNE2 shown in fig. 5A and the second conductive pattern CL2 shown in fig. 7B may be formed by the same or substantially the same process, the second connection electrode CNE2 shown in fig. 5A and the second conductive pattern CL2 shown in fig. 7B may be disposed on different layers from each other.

In addition, referring to fig. 3 to 5A, the upper insulating layer TFL may not be formed in the pad region NDA-PA. Among the first, second, and third input insulating layers ISL-IL1, ISL-IL2, and ISL-IL3 described with reference to fig. 6A, the second and third input insulating layers ISL-IL2 and ISL-IL3 may not be formed in the pad region NDA-PA. In the pad region NDA-PA, the sixth insulating layer 60 may be directly disposed on the fourth insulating layer 40, and the first input insulating layer ISL-IL1 may be directly disposed on the sixth insulating layer 60.

In an exemplary embodiment, an insulating layer disposed on the second conductive pattern CL2 and exposing the second conductive pattern CL2 may be defined as a pad insulating layer. The pad insulating layer may overlap the display region DP-DA and the pad region NDA-PA. For example, as shown in fig. 7B, in an exemplary embodiment, the pad insulating layer may include the sixth insulating layer 60 and the first input insulating layer ISL-IL 1.

Each of the contact holes CNT3 and CNT4 shown on the left side of fig. 7B and the contact hole CNT30 shown on the right side of fig. 7B may be defined as a pad contact hole. The third conductive pattern CL3 is in contact with the second conductive pattern CL2 through pad contact holes CNT3, CNT4, and CNT 30. The third conductive pattern CL3 may be formed using the second conductive layer ISL-CL2 shown in fig. 6A. The third conductive pattern CL3 may have a multilayer structure, for example, a titanium/aluminum/titanium triple-layer structure.

When viewed in a plan view, the third conductive pattern CL3 is disposed at the pad contact holes CNT3, CNT4, and CNT30 (e.g., disposed inside the pad contact holes CNT3, CNT4, and CNT30, disposed inside the pad contact holes CNT3, CNT4, and CNT30, or disposed on the pad contact holes CNT3, CNT4, and CNT 30). Third conductive pattern CL3 is disposed at pad contact holes CNT3, CNT4, and CNT30 (e.g., disposed inside pad contact holes CNT3, CNT4, and CNT30, disposed inside pad contact holes CNT3, CNT4, and CNT30, or disposed on pad contact holes CNT3, CNT4, and CNT 30) in third direction DR 3. Referring to pad contact holes CNT3 and CNT4 shown on the left side of fig. 7B, a third conductive pattern CL3 is disposed at least one pad contact hole CNT3 (e.g., disposed inside at least one pad contact hole CNT3, within at least one pad contact hole CNT3, or on at least one pad contact hole CNT 3) among two pad contact holes CNT3 and CNT 4. The third conductive pattern CL3 is a pattern that is in contact (e.g., direct contact) with the anisotropic conductive film ACF (e.g., refer to fig. 4A), and in the exemplary embodiment shown in fig. 7B, the third conductive pattern CL3 may be defined as an upper conductive pattern. The thickness TH61 of the sixth insulating layer 60 (see, e.g., fig. 7B) in the pad region NDA-PA may be different from the thickness TH60 of the sixth insulating layer 60 (see, e.g., fig. 5A) in the display region DP-DA. The thickness of the sixth insulating layer 60, which may be an organic layer, may be controlled according to regions using a half-tone mask.

The thickness TH61 of the sixth insulating layer 60 in the pad region NDA-PA may be smaller than the thickness TH60 of the sixth insulating layer 60 in the display region DP-DA. The thickness TH61 of the sixth insulating layer 60 in the pad region NDA-PA may be, for example, in a range from about 45% to about 55% of the thickness TH60 of the sixth insulating layer 60 in the display region DP-DA. The thickness TH61 is obtained by measuring the thickness of a region (hereinafter, referred to as "blocking region") 60-BP of the sixth insulating layer 60 disposed between both end portions DL-E of the pad region NDA-PA (e.g., disposed in or on the pad region NDA-PA), and the thickness TH60 is obtained by measuring the thickness of the sixth insulating layer 60 at a region overlapping with the transistor T2 in the display region DP-DA.

When the thickness TH61 of the sixth insulating layer 60 in the pad region NDA-PA is small, the bonding characteristics of the third conductive pattern CL3 and the anisotropic conductive film ACF (for example, refer to fig. 4A) may be improved. The third conductive pattern CL3 is positioned lower than the upper surface of the sixth insulating layer 60 and the upper surface of the first input insulating layer ISL-IL 1. The portion of the pad insulating layer overlapping the end portion DL-E of the data line DL serves as a stopper to prevent or substantially prevent the third conductive patterns CL3 from being short-circuited with each other.

For example, a first conductive layer ISL-CL1 may be formed on a surface (e.g., the entire surface) of the first input insulating layer ISL-IL1, and the first conductive layer ISL-CL1 may be patterned by an etching process to form a bridge portion CP1 from the first conductive layer ISL-CL1 (e.g., refer to fig. 6C). During the etching process of the first conductive layer ISL-CL1 at (e.g., in or on) the pad area NDA-PA, residues may remain on the first input insulating layer ISL-IL 1. The blocking region 60-BP may serve as a barrier to prevent or substantially prevent the etching residues from short-circuiting the third conductive pattern CL3 of the signal pad DP-PD adjacent to the etching residues.

As shown in fig. 7C, in an exemplary embodiment of the present invention, the end portion DL-E of the data line DL may be disposed in the same or substantially the same layer as that of the gate electrode G2 shown in fig. 5A. The first contact hole CNT1 extends through (e.g., penetrates) the second insulating layer 20 and the third insulating layer 30. The gate electrode G2 and the end portion DL-E of the data line DL may be formed through the same or substantially the same process.

As shown in fig. 7D, in an exemplary embodiment of the present invention, the second conductive pattern CL2 may include a first portion CL-P1 overlapping the end portion DL-E and a second portion CL-P2 extending from the first portion CL-P1. The second contact hole CNT2 may overlap the first contact hole CNT1 when viewed in a plan view. The first portion CL-P1 of the second conductive pattern CL2 contacts the first conductive pattern CL1 through the second contact hole CNT 2.

The second portion CL-P2 of the second conductive pattern CL2 is exposed through the third contact holes CNT3 and CNT30, and the third conductive pattern CL3 contacts the second portion CL-P2 of the second conductive pattern CL 2.

In this case, the first conductive pattern CL1 may have a length in the second direction DR2 that is less than the length of the second conductive pattern CL 2. The first conductive pattern CL1 may not overlap with the third contact holes CNT3 and CNT30 when viewed in a plan view (e.g., on a plane parallel or substantially parallel to the top surface of the display panel DP). The first conductive pattern CL1 may further include a portion corresponding to (e.g., overlapping) the second portion CL-P2 of the second conductive pattern CL 2.

Fig. 8A is a partial plan view illustrating a pad area NDA-PA according to an exemplary embodiment of the present disclosure. Fig. 8B is a sectional view taken along line II-II' of fig. 8A. Fig. 8C is a sectional view taken along line III-III' of fig. 8A. Hereinafter, redundant description of components and/or configurations identical or substantially identical to those described with reference to fig. 1 to 7D may not be repeated.

The signal pads DP-PD may be arranged in a plurality of rows different from each other, for example, a first pad row PDL1 and a second pad row PDL 2. The second pad rows PDL2 are disposed adjacent to the edge DP-E of the display panel DP in the first direction DR1 such that the second pad rows PDL2 is closer to the edge DP-E than the first pad rows PDL1 in the first direction DR 1. The signal pads of the first pad row PDL1 may be referred to as first signal pads DP-PD1, and the signal pads of the second pad row PDL2 may be referred to as second signal pads DP-PD 2.

The second signal pads DP-PD2 are disposed in a staggered arrangement relative to the first signal pads DP-PD 1. The third conductive pattern CL3 of the first pad row PDL1 is aligned with the end portion DL-E of the data line DL connected to the second pad row PDL2 in the first direction DR 1. The third conductive patterns CL3 of the first pad row PDL1 are diagonally disposed (e.g., disposed on a diagonal line) with respect to the third conductive patterns CL3 of the second pad row PDL 2.

Fig. 8B illustrates a cross-sectional view of the structure of the first signal pad DP-PD 1. The structure of the first signal pad DP-PD1 shown in fig. 8B may be the same as or substantially the same as the structure of the signal pad DP-PD shown in fig. 7B as a representative example. Referring to fig. 8B, the contact hole CNT3 shown at the left side of fig. 8B and the contact hole CNT3 shown at the right side of fig. 8B are identical or substantially identical to each other.

A line portion DL-S of the data line DL connected to the second signal pad DP-PD2 overlaps the third conductive pattern CL3 of the first pad row PDL 1. The data line DL connected to the second signal pad DP-PD2 is disposed in the same or substantially the same layer as that of the gate electrode G2 shown in fig. 5A.

Fig. 8C shows a cross-sectional view of the structure of the second signal pad DP-PD 2. The structure of the second signal pad DP-PD2 may be the same as or substantially the same as that of the signal pad DP-PD shown on the left side of fig. 7C as a representative example. However, the present disclosure is not limited thereto. For example, in various exemplary embodiments of the present disclosure, the sectional structures of the first and second signal pads DP-PD1 and DP-PD2 shown in fig. 8B and 8C may be modified to have the same or substantially the same structure as that of the signal pad DP-PD shown on the left side of fig. 7D, or may be modified to have the same or substantially the same structure as that of the signal pad DP-PD shown on the right side of fig. 7D. In other words, in another exemplary embodiment, the second conductive pattern CL2 may include a first portion CL-P1 and a second portion CL-P2.

Fig. 9 is a partial cross-sectional view illustrating a pad area NDA-PA according to an exemplary embodiment of the present disclosure. Hereinafter, redundant description of components and/or configurations identical or substantially identical to those described with reference to fig. 1 to 8C may not be repeated.

Referring to fig. 9, when compared to the signal pad DP-PD shown in fig. 7B, the second conductive pattern CL2 is omitted. The stacked structure of the insulating layers 10 to 40 is shown to have the same or substantially the same stacked structure as the stacked structure of the insulating layers 10 to 40 shown in fig. 7B. However, the present disclosure is not limited thereto, and one or more of the insulating layers 10 to 40 may be omitted, for example, the fourth insulating layer 40 may be omitted in another exemplary embodiment of the present disclosure.

In more detail, the signal pads DP-PD respectively connected to the first and second data lines DL may have the same or substantially the same stack structure. In this case, the signal pad DP-PD includes the middle conductive pattern CL1 and the upper conductive pattern CL 3. The middle conductive pattern CL1 includes a first portion CL-P1 overlapping the end portion DL-E of the data line DL and a second portion CL-P2 extending from the first portion CL-P1. The second portion CL-P2 of the middle conductive pattern CL1 may be disposed between end portions DL-E of the two data lines DL when viewed in a plan view. According to an exemplary embodiment, as shown in fig. 9, the middle conductive pattern CL1 includes a conductive pattern having a single-layer structure formed using one conductive layer. However, the present disclosure is not limited thereto, and for example, according to the embodiment described with reference to fig. 7B, the middle conductive pattern CL1 may include a conductive pattern having a multi-layer structure that may be formed using two or more conductive layers.

The first portion CL-P1 of the middle conductive pattern CL1 may be connected (e.g., directly connected) to the end portion DL-E of the data line DL, or may be connected to the end portion DL-E through one or more other conductive patterns. The upper conductive pattern CL3 does not overlap the end portions DL-E of the first and second data lines DL. The middle conductive pattern CL1 may be referred to as a first conductive pattern CL 1. The upper conductive pattern CL3 may be referred to as a third conductive pattern CL 3.

Fig. 10A is a partial plan view illustrating a pad area NDA-PA according to an exemplary embodiment of the present disclosure. Fig. 10B to 10E are sectional views taken along line IV-IV' of fig. 10A. Hereinafter, redundant description of components and/or configurations identical or substantially identical to those described with reference to fig. 1 to 9 may not be repeated.

Fig. 10A shows a pad area NDA-PA including a first pad row PDL1 and a second pad row PDL 2. According to an exemplary embodiment, the signal pad DP-PD may not include a conductive pattern extending in the second direction DR2, which may be different from the signal pad DP-PD described with reference to one or more of the above exemplary embodiments.

Fig. 10B and 10C show cross-sectional views corresponding to fig. 7B and 7C, respectively, according to other exemplary embodiments. The signal pad DP-PD includes the first conductive pattern CL1, the second conductive pattern CL2, and the third conductive pattern CL 3. The second contact hole CNT2 overlaps the first contact hole CNT 1. The second and first contact holes CNT2 and CNT1 overlap the end portion DL-E, the first conductive pattern CL1, the second conductive pattern CL2, and the third conductive pattern CL 3. In an exemplary embodiment, the middle conductive pattern may have a two-layer structure, but the present disclosure is not limited thereto. In an exemplary embodiment of the present disclosure, the middle conductive pattern may include the first conductive pattern CL1 or the second conductive pattern CL 2.

The thickness TH62 of the barrier region 60-BP in the pad region NDA-PA may be smaller than the thickness TH60 of the sixth insulating layer 60 in the display region DP-DA shown in fig. 5A. The thickness TH62 of the barrier region 60-BP may be in the range from about 60% to about 80% of the thickness TH60 of the sixth insulating layer 60 in the display region DP-DA. The thickness TH62 of the blocking region 60-BP can be adjusted by controlling the amount of light impinging on the blocking region 60-BP during the exposure process.

In an exemplary embodiment, the thickness TH62 of the barrier region 60-BP is relatively greater than the thickness TH61 of the barrier region 60-BP shown in FIG. 7B. In the exemplary embodiment, since the end portion DL-E, the first conductive pattern CL1, the second conductive pattern CL2, and the third conductive pattern CL3 are stacked to overlap each other, the uppermost position of the third conductive pattern CL3 is relatively higher than the uppermost position of the third conductive pattern CL3 shown in fig. 7B. Accordingly, in an exemplary embodiment, when the thickness of the blocking region 60-BP is greater than the thickness of the blocking region 60-BP shown in fig. 7B, the blocking region 60-BP shown in fig. 10B may have the above-described function of a barrier (e.g., the blocking region 60-BP may function as a barrier to prevent or substantially prevent etching residues from short-circuiting the third conductive patterns CL3 with each other).

Fig. 10D illustrates a cross-sectional view corresponding to the cross-sectional view illustrated in fig. 7B, according to another exemplary embodiment. In an exemplary embodiment, the thickness TH61 of the barrier region 60-BP may be in a range from about 45% to about 55% of the thickness TH60 of the sixth insulating layer 60 in the display region DP-DA (see, e.g., fig. 5A). According to an exemplary embodiment, the pad insulating layer may further include a third input insulating layer ISL-IL 3. The third input insulating layer ISL-IL3 includes an opening IL3-OP defined therethrough to expose the third conductive pattern CL 3. In an exemplary embodiment of the present disclosure, the pad insulating layer may further include a first input insulating layer ISL-IL 1. In this case, a contact hole is defined through the first input insulating layer ISL-IL1 to expose the second conductive pattern CL 2.

The third input insulating layer ISL-IL3 may be an organic layer. The region of the third input insulating layer ISL-IL3 disposed between the two end portions DL-E may serve as a barrier. An upper surface IL3-US of a portion of the third input insulating layer ISL-IL3 disposed between the two signal pads DP-PD is disposed higher than an uppermost end CL3-UP of the third conductive pattern CL 3.

Fig. 10E shows a cross-sectional view of a pad area NDA-PA according to an exemplary embodiment. The exemplary embodiment shown in fig. 10E may be different from the exemplary embodiment shown in fig. 10D. According to an exemplary embodiment, as shown in fig. 10E, the pad insulating layer may not include the sixth insulating layer 60. In this case, the pad insulating layer may include a first input insulating layer ISL-IL1, a second input insulating layer ISL-IL2, and a third input insulating layer ISL-IL 3. The first and second input insulating layers ISL-IL1 and ISL-IL2 may include inorganic layers, and the third input insulating layer ISL-IL3 may include organic layers.

The region of the third input insulating layer ISL-IL3 disposed between the two end portions DL-E may serve as a barrier. An upper surface IL3-US of a portion of the third input insulating layer ISL-IL3 disposed between the two signal pads DP-PD is disposed higher than an uppermost end CL3-UP of the third conductive pattern CL 3.

Referring to fig. 10A to 10E, the third conductive patterns CL3 may be prevented or substantially prevented from being shorted with each other by modifying (e.g., adjusting) the thickness of the pad insulating layer disposed between the end portions DL-E of the data lines DL. Portions of the pad insulating layer may serve as (or function as) barriers. In addition, the blocking member is formed by controlling the stack structure of the pad insulating layer and/or adjusting the thickness of an organic layer formed (e.g., concurrently or simultaneously formed) with the input sensor ISL.

Although one or more exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Thus, it will be appreciated by those skilled in the art that modifications may be made to the various aspects and features of the invention without departing from the spirit and scope of the invention as defined in the appended claims and their equivalents.