阅读说明：本技术 一种多通道高速数据对齐的方法及装置 (Method and device for aligning multi-channel high-speed data ) 是由 杨彦波 郝鹏 李恒 于 2020-06-12 设计创作，主要内容包括：本发明公开了一种多通道高速数据对齐的方法及装置,涉及通信技术领域。该方法包括：根据输入的控制信号、参考时钟产生采样时钟信号、采样参考时钟信号、接收时钟信号和接收参考时钟信号；根据输入的延时控制信号对接收参考时钟信号进行延时,产生延时接收参考时钟信号。发送侧的各通道均在采样参考时钟的每个上升沿开始,根据采样时钟信号对输入数据进行采样。接收侧的各通道对采样数据进行恢复和缓存,并在延时接收参考时钟信号的每个上升沿开始,根据接收时钟将数据从缓存中读取送出。本发明能在实现多通道高速数据对齐的同时,有效减少和确定由此引入的延时和抖动,满足实际应用需求。(The invention discloses a method and a device for aligning multi-channel high-speed data, and relates to the technical field of communication. The method comprises the following steps: generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; and delaying the receiving reference clock signal according to the input delay control signal to generate a delay receiving reference clock signal. Each channel on the transmission side samples input data according to a sampling clock signal, starting at each rising edge of a sampling reference clock. And each channel at the receiving side recovers and buffers the sampled data, and reads and sends the data out of the buffer according to the receiving clock from each rising edge of the delayed receiving reference clock signal. The invention can effectively reduce and determine the time delay and jitter introduced by the method while realizing the multi-channel high-speed data alignment, and meets the requirement of practical application.)

1. A method of multi-channel high speed data alignment, the method comprising the steps of:

generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; delaying a receiving reference clock signal according to an input delay control signal to generate a delay receiving reference clock signal;

each channel of the transmitting side samples input data according to the sampling clock signal from each rising edge of the sampling reference clock signal; and sending the sampled data to a receiving side;

and each channel at the receiving side recovers and buffers the sampled data, and reads and sends the data out of the buffer according to the receiving clock signal from each rising edge of the delayed receiving reference clock signal.

2. A method of multi-channel high speed data alignment as claimed in claim 1, wherein: according to the input control signal, a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal are generated by means of frequency multiplication and/or frequency division of a reference clock.

3. The method of multi-channel high speed data alignment of claim 1 wherein the sampling clock signal, the sampling reference clock signal, the receive reference clock signal are configurable in period and the configuration requirement is:

the frequency of the sampling clock signal is greater than or equal to that of the sampling reference clock signal, the frequency of the receiving clock signal is greater than or equal to that of the receiving reference clock signal, and the sampling reference clock signal and the receiving reference clock signal have the same frequency.

4. The method of multichannel high speed data alignment of claim 1 wherein the received reference clock signal is delayed according to an input delay control signal, the delay value is configurable, and the configuration requires:

the delay value is greater than or equal to a delay calculation value and is an integral multiple of a delay unit of the delayer, and the calculation process of the delay calculation value is as follows: and dividing the maximum delay in the delays of all channels by the delay unit of the delayer, rounding up the calculated value, and multiplying by the delay unit of the delayer.

5. The method of multi-channel high-speed data alignment of claim 1, wherein when each channel of the receiving side buffers the sample data, the data buffer depth of each channel is independently calculated, and the following requirements are satisfied:

the depth of each channel cache data is an integer which is greater than or equal to the calculated value of the channel cache depth, and the calculation process of the calculated value of the channel cache depth is as follows: subtracting the channel delay from the delay value, multiplying by a single-channel sampling rate, and rounding up the calculated value;

the single-channel sampling rate is the sampling reference clock signal frequency multiplied by the number of sampling points sampled at one time.

6. An apparatus for multi-channel high-speed data alignment, comprising: the device comprises a control side, a transmitting side and a receiving side;

the control side comprises a signal generating module and a signal delay module; the signal generation module is configured to: generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; the signal delay module is configured to: delaying a receiving reference clock signal according to an input delay control signal to generate a delay receiving reference clock signal;

the transmitting side comprises a plurality of groups of data sampling modules and transmitting drivers, and each group corresponds to one transmitting channel; the data sampling module is configured to: sampling input data according to the sampling clock signal from each rising edge of the sampling reference clock signal, and sending the sampled data to a sending driver; the transmit driver is to: sending the sampled data to a receiving side;

the receiving side comprises a plurality of groups of receivers, a data clock recovery module and a data cache module, wherein each group corresponds to a receiving channel; the receiver is configured to: receiving sampling data sent by a sending driver; the data clock recovery module is configured to: recovering the sampled data; the data caching module is configured to: and buffering the recovered data, and reading and sending the data out of the buffer according to the receiving clock signal from each rising edge of the delayed receiving reference clock signal.

7. The apparatus for multi-channel high speed data alignment of claim 6 wherein: the signal generation module generates a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal by means of frequency multiplication and/or frequency division of the reference clock.

8. The multi-channel high speed data alignment apparatus of claim 6, wherein the cycles of the sampling clock signal, the sampling reference clock signal, the receiving clock signal, and the receiving reference clock signal generated by the signal generation module are configurable, and the configuration requires:

the frequency of the sampling clock signal is greater than or equal to that of the sampling reference clock signal, the frequency of the receiving clock signal is greater than or equal to that of the receiving reference clock signal, and the sampling reference clock signal and the receiving reference clock signal have the same frequency.

9. The apparatus of claim 6, wherein the signal delay module delays the received reference clock signal according to an input delay control signal, the delay value is configurable, and the configuration requirement is:

the delay value is greater than or equal to a delay calculation value and is an integral multiple of a delay unit of the delayer, and the calculation process of the delay calculation value is as follows: and dividing the maximum delay in the delays of all channels by the delay unit of the delayer, rounding up the calculated value, and multiplying by the delay unit of the delayer.

10. The apparatus for multi-channel high-speed data alignment according to claim 6, wherein when the data caching module caches the recovered data, the cache data depth satisfies the following requirement:

the cache data depth of each channel is independently designed, the cache data depth of each channel is an integer which is greater than or equal to the calculated value of the cache depth of the channel, and the calculation process of the calculated value of the cache depth of each channel is as follows: subtracting the channel delay from the delay value, multiplying by a single-channel sampling rate, and rounding up the calculated value;

the single-channel sampling rate is the sampling reference clock signal frequency multiplied by the number of sampling points sampled at one time.

Technical Field

The invention relates to the technical field of communication, in particular to a method and a device for aligning multi-channel high-speed data.

Background

In the field of communications, high-speed data is transmitted in a serial manner through a high-speed driving device and a high-speed receiving device, for example, a serial transmitting and receiving part of Serdes (Serializer; Deserializer), and parallel-to-serial conversion is performed on received parallel data at a transmitting side Serdes, and then the parallel data is transmitted through a serial transmitting part; at the receiving side, a receiving section recovers a clock and data from the received serial data and then performs serial-to-parallel conversion.

Currently, for transmission rates below 10Gbps (10 gbits per Second), corresponding serial transmitting and receiving devices can be found for transmission. However, when the transmission rate is further increased, for example, 25Gbps and 40Gbps, the requirement of bandwidth cannot be met by using one-channel serial transmission (also called single channel). For this reason, the related art has been to group data and then perform parallel transmission using multiple paths. This type of multiplexing is also referred to as multi-channel data transmission, where each channel is also referred to as a channel. At the transmitting side, each channel independently transmits the allocated data, and after each channel at the receiving side receives the data, the channels are restored together to transmit the data.

Under the condition of adopting multi-channel transmission, data has certain correlation, and due to the inconsistency of transmission paths among channels and the inconsistency of processing, the data of each channel is not aligned, the correlation of the data is influenced, and further the delay and the jitter of the data are influenced. At present, the method for aligning such multi-channel transmission is mostly a method of adding an alignment mark in transmission data (in-band), that is, a transmitting side adds an alignment mark in each channel of data, and a receiving side aligns data according to the alignment mark. However, the main disadvantage of this approach is the complexity of the circuit design, the addition of the alignment mark increases the transmission overhead, and has a detrimental effect on the delay and jitter of the data transmission.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a method and an apparatus for aligning multi-channel high-speed data, which can effectively reduce and determine the delay and jitter introduced by the method and apparatus while implementing multi-channel high-speed data alignment, and meet the requirements of practical applications.

To achieve the above object, the present invention provides a method for multi-channel high-speed data alignment, comprising the following steps:

generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; delaying a receiving reference clock signal according to an input delay control signal to generate a delay receiving reference clock signal;

each channel of the transmitting side samples input data according to the sampling clock signal from each rising edge of the sampling reference clock signal; and sending the sampled data to a receiving side;

and each channel at the receiving side recovers and buffers the sampled data, and reads and sends the data out of the buffer according to the receiving clock signal from each rising edge of the delayed receiving reference clock signal.

On the basis of the technical scheme, according to the input control signal, a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal are generated in a mode of frequency multiplication and/or frequency division of a reference clock.

On the basis of the above technical solution, the periods of the sampling clock signal, the sampling reference clock signal, the receiving clock signal, and the receiving reference clock signal may be configured, and the configuration requirement is:

the frequency of the sampling clock signal is greater than or equal to that of the sampling reference clock signal, the frequency of the receiving clock signal is greater than or equal to that of the receiving reference clock signal, and the sampling reference clock signal and the receiving reference clock signal have the same frequency.

On the basis of the technical scheme, the method delays the received reference clock signal according to the input delay control signal, the delay value is configurable, and the configuration requirement is as follows:

the delay value is greater than or equal to a delay calculation value and is an integral multiple of a delay unit of the delayer, and the calculation process of the delay calculation value is as follows: and dividing the maximum delay in the delays of all channels by the delay unit of the delayer, rounding up the calculated value, and multiplying by the delay unit of the delayer.

On the basis of the technical scheme, when each channel on the receiving side caches the sampling data, the cache depth of each channel data is independently calculated, and the following requirements are met respectively:

the depth of each channel cache data is an integer which is greater than or equal to the calculated value of the channel cache depth, and the calculation process of the calculated value of the channel cache depth is as follows: subtracting the channel delay from the delay value, multiplying by a single-channel sampling rate, and rounding up the calculated value; the single-channel sampling rate is the sampling reference clock signal frequency multiplied by the number of sampling points sampled at one time.

The invention also provides a device for aligning multi-channel high-speed data, which comprises a control side, a sending side and a receiving side;

the control side comprises a signal generating module and a signal delay module; the signal generation module is configured to: generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; the signal delay module is configured to: delaying a receiving reference clock signal according to an input delay control signal to generate a delay receiving reference clock signal;

the transmitting side comprises a plurality of groups of data sampling modules and transmitting drivers, and each group corresponds to one transmitting channel; the data sampling module is configured to: sampling input data according to the sampling clock signal from each rising edge of the sampling reference clock signal, and sending the sampled data to a sending driver; the transmit driver is to: sending the sampled data to a receiving side;

the receiving side comprises a plurality of groups of receivers, a data clock recovery module and a data cache module, wherein each group corresponds to a receiving channel; the receiver is configured to: receiving sampling data sent by a sending driver; the data clock recovery module is configured to: recovering the sampled data; the data caching module is configured to: and buffering the recovered data, and reading and sending the data out of the buffer according to the receiving clock signal from each rising edge of the delayed receiving reference clock signal.

On the basis of the technical scheme, the signal generation module generates a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal in a mode of frequency multiplication and/or frequency division of the reference clock.

On the basis of the above technical solution, the periods of the sampling clock signal, the sampling reference clock signal, the receiving clock signal and the receiving reference clock signal generated by the signal generation module are configurable, and the configuration requirements are as follows:

the frequency of the sampling clock signal is greater than or equal to that of the sampling reference clock signal, the frequency of the receiving clock signal is greater than or equal to that of the receiving reference clock signal, and the sampling reference clock signal and the receiving reference clock signal have the same frequency.

On the basis of the above technical solution, the signal delay module delays the received reference clock signal according to the input delay control signal, and the delay value is configurable, and the configuration requirement is:

the delay value is greater than or equal to a delay calculation value and is an integral multiple of a delay unit of the delayer, and the calculation process of the delay calculation value is as follows: and dividing the maximum delay in the delays of all channels by the delay unit of the delayer, rounding up the calculated value, and multiplying by the delay unit of the delayer.

On the basis of the technical scheme, when the data caching module caches the recovered data, the caching data depth meets the following requirements:

the cache data depth of each channel is independently designed, the cache data depth of each channel is an integer which is greater than or equal to the calculated value of the cache depth of the channel, and the calculation process of the calculated value of the cache depth of each channel is as follows: subtracting the channel delay from the delay value, multiplying by a single-channel sampling rate, and rounding up the calculated value; the single-channel sampling rate is the sampling reference clock signal frequency multiplied by the number of sampling points sampled at one time.

The invention has the beneficial effects that:

(1) the invention utilizes the mode of carrying out control by an out-of-band transmission control signal, wherein the control signal comprises a clock generation sampling clock signal, a sampling reference clock signal, a receiving reference clock signal and a delay receiving reference clock signal, so that different channels of a transmitting side can synchronously sample different input data, and different channels of a receiving side can synchronously read and send the data, thereby realizing the alignment processing of multi-channel high-speed data. Meanwhile, the invention delays the receiving reference clock signal according to the input delay control signal, thereby generating a delay receiving reference clock signal; each channel of the receiving side receives the reference clock signal according to the same time delay and synchronously reads and sends the data out of the cache, thereby achieving the purpose of controllable time delay, ensuring that the transmitted data has deterministic time delay and the time delay is consistent after each power-on.

Compared with the mode of adding the alignment mark in the transmission data (in-band) adopted by the related technology, the invention does not need to insert the alignment mark, reduces the transmission overhead and has simple circuit design; and the delay and jitter of data transmission can not be additionally introduced, so that the delay and jitter introduced by the method can be effectively reduced and determined while the multichannel high-speed data alignment is realized, and the requirements of practical application are met.

(2) In the invention, the receiving reference clock is delayed, and the delay value is configurable and meets certain configuration requirements. When the configured delay is equal to the delay calculation value, the whole device has the minimum delay.

(3) In the invention, the cache data depth is designed, so that the depth of the data cache required by each path is minimum, and each path cache is calculated independently. When the device has the minimum delay, the required buffer depth of each path only needs to accommodate the data transmitted in the configuration delay and the delay difference time of the channel.

(4) The periods of a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal can be configured; the delay value of the delayed reception reference clock signal relative to the reception reference clock signal is configurable, so that flexible configuration can be performed according to the link delay of an application scene, and high adaptability is achieved.

(5) With the increase of signal rate, the difficulty of wiring the alignment relationship between multiple high-speed signal lines on a single Board of a PCB (Printed Circuit Board) is increasing, and usually a method of delaying time between equal-length high-speed signal lines is required to be adopted for processing. In the invention, because the synchronous sampling and synchronous sampling recovery modes are adopted, the requirement of time delay among high-speed signal wires with equal length can be reduced.

Drawings

FIG. 1 is a flow chart of a method of multi-channel high speed data alignment in an embodiment of the invention;

FIG. 2 is a schematic diagram of control signals generated in one example;

FIG. 3 is a timing diagram of data and signals in one example;

FIG. 4 is a block diagram of an apparatus for multi-channel high-speed data alignment according to an embodiment of the present invention.

Detailed Description

As communication rates become higher, a multi-channel parallel approach is required to support the high bandwidth requirement. In the case of multi-channel transmission, data between multiple channels has correlation. However, due to the inconsistency of transmission paths and processing among multiple channels, data has different transmission delays, and it is necessary to align the data of each channel. Also, some communication scenarios have deterministic latency requirements (i.e., latency and jitter errors) that are increasingly high as communication rates increase, and the latency and jitter introduced by using multiple channels for parallel transmission are reduced and determined.

In the prior art, a method of adding an alignment mark in transmission data (in-band) is adopted to achieve the purpose of aligning data of each channel, that is, a transmitting side adds an alignment mark in each path of data, and a receiving side performs data alignment according to the alignment mark. However, the main disadvantage of this approach is the complexity of the circuit design, the addition of the alignment mark increases the transmission overhead, and has a detrimental effect on the delay and jitter of the data transmission.

Aiming at the problem of how to effectively reduce and determine the introduced delay and jitter in the process of multichannel high-speed data alignment, the invention aims to provide a method and a device for multichannel high-speed data alignment, which can realize multichannel high-speed data alignment and simultaneously enable transmission data to have less deterministic delay so as to meet the requirements of practical application.

In order to achieve the purpose, the main design idea of the invention is as follows: generating a sampling clock signal, a sampling reference clock signal, a receiving clock signal and a receiving reference clock signal according to an input control signal and a reference clock; and delaying the receiving reference clock signal according to the input delay control signal to generate a delay receiving reference clock signal. Each channel on the transmission side samples input data according to a sampling clock signal, starting at each rising edge of a sampling reference clock. And each channel at the receiving side recovers and buffers the sampled data, and reads and sends the data out of the buffer according to the receiving clock from each rising edge of the delayed receiving reference clock signal.

In the scheme, the control mode is carried out by utilizing the out-of-band transmission control signal, and the control signal comprises a sampling clock signal, a sampling reference clock signal, a receiving reference clock signal and a delayed receiving reference clock signal, so that different channels of a transmitting side can synchronously sample different input data, and different channels of a receiving side can synchronously read and send out data, thereby realizing the alignment processing of multi-channel high-speed data. Meanwhile, the purpose of controllable delay can be achieved by delaying the received reference clock signal, so that the transmitted data has deterministic delay and the delay is consistent after each power-on.

Compared with the mode of adding the alignment mark in the transmission data (in-band) adopted by the related technology, the invention does not need to insert the alignment mark, reduces the transmission overhead and has simple circuit design; and the delay and jitter of data transmission can not be additionally introduced, so that the delay and jitter introduced by the method can be effectively reduced and determined while the multichannel high-speed data alignment is realized, and the requirements of practical application are met.

In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

However, it should be noted that: the examples to be described next are only some specific examples, and are not intended to limit the embodiments of the present invention necessarily to the following specific steps, values, conditions, data, orders, and the like. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.