阅读说明：本技术 使用电流模式逻辑的pvt鲁棒性mod 3分频器 (PVT robust MOD 3 frequency divider using current mode logic ) 是由 T·海勒 J·沃诺博伊 于 2020-03-11 设计创作，主要内容包括：本发明题为“使用电流模式逻辑的PVT鲁棒性MOD 3分频器”。本公开提供了一种例示性数字锁存器,该数字锁存器包括：差分晶体管对(“跟踪对”),该差分晶体管对电容耦合到差分输入信号以当时钟信号生效时引起在输出节点之间的差分输出电压来跟踪差分输入信号；交叉耦合晶体管对(“锁存对”),该交叉耦合晶体管对耦合到输出节点以当时钟信号解除生效时锁存差分输出电压；差分晶体管对(“时钟对”),该差分晶体管对引导在跟踪对与锁存对之间的偏置电流；以及匹配偏置晶体管组,该匹配偏置晶体管组确定时钟对的偏置电流和在基准电压节点上的基准电压,该基准电压节点以相等偏置电阻耦合到跟踪对中的每个晶体管的基极。(The invention provides a PVT robust MOD 3 frequency divider using current mode logic. The present disclosure provides an exemplary digital latch comprising: a differential transistor pair ("tracking pair") capacitively coupled to the differential input signal to cause a differential output voltage between the output nodes to track the differential input signal when the clock signal is asserted; a pair of cross-coupled transistors ("latch pair") coupled to the output nodes to latch the differential output voltage when the clock signal is deasserted; a differential transistor pair ("clock pair") that conducts a bias current between the tracking pair and the latching pair; and a set of matched bias transistors that determine a bias current for the clock pair and a reference voltage on a reference voltage node coupled with equal bias resistance to the base of each transistor in the tracking pair.)

1. An integrated circuit on a semiconductor substrate, the integrated circuit comprising a digital latch, the digital latch comprising:

a differential transistor pair, the differential transistor pair being a tracking pair, the differential transistor pair capacitively coupled to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted;

a cross-coupled transistor pair that is a latch pair that is coupled to the output node to latch the differential output voltage when the clock signal is deasserted;

a differential transistor pair that is a clock pair that directs a bias current between a shared emitter node of the tracking pair and a shared emitter node of the latching pair in response to the clock signal; and

a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, the matched set comprising:

a first bias transistor that determines the bias current of the clock pair; and

a second bias transistor that sources or sinks an equal bias current through a load resistor to determine a reference voltage at a reference voltage node,

the reference voltage node is coupled to the base of each transistor in the tracking pair by a bias resistance proportional to each of the base resistances to provide a bias voltage.

2. The integrated circuit of claim 1, wherein the voltage on the shared bias voltage node is determined by a bandgap voltage reference.

3. The integrated circuit of claim 1, wherein each of the output nodes is coupled to a supply voltage by a pull-up resistance equal to the load resistance.

4. The integrated circuit of claim 1, wherein the digital latch further comprises a first pair of emitter-follower configured transistors that amplify the clock signal to drive gates of transistors in the clock pair, the emitter-follower configured transistors being biased by respective bias transistors in the matched set.

5. The integrated circuit of claim 4, wherein the digital latch further comprises a second pair of emitter-follower configured transistors that buffer the differential output voltage for output, the emitter-follower configured transistors of the second pair each biased by a respective bias transistor in the matched set.

6. The integrated circuit of claim 1, wherein at least one of the transistors in the clock pair is implemented in a triple-well architecture, and wherein the integrated circuit further comprises a choke resistor that reverse biases an isolation well in the triple-well architecture.

7. The integrated circuit of any of claims 1-6, further comprising:

a first master latch coupled to provide the differential input signal to the digital latch to implement a first flip-flop; and

a second flip-flop, the second flip-flop comprising:

a second master latch; and

a slave latch capacitively coupled to receive an output from the second master latch and coupled to provide a capacitively coupled differential input signal to the first master latch.

8. The integrated circuit of claim 7, wherein the second master latch is capacitively coupled to receive a first output signal from the digital latch and capacitively coupled to receive a second output signal from the slave latch, and wherein the second master latch produces a third output signal that is a logical negation of the first output signal and the second output signal.

9. An integrated circuit on a semiconductor substrate, the integrated circuit comprising a modified digital latch, the modified digital latch comprising:

an input transistor arrangement, the input transistor arrangement comprising:

a first input transistor having a base capacitively coupled to receive a first input signal;

a second input transistor having a base capacitively coupled to receive a second input signal; and

a complementary transistor having a base capacitively coupled to a fixed voltage node, the input transistor arrangement producing a differential output voltage between output nodes when a clock signal is asserted, the differential output voltage representing a logical NOR of the first input signal and the second input signal;

a cross-coupled transistor pair that is a latch pair, the cross-coupled transistor pair coupled to the output node to latch the differential output voltage when the clock signal is deasserted;

a differential transistor pair that is a clock pair that directs a bias current between a shared emitter node of a tracking pair and a shared emitter node of the latching pair in response to the clock signal; and

a matched set of bias transistors each having a base coupled by a respective base resistance to a shared bias voltage node, said matched set comprising:

a first bias transistor that determines a bias current of the clock pair; and

a second bias transistor that sources or sinks an equal bias current through a load resistor to determine a reference voltage at a reference voltage node,

the reference voltage node is coupled to the base of each transistor in the input transistor arrangement by a bias resistance proportional to each of the base resistances to provide a bias voltage.

10. The integrated circuit of claim 9, further comprising:

a slave latch coupled to the modified digital latch to implement a flip-flop that provides a differential output between a positive output node and a negative output node.

11. The integrated circuit of claim 10, wherein the positive output node is coupled to the first input transistor as the first input signal, and wherein the modified digital latch further comprises a third input transistor having a base capacitively coupled to the negative output node to match a load of the positive output node.

Technical Field

The present disclosure relates to circuits for frequency division, and more particularly to a modulo three frequency divider using current mode logic implemented in a manner that reduces sensitivity to process, voltage, and temperature variations.

Background

The frequency divider is typically implemented as a digital state machine. Alternatives to digital logic dividers include Injection Locked Frequency Dividers (ILFD) and regenerative frequency dividers (also known as miller dividers). However, ILFD generally has a narrow, process sensitive frequency range. Regenerative dividers are not suitable for the case of modulus values of 3, which is the focus of this document. For prescaler dividers, the modulus is typically 2 or 3, with higher values obtained using a cascade of several dividers. The required modulus value 3 is typically derived from a combination of factors including the frequency of the reference oscillator, the operating frequency band, and constraints associated with the delta-sigma modulator. For example, design constraints for a high frequency fractional-N phase-locked loop suitable for use in a 20GHz chirp synthesizer in an automotive radar environment may require a modulo-3 divider at the output of a Voltage Controlled Oscillator (VCO).

At relatively low frequencies, the divider may be implemented using standard CMOS (complementary metal oxide silicon) logic. At input frequencies above the said 2GHz, standard CMOS logic does not perform satisfactorily. For high frequencies, faster Current Mode Logic (CML) is preferred. This preference is particularly pronounced for digital modulo-3 dividers, which are inherently slower than similar digital modulo-2 dividers. A modulo-2 divider may be implemented using a single delay flip-flop, whereas a modulo-3 divider requires a chain of two such flip-flops and nor gates.

The maximum operating frequency of the CML divider is approximately proportional to the inverse of the total open loop delay of the CML block. While techniques exist to minimize CML block delay and thereby increase the maximum operating frequency, they typically incur one or more of the following adverse consequences: (a) low yield due to process variation sensitivity and device mismatch; (b) failure at elevated temperatures; (c) sensitivity of performance to supply voltage variations; and (d) equipment reliability decreases, resulting in a low Mean Time To Failure (MTTF).

Disclosure of Invention

Thus, there are Current Mode Logic (CML) modulo 3 frequency dividers and frequency dividing methods that enable an improved trade-off between yield, sensitivity to temperature and supply voltage variations, reliability, and maximum operating frequency.

According to one aspect of the present disclosure there is provided an integrated circuit on a semiconductor substrate, the integrated circuit characterised in that it comprises a digital latch comprising: a differential transistor pair ("tracking pair") capacitively coupled to the differential input signal to cause a differential output voltage between the output nodes to track the differential input signal when the clock signal is asserted; a pair of cross-coupled transistors ("latch pair") coupled to the output nodes to latch the differential output voltage when the clock signal is deasserted; a differential transistor pair ("clock pair") that, in response to a clock signal, directs a bias current between the shared emitter node of the tracking pair and the shared emitter node of the latching pair; and a set of matched bias transistors each having a base coupled with a respective base resistance to a shared bias voltage node, the set of matched transistors comprising: a first bias transistor that determines a bias current of the clock pair; and a second biasing transistor that sources or sinks an equal biasing current through a load resistor to determine a reference voltage on a reference voltage node coupled to the base of each transistor in the tracking pair with a biasing resistance proportional to each of the base resistances to provide a biasing voltage.

In one embodiment, the integrated circuit is characterized in that the voltage on the shared bias voltage node is determined by a bandgap voltage reference.

In one embodiment, the integrated circuit is characterized in that each of the output nodes is coupled to the supply voltage with a pull-up resistance equal to the load resistance.

In one embodiment, the integrated circuit is characterized in that the digital latch further comprises a first pair of emitter-follower configured transistors that amplify the clock signal to drive gates of the transistors in the clock pair, the emitter-follower configured transistors being biased by respective bias transistors in the matched set.

In one embodiment, the integrated circuit is characterized in that the digital latch further comprises a second pair of emitter-follower configured transistors, the second pair of emitter-follower configured transistors buffering the differential output voltage for output, the emitter-follower configured transistors of the second pair being biased by respective bias transistors in the matched set.

In one embodiment, the integrated circuit is characterized in that at least one of the transistors in the clock pair is implemented in a triple well architecture, and wherein the integrated circuit further comprises a choke resistor that reverse biases the isolation well in the triple well architecture.

In one embodiment, the integrated circuit is characterized in that it further comprises: a first master latch coupled to provide the differential input signal to the digital latch to implement a first flip-flop; and a second flip-flop, the second flip-flop comprising: a second master latch; and a slave latch capacitively coupled to receive an output from the second master latch and coupled to provide a capacitively coupled differential input signal to the first master latch.

In one embodiment, the integrated circuit is characterized in that the second master latch is capacitively coupled to receive the first output signal from the digital latch and capacitively coupled to receive the second output signal from the slave latch, and wherein the second master latch produces a third output signal that is a logical nor of the first output signal and the second output signal.

According to another aspect of the present disclosure there is provided an integrated circuit on a semiconductor substrate, the integrated circuit being characterised in that it comprises a modified digital latch comprising: an input transistor arrangement, the input transistor arrangement comprising: a first input transistor having a base capacitively coupled to receive a first input signal; a second input transistor having a base capacitively coupled to receive a second input signal; and a complementary transistor having a base capacitively coupled to the fixed voltage node, the input transistor arrangement producing a differential output voltage between the output nodes when the clock signal is asserted, the differential output voltage representing a logical nor of the first input signal and the second input signal; a pair of cross-coupled transistors ("latch pair") coupled to the output nodes to latch the differential output voltage when the clock signal is deasserted; a differential transistor pair ("clock pair") that, in response to a clock signal, directs a bias current between the shared emitter node of the tracking pair and the shared emitter node of the latching pair; and a set of matched bias transistors each having a base coupled with a respective base resistance to a shared bias voltage node, the set of matched transistors comprising: a first bias transistor that determines a bias current of the clock pair; and a second biasing transistor that sources or sinks an equal biasing current through the load resistance to determine a reference voltage on a reference voltage node coupled to the base of each transistor in the input transistor arrangement with a biasing resistance proportional to each of the base resistances to provide a biasing voltage.

In one embodiment, the integrated circuit is characterized in that it further comprises: a slave latch coupled to the modified digital latch to implement a flip-flop that provides a differential output between the positive and negative output nodes.

In one embodiment, the integrated circuit is characterized in that the positive output node is coupled as a first input signal to a first input transistor, and wherein the modified digital latch further comprises a third input transistor having a base capacitively coupled to the negative output node to match the load of the positive output node.

Drawings

Fig. 1A is a block diagram of an exemplary digital modulo 3 frequency divider.

Fig. 1B is a block diagram of an exemplary delay flip-flop.

FIG. 1C is a block diagram of an exemplary delay flip-flop with an integrated NOR logic gate.

FIG. 1D is a schematic diagram of an exemplary Current Mode Logic (CML) latch.

FIG. 1E is a schematic diagram of an exemplary CML latch with integrated NOR logic gates.

Fig. 1F is a side view of an exemplary triple well architecture.

Fig. 2 is a block diagram of an exemplary digital modulo 3 frequency divider with output signal balancing.

Fig. 3 is a side view of an exemplary triple well architecture with choke resistance biasing.

FIG. 4 is a schematic diagram of an exemplary latch with AC input coupling and enhanced biasing.

Fig. 5 is a schematic diagram of an exemplary nor input latch with a dummy load.

It should be understood that the drawings and corresponding detailed description do not limit the disclosure, but on the contrary, provide a basis for understanding all modifications, equivalents, and alternatives falling within the scope of the appended claims.

Detailed Description

Fig. 1A is a block diagram of an exemplary digital modulo 3 frequency divider. The frequency divider is implemented as a digital state machine using two flip-flops (FF1, FF2) in combination with a nor logic gate. The flip-flops of the illustrated frequency divider accept differential signals at their clock and data inputs, and one or both of the flip-flops provide the differential signal as their state outputs. Differential frequency signal f_inIs provided to the clock input of flip-flop FF1 and is provided in inverted form to the clock input of flip-flop FF2 such that the two flip-flops alternately latch. The data input D of flip-flop FF1 is the state output Q of flip-flop FF 2. The nor logic gate combines the state output Q from the flip-flop FF1 with the state output Q from the flip-flop FF2 to generate a differential signal NOT (Q)_FF1Or Q_FF2) The differential signal is provided to the data input D of flip-flop FF 2. In one contemplated implementation, the nor logic gate generates a differential output signal from a single-ended input. At the input frequency signal f_inIn oscillation, the state output Q from FF2 is used as the output frequency signal f_outFor input signal f_inThe signal is asserted once every three cycles to provide the desired division modulo 3.

Each of the flip-flops FF1, FF2 may be implemented with a master latch and a slave latch. FIG. 1B is a block diagram of flip-flop FF1 showing the coupling of the state output Q of the master latch to the data input D of the slave latch, and the input frequency signal f_inCoupled to the clock input of the master latch and coupled in an inverted manner to the clock input of the slave latch. The latches operate alternately, with the slave latch holding and driving the state output Q of the flip-flop and the master latch acquiring the data input D of the flip-flop, and the master latch holding and driving the acquired data input and the slave latch acquiring the data input of the flip-flop.

Instead of implementing flip-flop FF2 in exactly the same manner, FF2 is implemented with a modified master latch as shown in fig. 1C. The modified master latch incorporates the function of a nor logic gate; thus, data input D is replaced by nor logic inputs a and B. This modification reduces the open loop delay of the divider and achieves a higher maximum operating frequency. Just as with FIG. 1B, the state output Q of the master latch is coupled to the data input D of the slave latch and the input frequency signal f is inverted_inCoupled to the clock input of the master latch and coupled in a non-inverting manner to the clock input of the slave latch. The latches operate alternately, with the slave latch holding and driving the state output Q of the flip-flop, while the master latch takes the logically combined data input A, B of the flip-flop, and the master latch holding and driving the result of the nor operation taken, while the slave latch takes the result.

Thus, the illustrated embodiment of the frequency divider includes three "regular" latches and one modified latch with a NOR logic function integrated into its input circuit.

FIG. 1D is a schematic diagram of a "conventional" latch implemented using Current Mode Logic (CML). It includes a differential transistor pair Q1, Q2 that causes the output node X, Y to track the state of the data inputs + D, -D when the transistor Q5 is turned on. The differential transistor pair Q1, Q2 may be referred to as a "tracking pair" accordingly. Each of the output nodes X, Y is coupled between the output node and a supply voltage V_CCLoad resistor R in between_LAnd (4) biasing. The tracking pair transistors Q1, Q2 share a source node that is coupled by transistor Q5 to the current sink I when the clock signal CK is asserted_EE。

The latch also includes a cross-coupled transistor pair Q3, Q4 that latches the state of the output node X, Y when the transistor Q6 is turned on. The transistor pair Q3, Q4 may be referred to as a "latch pair" accordingly. The latch pair transistors Q3, Q4 share an emitter node that is coupled to the current sink I by transistor Q6 when the clock signal CK is deasserted_EE。

The transistors Q5, Q6 are responsive to the clock signal CK to switch the sink current between the tracking pair and the latching pair, thereby enabling the latch to alternately acquire and hold the differential data input signal D in the state of the output node X, Y.

Relatedly, FIG. 1E is a schematic diagram of a modified latch implemented using CML. In the modified latch, the tracking pair is modified to integrate or not function. The latch and clock pair is unchanged relative to the conventional latch implementation of fig. 1D.

The tracking pair modification is as follows: the base of transistor Q2 is coupled to a bias voltage Vb that is intermediate the voltages representing boolean "1" and boolean "0". In fig. 1E, transistor Q1 of the "conventional" latch implementation is replaced by two parallel transistors Q1 and Q1' having their bases coupled to the gate input signals a and B, respectively. If either input signal a or B (or both) is asserted when transistor Q5 is turned on, the output node X is pulled low, thereby performing a nor function. Otherwise, the output node is driven by a pull-up resistor R_LBut remains high. Due to differential configurationWhen transistor Q5 is turned on, output node Y moves in reverse direction to output node X, converting the gate output to a differential signal suitable for capture by the latch pair when transistor Q6 is turned on.

It should be noted that the input signals a and B are generated by flip-flops, while the bias voltage Vb is generated by a different circuit type that generally cannot ensure that the bias voltage is consistently equal to the average (DC) voltage of the input signal. In contrast, differences in physical mechanisms result in such mismatches being sensitive to supply voltage, temperature and process variations. For example, the bias voltage may be generated by reducing the reference current across a reference resistor, thereby making the bias voltage sensitive to supply voltage and resistor process variations. The input signal may be provided as the output of an emitter follower, resulting in its DC voltage being dependent on the transistor bias current and the base voltage, which in turn is indirectly dependent on its load resistor, supply voltage and temperature. The DC offset varies significantly over the expected range of supply voltage, temperature and process variations, and as the signal frequency increases and the input signal amplitude decreases, the latch pair becomes less sensitive to these effects.

In some embodiments, the clock pair transistors may be implemented as N-channel metal oxide semiconductor field effect transistors (nmosfets) to minimize their headroom requirements. It should be noted, however, that the clock pair transistor does not have its source grounded. To prevent undesired bulk effects, the clock pair transistors may be implemented using a triple well architecture similar to that shown in fig. 1F.

Figure 1F is a side view of an exemplary triple-well architecture in which the source and drain wells are contained within a p-type body well that is in turn defined on all sides by an n-type isolation well that isolates the transistor body from the p-type substrate. To isolate the bulk well from the substrate, the isolation well is reverse biased with respect to the bulk well and the substrate. FIG. 1F shows the substrate connected to ground and the isolation well connected to a supply voltage V_DD. (the voltage of the bulk well will not exceed the supply voltage V_DD. ) When a positive voltage is applied to the gate, negative charge carriers accumulate under the oxide, forming a conductive n-channel between the source and drain. According to industry practiceThe source is also provided with an ohmic connection (via the P + well) to the bulk well. Note that the triple well architecture can be modeled using a pair of reverse biased parasitic diodes that separate the body well from the substrate. This representation will be used in the following schematic.

The reverse biased diode exhibits a capacitive behavior for high frequency signals. It is observed here that the isolation well is connected to a supply voltage V_DDProviding a low impedance path that can result in significant signal attenuation at high frequencies. To address this and other problems caused by the simple implementation set forth above, various enhancements are now set forth to provide a modulo-3 divider to enhance robustness to PVT (process, voltage, and temperature) variations.

Fig. 2 is a block diagram of an exemplary digital modulo 3 frequency divider with output signal balancing. Unlike the embodiment of fig. 1A in which the nor logic gate unbalances the load between the output signal nodes, the embodiment of fig. 2 employs a modified flip-flop FF2 that rebalances the load of the output signal nodes with a dummy load input d that matches the input impedance of the input signal a. An exemplary implementation of the dummy load is described below with reference to the schematic diagram of fig. 5.

However, before turning to the schematic diagram, a preferred biasing technique for the triple-well architecture as shown in figure 3 is first discussed. The embodiment of fig. 3 does not use a supply voltage V_DDInstead of using a choke resistor Rch to couple the supply voltage to the isolation well. As long as the choke resistance is comparable in magnitude to or larger than the impedance of the parasitic diode capacitance at the operating frequency, the overall impedance of the leakage path is almost doubled and the attenuation of the high frequency signal is significantly reduced. (further improvements can be made by reducing the bulk conductivity of the substrate, thereby increasing the impedance of the path from the bulk well to ground via the isolation well and the substrate.) the choke resistance is preferably set as high as possible while still ensuring that the isolation well is reverse biased over the expected source and drain voltage swings of the clock-pair transistor.

In some contemplated embodiments, each of the clock pair transistors has its own isolation well, such that a choke resistor is used for each isolation well. In other contemplated embodiments, a single isolation well is used for both clock pair transistors, thereby using only a single choke resistor.

In the context of the foregoing, turning now to FIG. 4, this figure is a schematic diagram of an exemplary latch with AC input coupling and enhanced biasing. The illustrative latch implementation may be used to implement each of the three "regular" latches in the modulo-3 frequency divider of fig. 2. The tracking pair transistors Q0, Q1 have their bases coupled to the data input through an AC coupling capacitor Ca. The DC bias to the tracking pair transistor base is provided from the reference node Vr via the base resistor Rb. The voltage of the reference node Vr is derived from the supply voltage V by using one of the bias transistor groups_CCDrawing current through a load resistor R_LTo be determined. To provide consistent performance that is more robust to PVT variations, each of the bias transistors is identically configured with its emitter grounded and its base coupled to the bias node Vb via a corresponding base resistor Rb, respectively. A temperature compensated bandgap voltage reference may be used to provide the voltage of the bias node Vb. Each of the base resistors are matched and each of the load resistors RL are matched to ensure that any PVT variations affect each of the circuit stages in a consistent manner, thereby maintaining performance matching.

The other of the bias transistor groups serves as a current sink for the clock pair transistors M0, M1. The base of clock pair transistor M0 receives a clock input from an emitter follower configured transistor that amplifies the negative clock input CK-, and the base of clock pair transistor M1 receives its clock input from a matched emitter follower configured transistor that amplifies the positive clock input CK +. The collectors of these emitter-follower configured transistors are coupled to a supply voltage V_CCAnd its emitter coupled to a corresponding bias transistor in the set of matched bias transistors. As discussed with reference to fig. 3, the clock pair transistors M0, M1 are implemented in a triple well architecture using a choke resistor RC to reverse bias their isolation wells with respect to their body wells (and with respect to the substrate). Schematic diagramIncluding a representation of the parasitic diodes modeling this reverse bias technique.

The load resistance RL of the output node X, Y matches the load resistance of the reference voltage node Vr. The transistor QX of the emitter follower configuration amplifies a signal from the output node X, thereby supplying the signal to the node Q +. The transistor QY of the emitter follower configuration amplifies a signal from the output node Y, thereby supplying the signal to the node Q-. The collectors of these emitter-follower configured transistors are coupled to a supply voltage V_CCAnd its emitter coupled to a corresponding bias transistor in the set of matched bias transistors.

As with the previous latch embodiments, the clock pairs alternately enable the tracking pair Q0, Q1 to obtain a differential signal from the data input node D +, D-and the latching pair Q2, Q3 to hold the signal on the output node Q +, Q-.

FIG. 5 is a schematic diagram of a latch implementing an exemplary modification of a NOR function and a dummy load. It shares many of the components of the embodiment of fig. 4, but the tracking pair transistor Q0 of fig. 4 is replaced by two transistors Q0a, Q0b having their collectors connected in parallel to the output node X and their emitters connected in parallel to the drain of the clock pair transistor M0. The base of transistor Q0a is coupled to signal input a through an AC coupling capacitor Ca, while the base of transistor Q0B is similarly coupled to signal input B through an AC coupling capacitor Ca. Each base is also coupled to a reference voltage node Vr through a base resistor Rb.

The complementary tracking pair resistor Q1 has its base coupled to ground through an AC coupling capacitance Cgnd and to the reference voltage node through a base resistor Rb. Since the data signal inputs in fig. 4 and 5 are AC coupled, they can be provided with a uniform reference voltage, thereby reducing sensitivity to PVT variations. Another advantage provided by AC coupling is that the reference voltage can be selected to provide a more robust bias to the clock-pair transistor and its corresponding bias transistor.

As with the previously described modified latch implementation, assertion of either signal input a or B (or both) causes the voltage at output node X to drop. The voltage at output node Y moves in anti-phase with the voltage at node X.

The schematic of fig. 5 also includes a dummy input d coupled to the base of transistor Q4 via an AC coupling capacitor Ca. This and each preceding capacitor Ca, Cgnd may be implemented as an on-chip metal-insulator-metal (MIM) plate capacitor. The base of transistor Q4 is also coupled to the reference voltage node Vr via a base resistor Rb. Transistor Q4 is biased by a load resistor RL coupling the collector to supply voltage Vcc and a bias transistor from a set of matched bias transistors coupling the emitter to ground to provide an input impedance that matches the input impedance of input signals a and B. The purpose of the dummy input is purely to provide an input impedance that is matched over the desired range of PVT variations, thereby reducing any load-induced variations on the positive and negative sides of the output signal of the frequency divider. Other embodiments providing similar load matching may also be used.

Thus, the following techniques are employed herein to provide potential advantages. (1) The tracking pair transistors Q0, Q1 and or the non-input transistors Q0a, Q0b are provided with uniform bias voltages with respect to each other and the complementary transistor Q1. (2) Increased leakage path impedance is provided by biasing the isolation well via a choke resistor. (3) Dummy loads are provided to balance the load of the differential output signal nodes of the frequency divider. Potential advantages include reduced sensitivity to PVT variations, reduced signal loss, and reduced phase and magnitude imbalance between output signals. Individually or in combination, these potential advantages may provide improved yield, reduced supply voltage sensitivity, improved reliability (longer mean time to failure), and higher maximum operating frequencies.

A modulo-3 divider with these advantages may improve the performance of a fractional-N synthesizer including a VCO, a reference clock, and a delta-sigma modulator controlled multi-modulus divider, because there are fewer constraints on the selection of VCO and reference clock frequencies, enabling an optimized design for better performance in terms of phase noise, frequency range, and other performance parameters. Furthermore, a simpler delta-sigma modulator may be employed, enabling higher frequency operation and reducing synthesizer phase noise. In the context of a chirp generator in an automotive radar application, lower phase noise results in better radar range and speed resolution.

The disclosed frequency divider may be implemented as an integrated circuit in silicon, SiGe, and other semiconductor substrate materials. These and many other modifications, equivalents, and alternatives will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications, equivalents, and alternatives as are appropriate.

In summary, the foregoing disclosure provides exemplary integrated circuit embodiments including digital latches and/or modified digital latches and methods of making the same. In one exemplary integrated circuit implementation, a digital latch comprises: a differential transistor pair ("tracking pair") capacitively coupled to the differential input signal to cause a differential output voltage between the output nodes to track the differential input signal when the clock signal is asserted; a pair of cross-coupled transistors ("latch pair") coupled to the output nodes to latch the differential output voltage when the clock signal is deasserted; a differential transistor pair ("clock pair") that, in response to a clock signal, directs a bias current between the shared emitter node of the tracking pair and the shared emitter node of the latching pair; and sets of matched bias transistors each having a base coupled with a respective base resistance to the shared bias voltage node. The matching group includes: a first bias transistor that determines a bias current of the clock pair; and a second biasing transistor that sources or sinks an equal biasing current through a load resistor to determine a reference voltage on a reference voltage node coupled to the base of each transistor in the tracking pair with a biasing resistance proportional to each of the base resistances to provide a biasing voltage.

In another exemplary embodiment, a modified digital latch comprises: an input transistor arrangement; latching the pair; a clock pair; and a matched bias transistor pair. The input transistor arrangement comprises: a first input transistor having a base capacitively coupled to receive a first input signal; a second input transistor having a base capacitively coupled to receive a second input signal; and a complementary transistor having a base capacitively coupled to the fixed voltage node, the input transistor arrangement producing a differential output voltage between the output nodes when the clock signal is asserted, the differential output voltage representing a logical nor of the first input signal and the second input signal. The latch pair is a cross-coupled transistor pair coupled to the output node to latch the differential output voltage when the clock signal is deasserted. The clock pair is a differential transistor pair that, in response to a clock signal, directs a bias current between the shared emitter node of the tracking pair and the shared emitter node of the latching pair. The matched bias transistor sets each having a base coupled with a respective base resistance to a shared bias voltage node, having: a first bias transistor that determines a bias current of the clock pair; and a second biasing transistor that sources or sinks an equal biasing current through the load resistance to determine a reference voltage on a reference voltage node coupled to the base of each transistor in the input transistor arrangement with a biasing resistance proportional to each of the base resistances to provide a biasing voltage.

In an exemplary method embodiment for fabricating a digital latch, the method comprises: capacitively coupling bases of a differential transistor pair ("tracking pair") to a differential input signal to cause a differential output voltage between output nodes to track the differential input signal when a clock signal is asserted; connecting a cross-coupled transistor pair ("latch pair") to the output nodes to latch the differential output voltage when the clock signal is deasserted; providing a differential transistor pair ("clock pair") that directs a bias current between the shared emitter node of the tracking pair and the shared emitter node of the latching pair in response to a clock signal; and biasing with sets of matched bias transistors each having a base coupled with a respective base resistance to the shared bias voltage node. The matching group includes: a first bias transistor that determines a bias current of the clock pair; and a second biasing transistor that sources or sinks an equal biasing current through a load resistor to determine a reference voltage on a reference voltage node coupled to the base of each transistor in the tracking pair with a biasing resistance proportional to each of the base resistances to provide a biasing voltage.

Each of the foregoing embodiments may be used with any one or more of the following optional features: 1. the voltage on the shared bias voltage node is determined by a bandgap or proportional temperature (PTAT) voltage reference. 2. Each of the output nodes is coupled to a supply voltage with a pull-up resistance equal to the load resistance. 3. A first pair of emitter-follower configured transistors that amplify the clock signal to drive gates of the transistors in the clock pair, the emitter-follower configured transistors being biased by respective bias transistors in the matched set. 4. A second pair of emitter-follower configured transistors buffering the differential output voltage for output, the emitter-follower configured transistors of the second pair being biased by respective bias transistors in the matched set. 5. At least one of the transistors in the clock pair is implemented with a triple well architecture. 6. A choke resistor that reverse biases an isolation well in a triple-well architecture. 7. A first master latch coupled to provide the differential input signal to the digital latch to implement a first flip-flop. 8. A second flip-flop, the second flip-flop comprising: a second master latch; and a slave latch capacitively coupled to receive an output from the second master latch and coupled to provide a capacitively coupled differential input signal to the first master latch. 9. The second master latch is capacitively coupled to receive the first output signal from the digital latch and is capacitively coupled to receive the second output signal from the slave latch. 10. The second master latch generates a third output signal that is a logical nor of the first output signal and the second output signal. 11. A slave latch coupled to the modified digital latch to implement a flip-flop that provides a differential output between the positive and negative output nodes. 12. The positive output node is coupled as a first input signal to the first input transistor, and wherein the modified digital latch further comprises a third input transistor having a base capacitively coupled to the negative output node to match a load of the positive output node. 13. Each of the output nodes is coupled to a supply voltage with a pull-up resistance equal to the load resistance. 14. Implementing a clock pair using a triple-well architecture; and reverse biasing the isolation well in the triple well architecture via the choke resistor. 15. Using bias transistors from the matched set to: biasing a first pair of emitter-follower configured transistors that amplify a clock signal to drive gates of the transistors in the clock pair; and biasing a second pair of emitter-follower configured transistors that amplify the differential output voltage for output.