阅读说明：本技术 Fifo数据传输方法及fifo存储装置 (FIFO data transmission method and FIFO storage device ) 是由 谭吉来 黄涛 刘雨婷 李瑞鹏 侯子超 王东琳 于 2020-07-02 设计创作，主要内容包括：本发明涉及一种FIFO数据传输方法及FIFO存储装置,属于数字电路设计领域,所述方法包括：每当转换模块输出非满信号且第一逻辑模块输出非空信号时,都会自动产生对前一级FIFO的读请求和对转换模块的写请求,形成数据搬移,使用寄存器优化RAM输出结构的时序性能,使用转换模块调整数据传输时序,转换模块也是先进先出的结构,依次输出写入的数据。本发明通过转换模块使FIFO在输出端口呈现“读使能作为取走数据的通知”的特性,使得读FIFO的数据输出延迟达到最低,可以减少关键路径相邻寄存器间逻辑延迟、隔离读使能信号与RAM读地址计算逻辑、有效优化FIFO时序、降低后端电路布线难度。(The invention relates to an FIFO data transmission method and an FIFO storage device, belonging to the field of digital circuit design, wherein the method comprises the following steps: when the conversion module outputs a non-full signal and the first logic module outputs a non-empty signal, a read request for a previous-stage FIFO and a write request for the conversion module are automatically generated to form data transfer, a register is used for optimizing the time sequence performance of an RAM output structure, the conversion module is used for adjusting the data transmission time sequence, the conversion module is also of a first-in first-out structure, and written data are sequentially output. The invention makes FIFO present the characteristic of 'read enable as the notice of taking away data' at the output port through the conversion module, makes the data output delay of reading FIFO reach the lowest, can reduce the logic delay between the adjacent registers of the key path, isolate read enable signal and RAM read address calculation logic, optimize FIFO time sequence effectively, reduce the wiring difficulty of the back end circuit.)

1. A FIFO data transmission method, which is applied to a FIFO storage device, comprises the following steps:

when the conversion module outputs a non-full signal and the first logic module outputs a non-empty signal, a read request to a previous stage FIFO and a write request to the conversion module are automatically generated to form data movement;

the RAM module reads out data stored in the current address according to the read pointer sent by the first logic module and writes the registered data into the conversion module in the next clock cycle through the register; optimizing the time sequence performance of the RAM module output structure by using a register in the data moving process, and adjusting the data transmission time sequence by using the conversion module;

the conversion module is also of a first-in first-out structure and sequentially outputs written data.

2. The FIFO data transmission method according to claim 1, wherein the conversion module is composed of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

3. The FIFO data transmission method according to claim 2, wherein the conversion module includes a second logic module and a second register, a first selector, a third register, a second selector, and a fourth register connected in series in this order;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

the data input terminal of the second register, a data input terminal of the first selector, and a data input terminal of the second selector may all receive data to be written.

4. The FIFO memory device is characterized by comprising a first logic module, a NOR gate, an RAM module, a first register and a conversion module; the first logic module is connected with the RAM module; a first input end of the nor gate is connected with an empty signal output end of the first logic module, a second input end of the nor gate is connected with a full signal output end of the conversion module, and output ends of the nor gate are respectively connected with a read enable end of the first logic module and a write enable end of the conversion module; the first register is respectively connected with the RAM module and the conversion module;

the conversion module is used for receiving a first read enable signal and judging whether the state of the conversion module is not full, if so, sending a non-full signal to the NOR gate, and otherwise, sending a full signal to the NOR gate;

the first logic module is used for judging whether the read pointer and the write pointer are equal, and if not, sending a non-null signal to the nor gate; if the two signals are equal, a null signal is sent to the NOR gate;

the nor gate is used for sending a second read enable signal to the first logic module and sending a second write enable signal to the conversion module after receiving the non-full signal and the non-empty signal;

the first logic module is further configured to send the read pointer to the RAM module after receiving the second read enable signal, add 1 to the read pointer, and point to a next address to be read;

the RAM module is used for reading out data stored in a current address according to the read pointer sent by the first logic module and sending the data to the first register;

the first register is used for carrying out register processing on the read data and writing the data into the conversion module in the next clock cycle;

the conversion module is of a first-in first-out structure and sequentially outputs written data.

5. The FIFO storage device of claim 4, wherein the conversion module is composed of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

6. The FIFO storage device of claim 5, wherein the conversion module comprises a second logic module and a second register, a first selector, a third register, a second selector and a fourth register connected in series in sequence;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

and the data input end of the second register, the data input end of the first selector and the data input end of the second selector are all connected with the data output end of the first register.

7. The FIFO memory device is characterized by comprising a first logic module, a NOR gate, a RAM module and a conversion module; the first logic module is connected with the RAM module; the RAM module comprises a fifth register, and the data output end of the fifth register is connected with the data input end of the conversion module; a first input end of the nor gate is connected with an empty signal output end of the first logic module, a second input end of the nor gate is connected with a full signal output end of the conversion module, and output ends of the nor gate are respectively connected with a read enable end of the first logic module and a write enable end of the conversion module;

the conversion module is used for receiving a first read enable signal and judging whether the state of the conversion module is not full, if so, sending a non-full signal to the NOR gate, and otherwise, sending a full signal to the NOR gate;

the first logic module is used for judging whether the read pointer and the write pointer are equal, and if not, sending a non-null signal to the nor gate; if the two signals are equal, a null signal is sent to the NOR gate;

the nor gate is used for sending a second read enable signal to the first logic module and sending a second write enable signal to the conversion module after receiving the non-full signal and the non-empty signal;

the first logic module is further configured to send the read pointer to the RAM module after receiving the second read enable signal, add 1 to the read pointer, and point to a next address to be read;

the RAM module is used for reading data stored in a current address according to the read pointer sent by the first logic module, performing register processing through the built-in fifth register, and writing the data into the conversion module in the next clock cycle;

the conversion module is of a first-in first-out structure and is also used for sequentially outputting written data.

8. The FIFO memory device of claim 7, wherein the conversion module is comprised of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

9. The FIFO memory device of claim 8, wherein the conversion module comprises a second logic module and a second register, a first selector, a third register, a second selector, and a fourth register serially connected in sequence;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

and the data input end of the second register, the data input end of the first selector and the data input end of the second selector are all connected with the data output end of the fifth register.

Technical Field

The invention relates to the technical field of digital integrated circuit design, in particular to an FIFO data transmission method and an FIFO storage device.

Background

With the expansion of the design scale of digital electronic systems and the increase of chip integration, complexity and functional requirements, some practical application systems often contain multiple clocks, and data is inevitably transferred between different clock domains.

The fifo (First In First out) is a First In First out memory adopting a ring memory structure, and uses a dual port memory to store data, the dual port memory has independent read and write ports, one end of the dual port memory is used for a data transmitting side In a write clock domain to write data, and the other end of the dual port memory is used for a data receiving side In a read clock domain to read data. The FIFO is used as a buffer area for data transmission in different clock domains, so that the time sequence requirement for data transmission in different clock domains becomes loose, and the transmission efficiency can be improved, therefore, the FIFO circuit is more and more widely applied to digital circuit systems.

Conventional RAM-based FIFO structures as shown in fig. 1, a read pointer (rdaddr) from a Logic module (Logic) is directly input to the RAM without being registered, and output data (dout) of the RAM is also directly output without being registered. The read enable signal of this configuration is coupled to the address and the logic path of the read enable signal is as shown in FIG. 2. If the address bit width of the FIFO is N, that is, the depth of the FIFO is 2N, the bit width of the Adder (Adder) and the numerical Comparator (Comparator) through which the read enable signal (rden) passes is N +1, so the rden path logic delay of the structure is large, which is not beneficial to increasing the main frequency. Moreover, the dout of the structure and the addressing logic of the RAM are directly output, so that the timing sequence of the dout port is poor; in the process of implementing back-end layout and wiring, as shown in fig. 3, the RAM often needs to be centrally laid out, so that the timing sequence of the dout port of the FIFO is indirectly worse, and the back-end wiring difficulty is higher.

With the development of integrated circuit technology, the process feature size is continuously reduced, the chip integration level and frequency are continuously improved, and the FIFO is used as an important module for transferring data across clock domains, and the port timing needs to be optimized as much as possible to meet the increasingly stringent timing requirements of integrated circuit chip design. However, the conventional FIFO structure based on the RAM has poor port timing and long critical path delay, which increases the difficulty of back-end wiring and hardly increases the operating frequency, and therefore, it is necessary to design a high-performance FIFO structure.

Disclosure of Invention

The invention aims to provide an FIFO data transmission method which has the characteristics of reducing logic delay between adjacent registers of a critical path, effectively optimizing FIFO time sequence and reducing wiring difficulty of a back-end circuit.

The above object of the present invention is achieved by the following technical solutions:

a FIFO data transmission method is applied to a FIFO storage device and comprises the following steps:

when the conversion module outputs a non-full signal and the first logic module outputs a non-empty signal, a read request to a previous stage FIFO and a write request to the conversion module are automatically generated to form data movement;

the RAM module reads out data stored in the current address according to the read pointer sent by the first logic module and writes the registered data into the conversion module in the next clock cycle through the register; optimizing the time sequence performance of the RAM module output structure by using a register in the data moving process, and adjusting the data transmission time sequence by using the conversion module;

the conversion module is also of a first-in first-out structure and sequentially outputs written data.

By adopting the technical scheme, the read enabling signal and the RAM read address calculation logic are isolated, after the read enabling signal is isolated by the conversion module, no direct combinational logic exists between the read enabling signal and the space and full judgment of the first logic module and the addressing logic of the RAM module, the combinational logic through which the read enabling signal passes is greatly reduced, the read enabling signal is deeply decoupled from the FIFO data, and the time delay of a key path can be reduced; moreover, the conversion module isolates the output of the RAM module from the output end of the FIFO structure, the FIFO time sequence is effectively optimized, the time sequence requirement of the read port is more friendly to the design of the connection structure of the rear-stage circuit, the wiring difficulty of the rear-stage circuit can be reduced, and the wiring realization of the circuit is facilitated; the method can be adopted to optimize the read port for both synchronous FIFO and asynchronous FIFO.

Preferably, the conversion module is composed of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

By adopting the technical scheme, the smooth operation of the FIFO can be ensured, namely, when the FIFO is not full and not empty in practice, the FIFO can be read and written once per period, and the data can be ensured to rapidly and smoothly pass through the FIFO structure.

Preferably, the conversion module comprises a second logic module, and a second register, a first selector, a third register, a second selector and a fourth register which are connected in series in sequence;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

the data input terminal of the second register, a data input terminal of the first selector, and a data input terminal of the second selector may all receive data to be written.

By adopting the technical scheme, the minimum depth of the best effect can be ensured to be 3.

The second purpose of the invention is to provide an FIFO storage device, which has the characteristics of reducing logic delay between adjacent registers of a key path, effectively optimizing FIFO time sequence and reducing wiring difficulty of a back-end circuit.

The second aim of the invention is realized by the following technical scheme:

a FIFO storage device comprises a first logic module, a NOR gate, an RAM module, a first register and a conversion module; the first logic module is connected with the RAM module; a first input end of the nor gate is connected with an empty signal output end of the first logic module, a second input end of the nor gate is connected with a full signal output end of the conversion module, and output ends of the nor gate are respectively connected with a read enable end of the first logic module and a write enable end of the conversion module; the first register is respectively connected with the RAM module and the conversion module;

the conversion module is used for receiving a first read enable signal and judging whether the state of the conversion module is not full, if so, sending a non-full signal to the NOR gate, and otherwise, sending a full signal to the NOR gate;

the first logic module is used for judging whether the read pointer and the write pointer are equal, and if not, sending a non-null signal to the nor gate; if the two signals are equal, a null signal is sent to the NOR gate;

the nor gate is used for sending a second read enable signal to the first logic module and sending a second write enable signal to the conversion module after receiving the non-full signal and the non-empty signal;

the first logic module is further configured to send the read pointer to the RAM module after receiving the second read enable signal, add 1 to the read pointer, and point to a next address to be read;

the RAM module is used for reading out data stored in a current address according to the read pointer sent by the first logic module and sending the data to the first register;

the first register is used for carrying out register processing on the read data and writing the data into the conversion module in the next clock cycle;

the conversion module is of a first-in first-out structure and is also used for sequentially outputting written data.

By adopting the technical scheme, the read enabling signal and the RAM read address calculation logic are isolated, after the read enabling signal is isolated by the conversion module, no direct combinational logic exists between the read enabling signal and the space and full judgment of the first logic module and the addressing logic of the RAM module, the combinational logic through which the read enabling signal passes is greatly reduced, the read enabling signal is deeply decoupled from the FIFO data, and the time delay of a key path can be reduced; moreover, the conversion module isolates the output of the RAM module from the output end of the FIFO structure, the FIFO time sequence is effectively optimized, the time sequence requirement of the read port is more friendly to the design of the connection structure of the rear-stage circuit, the wiring difficulty of the rear-stage circuit can be reduced, and the wiring realization of the circuit is facilitated; the device can be used for optimizing the read port for both synchronous FIFO and asynchronous FIFO.

Preferably, the conversion module is composed of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

By adopting the technical scheme, the smooth operation of the FIFO can be ensured, namely, the FIFO is actually not full and not empty, once reading and once writing operation can be carried out every period, and the data can be ensured to rapidly and smoothly pass through the FIFO structure.

Preferably, the conversion module comprises a second logic module, and a second register, a first selector, a third register, a second selector and a fourth register which are connected in series in sequence;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

and the data input end of the second register, the data input end of the first selector and the data input end of the second selector are all connected with the data output end of the first register.

By adopting the technical scheme, the minimum depth of the best effect can be ensured to be 3.

The third objective of the present invention is to provide an FIFO storage device having the features of reducing logic delay between adjacent registers of the critical path, effectively optimizing FIFO timing, and reducing wiring difficulty of the back-end circuit.

The third object of the invention is realized by the following technical scheme:

a FIFO storage device comprises a first logic module, a NOR gate, an RAM module and a conversion module; the first logic module is connected with the RAM module; the RAM module comprises a fifth register, and the data output end of the fifth register is connected with the data input end of the conversion module; a first input end of the nor gate is connected with an empty signal output end of the first logic module, a second input end of the nor gate is connected with a full signal output end of the conversion module, and output ends of the nor gate are respectively connected with a read enable end of the first logic module and a write enable end of the conversion module;

the conversion module is used for receiving a first read enable signal and judging whether the state of the conversion module is not full, if so, sending a non-full signal to the NOR gate, and otherwise, sending a full signal to the NOR gate;

the first logic module is used for judging whether the read pointer and the write pointer are equal, and if not, sending a non-null signal to the nor gate; if the two signals are equal, a null signal is sent to the NOR gate;

the nor gate is used for sending a second read enable signal to the first logic module and sending a second write enable signal to the conversion module after receiving the non-full signal and the non-empty signal;

the first logic module is further configured to send the read pointer to the RAM module after receiving the second read enable signal, add 1 to the read pointer, and point to a next address to be read;

the RAM module is used for reading data stored in a current address according to the read pointer sent by the first logic module, performing register processing through the built-in fifth register, and writing the data into the conversion module in the next clock cycle;

the conversion module is of a first-in first-out structure and sequentially outputs written data.

By adopting the technical scheme, the read enabling signal and the RAM read address calculation logic are isolated, after the read enabling signal is isolated by the conversion module, no direct combinational logic exists between the read enabling signal and the space and full judgment of the first logic module and the addressing logic of the RAM module, the combinational logic through which the read enabling signal passes is greatly reduced, the read enabling signal is deeply decoupled from the FIFO data, and the time delay of a key path can be reduced; moreover, the conversion module isolates the output of the RAM module from the output end of the FIFO structure, the FIFO time sequence is effectively optimized, the time sequence requirement of the read port is more friendly to the design of the connection structure of the rear-stage circuit, the wiring difficulty of the rear-stage circuit can be reduced, and the wiring realization of the circuit is facilitated; the device can be used for optimizing the read port for both synchronous FIFO and asynchronous FIFO.

Preferably, the conversion module is composed of at least three registers connected in series; and the read data port of the FIFO storage device is fixedly connected with one of the at least three registers and used as an output.

By adopting the technical scheme, the smooth operation of the FIFO can be ensured, namely, the FIFO is actually not full and not empty, once reading and once writing operation can be carried out every period, and the data can be ensured to rapidly and smoothly pass through the FIFO structure.

Preferably, the conversion module comprises a second logic module, and a second register, a first selector, a third register, a second selector and a fourth register which are connected in series in sequence;

the second logic module is respectively connected with an enabling control end of the second register, a selecting control end of the first selector, an enabling control end of the third register, a selecting control end of the second selector and an enabling control end of the fourth register;

and the data input end of the second register, the data input end of the first selector and the data input end of the second selector are all connected with the data output end of the fifth register.

By adopting the technical scheme, the minimum depth of the best effect can be ensured to be 3.

Drawings

FIG. 1 is a block diagram of a conventional RAM-based FIFO;

FIG. 2 is a schematic diagram of the read enable signal logic path of a conventional RAM-based FIFO;

FIG. 3 is a back-end layout schematic of a conventional RAM-based FIFO;

FIG. 4 is a schematic structural diagram of a FIFO memory device according to a second embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a RAM module according to a second embodiment of the present invention;

fig. 6 is a schematic structural diagram of a conversion module according to a second embodiment and a third embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a FIFO memory device according to a third embodiment of the present invention;

fig. 8 is a timing diagram for data transmission according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Moreover, the terms "first," "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The embodiments of the present invention will be described in further detail with reference to the drawings attached hereto.

The FIFO has two pointers: rd _ addr (read pointer) and wr _ addr (write pointer) to indicate the memory address where the FIFO is to be read or written. Initially the read/write pointer points to the initial address of the memory and each time a read/write operation is performed the corresponding pointer is incremented to point to the next address to be read/written. When the pointer moves to the last address of the memory, the read/write operation is performed again, and the corresponding pointer jumps back to the original address.

The FIFO has two indication signals: full and empty signals, indicating the empty and full status of the FIFO. In the case of a non-full or non-empty FIFO, the process continues with the change of the read/write enable signal. When the FIFO is full or is about to be full, a full signal is sent by the FIFO to prevent the write operation of the FIFO from continuing to write data into the FIFO causing an overflow (overflow). An empty signal is sent by the FIFO when the FIFO is empty or about to be empty to prevent a read operation of the FIFO from continuing to read data from the FIFO resulting in a read of invalid data (underflow).

The FIFO has two clocks: the read clock and the write clock, the clock followed for read/write operations, read/write data on each clock edge.

The peripheral interfaces of the FIFO can receive/output full, empty, wren, rden, resetn, wr _ data, dout, and the like, respectively.

The FIFO storage device comprises two stages of FIFO structures which are connected in series, wherein the FIFO structure at the previous stage comprises a first logic module and an RAM module, the FIFO structure belongs to a conventional FIFO structure, and the FIFO structure at the next stage is a conversion module.

The first logic module judges the empty and full state of the first-stage FIFO and sends a read/write pointer to the RAM module. The first logic module comprises a reset input end (resetn), a write enable end (wren), a full signal output end (full), a write pointer output end (Wr _ addr), a read pointer output end (Rd _ addr), an empty signal output end (empty) and a read enable end (rden). The full signal output end, the reset input end and the write enable end of the first logic module are respectively a full signal output end, a reset input end and a write enable end of the FIFO.

The conversion module is responsible for external handshake and data output of the read port; it can be regarded as a FIFO built by registers, the depth of which is determined by the number of registers that build the FIFO internally. The register can adopt a D trigger with a cache function, and the minimum number of fifth registers for ensuring the smooth operation of the FIFO is 3. The conversion module can be composed of at least three registers connected in series; the reading data port of the FIFO memory device is fixedly connected with one register of the at least three registers and used as an output.

The conversion block is a sub-block inside the FIFO, whose full only indicates the full state of the conversion block. The conversion module comprises an empty signal output end (empty), a read enable end (rden), a data output end (Q), a full signal output end (full), a data input end (D), a reset input end (resetn) and a write enable end (wren). The empty signal output end, the read enable end, the data output end and the reset input end of the conversion module are respectively an empty signal output end, a read enable end, a read data port (dout) and a reset input end of the FIFO.

The RAM (Random Access Memory) capable of registering a read-write pointer is used as an internal Memory of the FIFO, and may be a dual-port Random Access Memory, that is, the RAM module in this embodiment is a read-write dual-port RAM, and can provide a large amount of storage space for the FIFO to better cache data in the FIFO.

The RAM module includes a data input terminal (D), a read pointer input terminal (Rd _ addr), a write pointer input terminal (Wr _ addr), a data output terminal Q, and a data output terminal QP. The data input end (D) of the RAM module is a write data port (Wr _ data) of the whole FIFO.

When the reset input resetn =0 of the FIFO, i.e., the reset inputs resetn =0 of the first logic block and the conversion block, a reset operation is performed. The full signal output end full, the empty signal output end empty and the empty signal output end empty of the first logic module are all reset to 1, which indicates that the FIFO in the reset state is not allowed to be read and written; the read pointer output end Rd _ addr and the write pointer output end Wr _ addr of the first logic module are both reset to 0, that is, the read/write pointers both point to the initial address (0 address) of the RAM module.

When the reset input end resetn =1 of the FIFO, the reset is over, the circuit is in a working state, the read/write pointers of the first logic module are equal, Wr _ addr = Rd _ addr =0, the full signal output end full =0 and the empty signal output end empty =1 of the FIFO indicate that the state of the FIFO is empty at this time, and data is not allowed to be read out. When the write enable end wren =1 of the FIFO indicates that the write function of the FIFO is enabled, the write data port Wr _ data of the FIFO provides write data for the RAM module, the data is written into the 0 address of the RAM module, the write pointer output end Wr _ addr of the first logic module points to the next address to be written, that is, Wr _ addr =1, at this time, Wr _ addr leads Rd _ addr, the full signal output end full =0 of the FIFO, and the empty signal output end empty =0 of the first logic module, which indicates that the RAM module is in a non-empty and non-full state at this time, and allows a read/write operation.