阅读说明：本技术 HfO2基栅介质层材料及其制备方法和半导体器件 (HfO2Base gate dielectric layer material, preparation method thereof and semiconductor device ) 是由 裘三君 于 2020-07-16 设计创作，主要内容包括：本发明涉及一种HfO<Sub>2</Sub>基栅介质层材料,包括Y<Sub>2</Sub>O<Sub>3</Sub>,且在所述HfO<Sub>2</Sub>基栅介质层材料中,Y原子个数百分比为0.01-28％。本发明的HfO<Sub>2</Sub>基栅介质层材料,掺杂有Y原子个数百分比为0.01-28％的Y<Sub>2</Sub>O<Sub>3</Sub>,可以有效降低SiC的界面态密度,提高栅介质层质量,同时解决了SiC半导体器件栅极漏电流大,耐压不足的问题,提高了SiC器件的性能。(The invention relates to HfO 2 A base gate dielectric layer material including Y 2 O 3 And in the HfO 2 In the material of the basic grid dielectric layer, the atomic percentage of Y is 0.01-28%. HfO of the invention 2 A base gate dielectric layer material doped with Y atom percentage of 0.01-28% 2 O 3 The method can effectively reduce the interface state density of SiC, improve the quality of a gate dielectric layer and simultaneously solve the problem of a SiC semiconductor device gateThe leakage current is large, the voltage resistance is insufficient, and the performance of the SiC device is improved.)

1. HfO₂A base gate dielectric layer material including Y₂O₃And in the HfO₂In the material of the basic grid dielectric layer, the atomic percentage of Y is 0.01-28%.

2. HfO₂A base gate dielectric layer of HfO as defined in claim 1₂Preparing a base gate dielectric layer material, arranging the base gate dielectric layer material on the SiC substrate, and forming the HfO₂The density of the interface state between the base gate dielectric layer and the SiC is 1 multiplied by 10⁹-9.9×10¹⁰/cm²。

3. HfO according to claim 2₂A gate dielectric layer, wherein the SiC substrate has a doping concentration of 4.8 × 10¹⁵-5.2×10¹⁵cm^-3The doping concentration of the P-type SiC substrate is 0.8 multiplied by 10¹⁵-1.2×10¹⁵cm^-3An N-type SiC substrate of (1).

4. HfO prepared using the material of claim 2 or 3₂The thickness of the base gate dielectric layer is 10-100 nm.

5. A semiconductor device comprising the HfO of any one of claims 2-4₂And a base gate dielectric layer.

6. Use of the semiconductor device of claim 5 in a MOS capacitor structure and/or an NMOSFET capacitor structure.

7. A method for manufacturing a semiconductor device according to claim 5, comprising the steps of:

firstly, cleaning the SiC substrate, removing an oxide layer on the surface of the SiC substrate, and then drying the SiC substrate;

preparing the HfO on the pretreated SiC substrate by adopting a magnetron sputtering method₂A base gate dielectric layer;

in the HfO₂And preparing a metal electrode on the base gate dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising the steps of: and depositing photoresist on the metal electrode, then photoetching to obtain a gate pattern, and etching the metal electrode to obtain a gate electrode.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the thickness of the metal electrode is 50 to 300 nm.

10. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein the metal element in the metal electrode is at least one of Al, Pt, W, Ni, and Au.

Technical Field

The invention belongs to the technical field of semiconductor materials, and particularly relates to HfO₂A base gate dielectric layer material, a preparation method thereof and a semiconductor device.

Background

The silicon-based semiconductor material is a novel material developed on the basis of silicon materials, and comprises a germanium-silicon material, porous silicon, microcrystalline silicon and other materials which are heteroepitaxial with silicon as a substrate on a semiconductor insulating layerCompound semiconductor materials, and the like. Compared with the conventional SiO₂The third generation semiconductor material represented by SiC not only has the characteristics of high forbidden bandwidth, high thermal conductivity, high breakdown field strength, high saturated electron drift rate and the like, but also has good physical and chemical stability, strong enough irradiation resistance, high mechanical strength and the like, and has wide development potential. Therefore, SiC is increasingly used to develop high-temperature, high-power, high-frequency power semiconductor devices.

At present, an insulated gate dielectric layer of a SiC-based MOS power device is mainly formed by thermally oxidizing the SiC surface at high temperature to form SiO₂And annealing the dielectric layer. However, SiO formed by thermally oxidizing a SiC substrate₂More interface states exist between the layer and the SiC substrate, and the carrier mobility of the MOS device channel is lower by one order of magnitude than that of the SiC material due to the scattering of the interface states to carriers, so that the performance of the SiC-based semiconductor material is influenced. In addition, after the SiC surface is oxidized at high temperature, a large amount of carbon particles are remained, so that SiO is generated₂The quality of the dielectric layer is poor, the grid leakage current of the power device is large, the power consumption of the driving chip is increased, and the withstand voltage of the grid dielectric layer is not ideal.

Therefore, a new insulating dielectric layer material for SiC base is urgently needed to be researched to improve the quality of the gate dielectric layer, reduce the density of the SiC interface state, solve the problems of non-ideal gate dielectric layer and large gate leakage current, and further improve the performance of the SiC semiconductor device.

Disclosure of Invention

The invention provides a doped Y₂O₃HfO of₂The material of the base gate dielectric layer can reduce the interface state density of SiC, improve the quality of the gate dielectric layer, solve the problems of large gate leakage current and insufficient voltage resistance of the SiC semiconductor device and improve the performance of the SiC device.

The invention also provides a doped Y₂O₃HfO of₂The gate dielectric layer reduces the interface state density of SiC, has excellent quality, solves the problems of large gate leakage current and insufficient voltage resistance of the SiC semiconductor device, and improves the performance of the SiC device。

The invention also provides a semiconductor device comprising a doped Y₂O₃HfO of₂The semiconductor device has lower SiC interface state density, and the grid leakage current is small, the pressure resistance is strong, and the performance is good.

The invention also provides the application of the semiconductor device in an MOS capacitor structure and/or an NMOSFET capacitor structure.

The invention also provides a preparation method of the semiconductor device, which has simple process and is convenient for large-scale production.

The technical scheme provided by the invention is as follows:

in a first aspect, the present invention provides an HfO₂A base gate dielectric layer material including Y₂O₃And in the HfO₂In the material of the basic grid dielectric layer, the atomic percentage of Y is 0.01-28%.

In the present invention, in HfO₂Y is doped in the base gate dielectric layer material with the atomic number percentage of Y being about 0.01-28%₂O₃For example, 5-15%, 0.5-5%, 2-8%, 15-28%, 10-15%, can effectively reduce the interface state density of SiC, improve the quality of gate dielectric layer, solve the problems of large gate leakage current and insufficient withstand voltage of SiC semiconductor device, and improve the performance of SiC device.

In a second aspect, the present invention provides an HfO₂A base gate dielectric layer made of the above HfO₂Preparing a base gate dielectric layer material, arranging the base gate dielectric layer material on the SiC substrate, and forming the HfO₂The density of the interface state between the base gate dielectric layer and the SiC is 1 multiplied by 10⁹-9.9×10¹⁰/cm²，5×10¹⁰/cm²，1/cm²，9.9×10¹⁰/cm²，2×10¹⁰/cm²，4×10¹⁰/cm²，9×10¹⁰/cm²，8×10¹⁰/cm²，6×10¹⁰/cm²。

HfO of the invention₂A gate dielectric layer formed by doping with Y atomsY with a sub-number percentage of 0.01-28%₂O₃The interface state density of the SiC can be reduced, the quality of a gate dielectric layer is improved, the problems of large gate leakage current and insufficient voltage resistance of the SiC semiconductor device are solved, and the safety and the stability of the SiC device are improved.

The present invention is not particularly limited to the SiC substrate, and it is understood that the conventional arrangement based on the SiC substrate is within the scope of the present invention. For example, the SiC substrate can be doped to a doping concentration of about 4.8X 10¹⁵-5.2×10¹⁵cm^-3Is set with a doping concentration of about 0.8 x 10 under the P-type SiC substrate¹⁵-1.2×10¹⁵cm^-3An N-type SiC substrate of (1).

If HfO₂The performance of a semiconductor device is possibly influenced by the overlarge thickness of the base gate dielectric layer, HfO₂If the thickness of the base gate dielectric layer is too small, the effect may not be achieved. Therefore, the invention is applicable to HfO₂The thickness of the base gate dielectric layer is limited, and the inventor researches and discovers that when HfO is used₂When the thickness of the base gate dielectric layer is about 10-100nm, for example 40-60nm, the interface state density of SiC can be better reduced, the quality of the gate dielectric layer is improved, and the safety and the stability of a SiC device are better improved.

In a third aspect, the present invention provides a semiconductor device comprising the above HfO₂And a base gate dielectric layer.

HfO of semiconductor device of the present invention₂The basic gate dielectric layer is doped with Y atom percentage of 0.01-28%₂O₃The interface state density of SiC is effectively reduced, the problems of large grid leakage current and insufficient voltage resistance of the SiC semiconductor device are solved, and the safety and the stability of the SiC device are improved.

In a fourth aspect, the invention provides an application of the semiconductor device in a MOS capacitor structure and/or an NMOSFET capacitor structure.

In a fifth aspect, the present invention provides a method for manufacturing a semiconductor device, including the steps of:

firstly, cleaning the SiC substrate, removing an oxide layer on the surface of the SiC substrate, and then drying the SiC substrate;

preparing the HfO on the pretreated SiC substrate by adopting a magnetron sputtering method₂A base gate dielectric layer;

in the HfO₂And preparing a metal electrode on the base gate dielectric layer.

In the present invention, the method for cleaning the SiC substrate may be a method that is conventional in the art as long as the cleaning of the SiC substrate is achieved, and for example, the cleaning may be performed by using a conventional RCA technique. In the removal of the SiC surface oxide layer, an acid solution soaking method may be used, for example, HF with a concentration of about 1-5%, or other methods conventional in the art may be used, and the present invention is not particularly limited thereto. The drying mode can adopt natural drying, drying and the like.

In the invention, the thickness of the gate dielectric layer can be accurately controlled by adopting a sputtering method, so that HfO with high conformality and high quality can be obtained₂And a base gate dielectric layer. The preparation method of the metal electrode is not particularly limited, and the metal electrode can be prepared by adopting the conventional technical means of the invention, for example, the metal can be deposited by a lift-off or hardmark method, and the metal electrode can also be obtained by sputtering by a PVD (physical vapor deposition) process.

The preparation method of the semiconductor device has the advantages of simple process and convenience for large-scale production, and the semiconductor device prepared by the method has small grid leakage current, strong pressure resistance and good safety and stability.

As a specific embodiment of the method of the present invention, the method for manufacturing a semiconductor device further includes the steps of: and depositing photoresist on the metal electrode, then photoetching to obtain a gate pattern, and etching the metal electrode to obtain a gate electrode.

As a specific embodiment of the method of the present invention, the thickness of the metal electrode is 50-300nm, such as 80-100nm, 50-90nm, 100-200nm, 200-300nm, 150-250 nm.

Of course, the metal element may be selected according to preset requirements, and may be selected from one of Al, Pt, W, Ni or Au, such as Ni.

Doping Y of the invention₂O₃HfO of₂The material of the base gate dielectric layer can reduce the interface state density of SiC, improve the quality of the gate dielectric layer, solve the problems of large gate leakage current and insufficient voltage resistance of the SiC semiconductor device and improve the performance of the SiC device. In addition, doping Y of the invention₂O₃HfO of₂The base gate dielectric layer reduces the interface state density of SiC, has excellent quality, solves the problems of large grid leakage current and insufficient voltage resistance of the SiC semiconductor device, and improves the performance of the SiC device.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 to 7 are schematic views of respective structures in a process flow of manufacturing a SiC semiconductor device of an NMOSFET structure of example 1;

fig. 8 to 9 are schematic views of respective structures in a manufacturing process flow of the SiC semiconductor device of the MOS structure of embodiment 2.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The present invention is described in detail below: