阅读说明：本技术 一种同一pcie槽位兼容不同pcie带宽的pcie设备、装置及方法 (PCIE equipment, device and method for realizing compatibility of same PCIE slot position with different PCIE bandwidths ) 是由 张�杰 于 2020-05-29 设计创作，主要内容包括：本发明公开一种同一PCIE槽位兼容不同PCIE带宽的PCIE设备、装置及方法,包括PCIE单板,PCIE单板上设置对应第一PCIE XN设备的第一核心芯片和对应第二PCIE XN设备的第二核心芯片,PCIE单板本体上还设置XN+XN金手指,该XN+XN金手指由两个XN金手指组成；该PCIE单板形成一PCIE XN+XN设备；其中N为1、2、4、8中的任一种。PCIE XN+XN设备可与具有X2N槽位的PCIE扩展卡插接。本发明为配置多个PCIE XN设备节省槽位空间,解决了同一PCIE X2N槽位既能支持X2N带宽的设备,也能支持XN+XN带宽的设备,实现了同一槽位兼容不同PCIE设备的设计。(The invention discloses PCIE equipment, a device and a method for realizing compatibility of different PCIE bandwidths at the same PCIE slot position, wherein the device comprises a PCIE single board, a first core chip corresponding to first PCIE XN equipment and a second core chip corresponding to second PCIE XN equipment are arranged on the PCIE single board, and an XN + XN golden finger is also arranged on a PCIE single board body and consists of two XN golden fingers; the PCIE single board forms a PCIE XN + XN device; wherein N is any one of 1, 2, 4 and 8. A PCIE XN + XN device may be plugged into a PCIE expansion card with X2N slot. The invention saves slot space for configuring a plurality of PCIE XN devices, solves the problem that the same PCIE X2N slot can support both the device with X2N bandwidth and the device with XN + XN bandwidth, and realizes the design that the same slot is compatible with different PCIE devices.)

1. A PCIE device compatible with different PCIE bandwidths in the same PCIE slot position is characterized by comprising a PCIE single board, wherein the PCIE single board is provided with a first core chip corresponding to a first PCIE XN device and a second core chip corresponding to a second PCIE XN device, and a PCIE single board body is also provided with an XN + XN golden finger which consists of two XN golden fingers; the PCIE single board forms a PCIE XN + XN device; wherein N is any one of 1, 2, 4 and 8.

2. The PCIE device of claim 1, wherein bandwidth identification pins are configured on XN + XN gold fingers on the PCIE board.

3. The PCIE device of claim 2, wherein the bandwidth identification pin is a reserved pin of one of the XN gold fingers, and the reserved pin is grounded.

4. A device of the PCIE device of claim 3, where the same PCIE slot is compatible with different PCIE bandwidths, and the device includes a motherboard and a PCIE expansion card, where the PCIE expansion card is provided with an X2N slot; the PCIE expansion card is characterized in that the PCIE expansion card is inserted into the PCIE equipment through an X2N slot position; the PCIE device is a PCIE X2N device or a PCIE XN + XN device;

a pin on an X2N slot of the PCIE expansion card is pulled up to a power supply, and the identification pin corresponds to a bandwidth identification pin of the PCIE XN + XN equipment; the signal of the identification pin in the X2N slot of the PCIE expansion card is named as a Present signal;

the PCIE expansion card transmits the Present signal and the bandwidth configuration information to the motherboard, and the motherboard configures the corresponding bandwidth for the X2N slot according to the Present signal and the bandwidth configuration information.

5. The device of claim 4, wherein a PCH chip and a Slimline connector are disposed on a motherboard, and the PCIE expansion card is connected to the PCH chip via the Slimline connector; the PCH chip is connected with the Slimline connector through at least one 2-to-1 analog switch;

configuring a BIOS program on the mainboard; the bandwidth configuration information comprises default configuration information and standby configuration information;

the PCIE expansion card transmits the Present signal to a control end of the 1-from-2 analog switch through a Slimline connector, and transmits bandwidth configuration information to an input end of the 1-from-2 analog switch through the Slimline connector; the 1-from-2 analog switch gates a channel according to the Present signal and transmits default configuration information or standby configuration information to the PCH chip.

6. The device of claim 5, wherein M GPIO pins are provided on a PCH chip, and each GPIO pin is connected to a slim connector via a 1-from-2 analog switch;

the bandwidth configuration information is address coding which is marked by 0 and 1 and comprises M bits; the address code of the standby configuration information is the negation of the corresponding bit of the address code of the default configuration information; wherein M is an integer greater than 1.

7. The device of claim 6, wherein a PCIE expansion card is a Riser card.

8. A method for the same PCIE slot to be compatible with different PCIE bandwidths based on the apparatus in claim 7, comprising the steps of:

inserting a certain PCIE device into a PCIE expansion card with an X2N slot;

the PCIE expansion card transmits the Present signal and the bandwidth configuration information to the mainboard;

when the Present signal is at a high level, the bandwidth configuration information received by the motherboard is default configuration information, which indicates that the inserted PCIE device is a PCIE X2N device, and the motherboard configures an X2N bandwidth for an X2N slot of a PCIE expansion card;

when the Present signal is at a low level, the bandwidth configuration information received by the motherboard is the standby configuration information, which indicates that the inserted PCIE device is a PCIE XN + XN device, and the motherboard configures an XN + XN bandwidth for an X2N slot of the PCIE expansion card.

Technical Field

The invention relates to the field of PCIE equipment, in particular to PCIE equipment, a device and a method for realizing compatibility of different PCIE bandwidths at the same PCIE slot position.

Background

In the server system, a plurality of devices can be hung under the PCIE bus of the mainboard, including external plug-in cards such as hard disks, network cards, SAS/RAID cards and the like. PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, and connected PCIE equipment distributes independent channel bandwidth without sharing bus bandwidth. In the actual board design, the bandwidth required by the equipment needs to be determined, and the equipment can be normally used only by correctly setting under the BIOS. The BIOS is a set of programs solidified on ROM in the server mainboard, and the programs store the basic input and output program, the self-test program after power-on and the system self-starting program of the computer.

Based on the characteristics of PCIE, the bandwidth supports downward compatibility, and for ports set to X16 bandwidth, devices of X8, X4, X2, and X1 are supported downward. In the configuration of a server, a need for multiple PCIE X8 devices may sometimes occur, which may cause a PCIE X8 slot to be insufficient, and then the X8 device may be plugged into an X16 slot for use. This may cause waste of the PCIE X16 slot on the Riser card, for example, two PCIE X8 devices are inserted into two slots of PCIE X16, and it is not possible to support two devices of X8 in one X16 slot.

Disclosure of Invention

In order to solve the above problems, the present invention provides a PCIE device, an apparatus, and a method that are compatible with different PCIE bandwidths in the same PCIE slot, and can implement that one X2N slot supports two XN devices.

The technical scheme of the invention is as follows: a PCIE device compatible with different PCIE bandwidths in the same PCIE slot position comprises a PCIE single board, wherein a first core chip corresponding to a first PCIE XN device and a second core chip corresponding to a second PCIE XN device are arranged on the PCIE single board, and an XN + XN golden finger is further arranged on a PCIE single board body and consists of two XN golden fingers; the PCIE single board forms a PCIE XN + XN device; wherein N is any one of 1, 2, 4 and 8.

Further, a bandwidth identification pin is configured on an XN + XN gold finger on the PCIE board.

Further, the bandwidth identification pin is a reserved pin of one XN gold finger, and the reserved pin is grounded.

The technical scheme of the invention also comprises a device for realizing compatibility of different PCIE bandwidths in the same PCIE slot position of the PCIE equipment, which comprises a mainboard and a PCIE expansion card, wherein the PCIE expansion card is provided with an X2N slot position; the PCIE expansion card is connected with the PCIE equipment through an X2N slot position; the PCIE device is a PCIE X2N device or a PCIE XN + XN device;

a pin on an X2N slot of the PCIE expansion card is pulled up to a power supply, and the identification pin corresponds to a bandwidth identification pin of the PCIE XN + XN equipment; the signal of the identification pin in the X2N slot of the PCIE expansion card is named as a Present signal;

the PCIE expansion card transmits the Present signal and the bandwidth configuration information to the motherboard, and the motherboard configures the corresponding bandwidth for the X2N slot according to the Present signal and the bandwidth configuration information.

Furthermore, a PCH chip and a Slimline connector are arranged on the main board, and the PCIE expansion card is connected with the PCH chip through the Slimline connector; the PCH chip is connected with the Slimline connector through at least one 2-to-1 analog switch;

configuring a BIOS program on the mainboard; the bandwidth configuration information comprises default configuration information and standby configuration information;

the PCIE expansion card transmits the Present signal to a control end of the 1-from-2 analog switch through a Slimline connector, and transmits bandwidth configuration information to an input end of the 1-from-2 analog switch through the Slimline connector; the 1-from-2 analog switch gates a channel according to the Present signal and transmits default configuration information or standby configuration information to the PCH chip.

Furthermore, M GPIO pins are arranged on the PCH chip, and each GPIO pin is connected with the Slimline connector through a 2-to-1 analog switch;

the bandwidth configuration information is address coding which is marked by 0 and 1 and comprises M bits; the address code of the standby configuration information is the negation of the corresponding bit of the address code of the default configuration information; wherein M is an integer greater than 1.

Further, the PCIE expansion card is a Riser card.

The technical scheme of the invention also comprises a method for realizing compatibility of different PCIE bandwidths at the same PCIE slot position of the device, which comprises the following steps:

inserting a certain PCIE device into a PCIE expansion card with an X2N slot;

the PCIE expansion card transmits the Present signal and the bandwidth configuration information to the mainboard;

when the Present signal is at a high level, the bandwidth configuration information received by the motherboard is default configuration information, which indicates that the inserted PCIE device is a PCIE X2N device, and the motherboard configures an X2N bandwidth for an X2N slot of a PCIE expansion card;

when the Present signal is at a low level, the bandwidth configuration information received by the motherboard is the standby configuration information, which indicates that the inserted PCIE device is a PCIE XN + XN device, and the motherboard configures an XN + XN bandwidth for an X2N slot of the PCIE expansion card.

The invention provides PCIE equipment, a device and a method for realizing compatibility of different PCIE bandwidths at the same PCIE slot position, which are characterized in that PCIE XN + XN equipment is arranged, can be inserted into an X2N slot, and is simultaneously configured with corresponding pin identifiers, so that a mainboard is enabled to configure corresponding bandwidths according to the identifiers. The invention saves slot space for configuring a plurality of PCIE XN devices, solves the problem that the same PCIE X2N slot can support both the device with X2N bandwidth and the device with XN + XN bandwidth, and realizes the design that the same slot is compatible with different PCIE devices.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a second embodiment of the present invention.

FIG. 3 is a schematic flow chart of a third method according to an embodiment of the present invention.

In the figure, 1-a first PCIE XN device, 2-a second PCIE XN device, 3-a first core chip, 4-a second core chip, 5-PCIE XN + XN device, 6-XN + XN gold finger, 7-PCIE expansion card, 8-X2N gold finger, 9-PCIE X2N device, 10-motherboard, 11-Slimline connector, 12-PCH chip, and 13-2 selects 1 analog switch.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings by way of specific examples, which are illustrative of the present invention and are not limited to the following embodiments.