阅读说明：本技术 阵列基板及其制造方法 (Array substrate and manufacturing method thereof ) 是由 梁超 刘旭阳 于 2020-06-22 设计创作，主要内容包括：一种阵列基板,包括层叠设置的柔性基板、阻挡层及缓冲层。所述阵列基板还包括:半导体层,位于所述缓冲层上,包括两个源/漏极及位于所述两个源/漏极间的通道区；第一栅绝缘层,位于所述半导体层与所述缓冲层上；第一栅极,位于所述第一栅绝缘层上；层间介电层,位于所述第一栅极及所述第一栅绝缘层上,包括对应所述第一栅极而设置的凹槽；两个接触孔,形成于所述层间介电层及所述第一栅绝缘层内,分别露出所述两个源/漏极之一；以及多个金属层,设置于所述层间介电层上,对应于所述两个接触孔及所述凹槽,其中对应于所述两个接触孔设置的所述金属层具有第一顶面,而对应于所述凹槽设置的所述金属层具有低于所述第一顶面的第二顶面。(An array substrate comprises a flexible substrate, a barrier layer and a buffer layer which are arranged in a stacked mode. The array substrate also comprises a semiconductor layer, a buffer layer and a plurality of metal layers, wherein the semiconductor layer is positioned on the buffer layer and comprises two source/drain electrodes and a channel region positioned between the two source/drain electrodes; the first gate insulating layer is positioned on the semiconductor layer and the buffer layer; a first gate electrode on the first gate insulating layer; an interlayer dielectric layer on the first gate and the first gate insulating layer, including a groove corresponding to the first gate; two contact holes formed in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes; and a plurality of metal layers disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layers disposed corresponding to the two contact holes have a first top surface, and the metal layers disposed corresponding to the groove have a second top surface lower than the first top surface.)

1. The array substrate comprises a flexible substrate, a barrier layer and a buffer layer which are arranged in a stacked mode, and is characterized in that the barrier layer is arranged on the flexible substrate;

the semiconductor layer is positioned on the buffer layer and comprises two source/drain electrodes and a channel region positioned between the two source/drain electrodes;

the first gate insulating layer is positioned on the semiconductor layer and the buffer layer;

the first grid electrode is positioned on the first grid insulating layer, and the vertical projection of the first grid electrode on the flexible substrate completely falls into the vertical projection of the channel region of the semiconductor layer on the flexible substrate;

an interlayer dielectric layer on the first gate and the first gate insulating layer, including a groove corresponding to the first gate;

two contact holes formed in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes; and

and a plurality of metal layers disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layers disposed corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers disposed corresponding to the groove have second top surfaces lower than the first top surfaces.

2. The array substrate of claim 1, wherein the plurality of metal layers are formed simultaneously from the same metal material.

3. The array substrate of claim 1, wherein the top surface of the interlayer dielectric layer exposed by the groove is lower than the top surface of the interlayer dielectric layer outside the groove.

4. The array substrate of claim 1, wherein the metal layer disposed corresponding to the recess is disposed corresponding to the first gate and forms a parasitic capacitance with the first gate insulating layer and the first gate.

5. The array substrate of claim 1, wherein the first gate electrode, the first gate insulating layer, the semiconductor layer and the two source/drain electrodes constitute a thin film transistor.

6. The array substrate of claim 1, wherein the array base layer further comprises:

an organic dielectric layer formed on the plurality of metal layers and the interlayer dielectric layer;

an anode formed on the organic dielectric layer and electrically connected to one of the metal layers; and

and the pixel limiting layer is formed on the anode and the organic dielectric layer and exposes a part of the anode.

7. The manufacturing method of the array substrate comprises a flexible substrate, a barrier layer and a buffer layer which are arranged in a stacked mode, and is characterized by comprising the following steps:

forming a semiconductor layer on the buffer layer;

forming a first gate insulating layer on the semiconductor layer and the buffer layer;

forming a first gate electrode on a portion of the first gate insulating layer;

forming two source/drain electrodes in the semiconductor layer and a channel region between the two source/drain electrodes, wherein a vertical projection of the first gate electrode on the flexible substrate completely falls within a vertical projection of the channel region of the semiconductor layer on the flexible substrate;

forming an interlayer dielectric layer on the first gate electrode and the first gate insulating layer,

forming two contact holes in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes respectively;

forming a groove in the interlayer dielectric layer, wherein the groove is arranged corresponding to the first grid electrode; and

forming a plurality of metal layers on the interlayer dielectric layer, wherein the plurality of metal layers are respectively arranged corresponding to the two contact holes and the groove, the metal layers arranged corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers arranged corresponding to the groove have second top surfaces lower than the first top surfaces.

8. The method of claim 7, wherein the plurality of metal layers are formed simultaneously from the same metal material by patterning through a same photomask and etching process (none shown).

9. The method as claimed in claim 7, wherein the metal layer disposed corresponding to the recess is disposed corresponding to the first gate, and forms a parasitic capacitance with the first gate insulating layer and the first gate.

10. The method of claim 7, wherein the first gate electrode, the first gate insulating layer, the semiconductor layer and the two source/drain electrodes form a thin film transistor.

Technical Field

The present disclosure relates to the field of display devices, and particularly, to an array substrate and a method for manufacturing the same.

Background

In the field of Display technology, flat panel Display technologies such as Liquid Crystal Displays (LCDs) and Organic Light Emitting Diodes (OLEDs) have become the main fields of research and development. Among them, the OLED has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of approximately 180 degrees, a wide range of use temperature, and capability of realizing flexible display and large-area full-color display, and is considered as a display device with the most potential development in the industry.

OLEDs are classified into passive OLEDs (pmoleds) and active OLEDs (amoleds) according to driving types. The AMOLED is a self-luminous component generally composed of a Low Temperature Poly-Silicon (LTPS) driving backplane and an electroluminescent layer. For the AMOLED, the low-temperature polysilicon has higher electron mobility, so that the low-temperature polysilicon material has the advantages of high resolution, high reaction speed, high brightness, high aperture opening ratio, low energy consumption and the like.

AMOLEDs typically employ an array substrate comprising Thin Film Transistors (TFTs), and the fabrication of TFTs involves the use of multiple photomasks (photo masks). If the number of photomasks used is larger, the whole process flow of the TFT is longer, the difficulty is higher, and the cost is higher. Therefore, how to reduce the number of photomasks for manufacturing the TFT while ensuring the performance of the array is not changed is one of the important directions for reducing the cost in the subsequent AMOLED manufacturing.

Disclosure of Invention

The invention aims to simplify the process flow of the existing array substrate, reduce the manufacturing difficulty and save the cost.

In order to achieve the above object, the present invention provides an array substrate, which includes a flexible substrate, a barrier layer, and a buffer layer stacked on the flexible substrate. The array substrate includes:

the semiconductor layer is positioned on the buffer layer and comprises two source/drain electrodes and a channel region positioned between the two source/drain electrodes;

the first gate insulating layer is positioned on the semiconductor layer and the buffer layer;

the first grid electrode is positioned on the first grid insulating layer, and the vertical projection of the first grid electrode on the flexible substrate completely falls into the vertical projection of the channel region of the semiconductor layer on the flexible substrate;

an interlayer dielectric layer on the first gate and the first gate insulating layer, including a groove corresponding to the first gate;

two contact holes formed in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes; and

and a plurality of metal layers disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layers disposed corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers disposed corresponding to the groove have second top surfaces lower than the first top surfaces.

In some embodiments, the plurality of metal layers are formed simultaneously from the same metal material.

In some embodiments, a top surface of the interlayer dielectric layer exposed by the recess is lower than a top surface of the interlayer dielectric layer outside the recess.

In some embodiments, the metal layer disposed corresponding to the groove is disposed corresponding to the first gate electrode, and forms a parasitic capacitance with the first gate insulating layer and the first gate electrode.

In some embodiments, the first gate electrode, the first gate insulating layer, the semiconductor layer, and the two source/drain electrodes constitute a thin film transistor.

In some embodiments, the array substrate further comprises:

an organic dielectric layer formed on the plurality of metal layers and the interlayer dielectric layer;

an anode formed on the organic dielectric layer and electrically connected to one of the metal layers; and

and the pixel limiting layer is formed on the anode and the organic dielectric layer and exposes a part of the anode.

The embodiment of the present application further provides a manufacturing method of an array substrate, where the array substrate includes a flexible substrate, a barrier layer, and a buffer layer, which are stacked, and the manufacturing method is characterized by including the following steps:

forming a semiconductor layer on the buffer layer;

forming a first gate insulating layer on the semiconductor layer and the buffer layer;

forming a first gate electrode on a portion of the first gate insulating layer;

forming two source/drain electrodes in the semiconductor layer and a channel region between the two source/drain electrodes, wherein a vertical projection of the first gate electrode on the flexible substrate completely falls within a vertical projection of the channel region of the semiconductor layer on the flexible substrate;

forming an interlayer dielectric layer on the first gate electrode and the first gate insulating layer,

forming two contact holes in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes respectively;

forming a groove in the interlayer dielectric layer, wherein the groove is arranged corresponding to the first grid electrode; and

forming a plurality of metal layers on the interlayer dielectric layer, wherein the plurality of metal layers are respectively arranged corresponding to the two contact holes and the groove, the metal layers arranged corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers arranged corresponding to the groove have second top surfaces lower than the first top surfaces.

In some embodiments, the multiple metal layers are formed simultaneously from the same metal material through patterning of the same photomask and etching process (both not shown).

In some embodiments, the metal layer disposed corresponding to the groove is disposed corresponding to the first gate electrode, and forms a parasitic capacitance with the first gate insulating layer and the first gate electrode.

In some embodiments, the first gate electrode, the first gate insulating layer, the semiconductor layer, and the two source/drain electrodes constitute a thin film transistor.

In the array substrate and the manufacturing method thereof provided by the embodiment of the application, five photo masks and etching processes are used to complete the parasitic capacitance (Cst) in the Thin Film Transistor (TFT) and the AMOLED driving circuit, so as to reduce the Crosstalk (Crosstalk) between adjacent pixels. In the array substrate according to the embodiment of the present invention, the metal layer serving as the upper electrode plate of the parasitic capacitor and the metal layer electrically connected to the source/drain are simultaneously deposited and patterned by the same photo mask and etching process (both not shown), which can save at least one deposition of the insulating layer and the implementation of the related process flows such as an additional photo mask and etching process (both not shown) for individually patterning the upper electrode plate of the parasitic capacitor, compared to the conventional manufacturing method. Therefore, the array substrate and the manufacturing method thereof provided by the embodiment of the application have the technical effects of simplifying the process flow, reducing the manufacturing difficulty, saving the cost and the like.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 to 8 are schematic cross-sectional views of steps of a method for manufacturing an array substrate according to the present invention.

FIG. 9 is a schematic structural diagram of a display panel according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The following description of the embodiments refers to the accompanying drawings for illustrating the specific embodiments in which the invention may be practiced. The directional terms used in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., refer to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention.

The present embodiment provides a method for manufacturing an array substrate, which is illustrated by the cross-sectional views of fig. 1 to 8.

First, referring to fig. 1, a flexible substrate 100 is provided, and a material of the flexible substrate 100 may be Polyimide (PI). Specifically, the flexible substrate 100 defines a display area a and an adjacent non-display area B. The display area a is, for example, an area where the AMOLED array assembly is formed, and the non-display area B is, for example, an area where the bending assembly is formed. Next, a barrier layer 102 and a buffer layer 104 are sequentially deposited on the flexible substrate 110. Next, a semiconductor layer 106 is formed on the buffer layer 104 within the display region a. The semiconductor layer 106 may be a polysilicon layer processed by excimer laser crystallization, and patterned by a first photomask and etching process (both not shown).

Next, referring to fig. 2, a first gate insulating layer 108 is deposited on the semiconductor layer 106 and the buffer layer 104, a first gate layer is deposited on the first gate insulating layer 108, and the first gate layer is patterned through a second photo mask and etching process (both not shown) to form a first gate electrode 110. Then, the first gate 110 is used as a hard mask (hard mask), a self-aligned ion implantation process is performed to form two source/drain electrodes 106A in the semiconductor layer 106 not covered by the first gate 110, and the semiconductor layer between the two source/drain electrodes 106A is used as a channel region. Therefore, the vertical projection of the first gate electrode 110 on the flexible substrate 100 completely falls within the vertical projection of the channel region of the semiconductor layer 106 on the flexible substrate 100.

Next, referring to fig. 3, an interlayer dielectric layer 112 is deposited on the first gate insulating layer 108 and the first gate electrode 110, and is patterned by a third photo mask and etching process (both not shown) to form two contact holes (contacts) 114 and a first opening 116. The two contact holes 114 are formed in the display area a, penetrate through the interlayer dielectric layer 112 and the first gate insulating layer 108, and respectively expose one of the two source/drain electrodes 106A. The first opening 116 is formed in the non-display region B, penetrates through the interlayer dielectric layer 112 and the first gate insulating layer 108, and exposes a portion of the buffer layer 104.

Next, referring to fig. 4, a portion of the interlayer dielectric layer 112 in the display region a located on the first gate 110 and a portion of the buffer layer 104 and the barrier layer 102 in the non-display region B exposed by the first deep hole 116 are patterned by a fourth photo mask and etching process (neither of which is shown), a recess 118 is formed in the interlayer dielectric layer 112 in the display region a, and a second opening 120 is formed in the barrier layer 102 and the buffer layer 104 in the non-display region B. As shown in fig. 4, the top surface of the ild layer 112 exposed by the recess 118 is lower than the top surfaces of the other ild layers 112 in the display area a. In the display area a, the groove 118 is disposed corresponding to the first gate electrode 110. In the non-display region B, a vertical projection of the second opening 120 on the flexible substrate 100 completely falls into a vertical projection of the first opening 116 on the flexible substrate 100, and the first opening 116 and the second opening 120 form a step structure.

Next, referring to fig. 5, a metal material is deposited on the ild 112, the buffer layer 104 and the barrier layer 102, fills the plurality of contact holes 114, the first opening 116 and the second opening 120, and is patterned by a fifth photomask and etching process (none shown) to form three metal layers 122 and 124. The metal layer 122 in the display area a further includes a metal contact portion filling the contact hole 114 and electrically connecting the source/drain 106A through the metal contact portion. The metal layer 122 is also formed on a portion of the barrier layer 102 exposed by the second opening 120 in the non-display region B, and the metal layer 124 is formed in the recess 118 of the interlayer dielectric layer 112 on the first gate 110 in the display region a. In addition, the metal layer 122 disposed corresponding to the two contact holes 114 fills the contact holes 114 and has a first top surface, and the metal layer 124 disposed corresponding to the recess 118 has a second top surface lower than the first top surface.

Here, as shown in fig. 5, the first gate electrode 110, the first gate insulating layer 108, the semiconductor layer 106, and the two source/drain electrodes 106A in the display region a constitute a thin film transistor. The metal layer 124 disposed corresponding to the groove 118 is disposed corresponding to the first gate electrode 110, and forms a parasitic capacitance with the first gate insulating layer 108 and the first gate electrode 110.

Next, referring to fig. 6, an organic photoresist is filled in the first opening 116 and the second opening 120 in the non-display region B, and the organic photoresist is continuously coated on the metal layer 122, the metal layer 124 and the interlayer dielectric layer 112 to form an organic dielectric layer 126. Next, the organic material layer 126 corresponding to one of the metal layers 122 in the display area a is patterned by a sixth photomask and etching process (both not shown), so as to form a contact hole 128 exposing a portion of the metal layer 122.

Next, referring to fig. 7, metal is deposited on the organic dielectric layer 126 and fills the contact hole 128, and a patterned metal layer 130 is formed by a seventh photo mask and etching process (neither shown). The metal layer 130 is formed in the display area a and fills the contact hole 128 to electrically connect the metal layer 122 therebelow. The metal layer 130 is an anode of the light emitting unit.

Next, referring to fig. 8, a pixel defining layer 132 and a supporting layer 136 are formed on the organic material layer 126 and the metal layer 130, and the pixel defining layer 132 and the supporting layer 136 are patterned by an eighth photo mask and etching process (neither shown), so as to form a third opening 134 in the pixel defining layer 132 and the supporting layer 136. The third opening 134 penetrates the support layer and the pixel defining layer 132 and corresponds to the metal layer 130. A light emitting layer and a cathode layer (both not shown) may be further formed in the third opening 134 to complete the fabrication of a light emitting device such as an Organic Light Emitting Diode (OLED).

As shown in fig. 8, an embodiment of the invention provides an array substrate 10, which includes a flexible substrate 10, a barrier layer 102 and a buffer layer 104 stacked on the flexible substrate, and a display area a and a non-display area B adjacent to the display area a are defined on the flexible substrate, and the display area a includes:

a semiconductor layer 106 disposed on the buffer layer 104 and including two source/drain electrodes 106A and a channel region disposed therebetween;

a first gate insulating layer 108 on the semiconductor layer 106 and the buffer layer 104;

a first gate electrode 110 on the first gate insulating layer 108, wherein a vertical projection of the first gate electrode 110 on the flexible substrate 100 completely falls within a vertical projection of the channel region of the semiconductor layer 106 on the flexible substrate 100;

an interlayer dielectric layer 112 on the first gate electrode 110 and the first gate insulating layer 108, including a groove 118 (see fig. 5) corresponding to the first gate electrode 110;

two contact holes 114 (see fig. 5) formed in the interlayer dielectric layer 112 and the first gate insulating layer 108 to expose one of the two source/drain electrodes 106A, respectively; and

a plurality of metal layers 122 and 124 disposed on the interlayer dielectric layer 112 corresponding to the two contact holes 114 and the recess 118, wherein the metal layer 122 disposed corresponding to the two contact holes 114 fills the contact holes 114 and has a first top surface, and the metal layer 124 disposed corresponding to the recess 118 has a second top surface lower than the first top surface.

In addition, in the display area a, the array substrate 10 further includes:

an organic dielectric layer 126 formed on the plurality of metal layers 122 and 124 and the interlayer dielectric layer 112;

an anode (metal layer 130) formed on the organic dielectric layer 126 and electrically connected to one of the metal layers 122; and

a pixel defining layer 132 formed on the anode 130 and the organic dielectric layer 126 to expose a portion of the anode (metal layer 130).

In addition, the array substrate 10 of the present invention includes a non-display element formed by the metal layer 22, the organic dielectric layer 126 and the pixel defining layer 132 in the non-display region B, for example, for a bending element.

In the array substrate and the manufacturing method thereof provided by the embodiment of the present application, five photo masks and etching processes (all not shown) shown in fig. 1 to 5 are used to complete the parasitic capacitance (Cst) in the Thin Film Transistor (TFT) and the AMOLED driving circuit, thereby reducing the cross talk (Crosstalk) between adjacent pixels. The metal layer 124 serving as the upper electrode plate of the parasitic capacitor in the array substrate 10 according to the embodiment of the present invention may be deposited simultaneously with the metal layer 122 electrically connected to the source/drain 106A and patterned by a same photo mask and etching process (all not shown), which may save at least one deposition of an insulating layer and an additional photo mask and etching process (all not shown) for individually patterning the upper electrode plate of the parasitic capacitor, compared to the conventional manufacturing method. Therefore, the array substrate and the manufacturing method thereof provided by the embodiment of the application have the technical effects of simplifying the process flow, reducing the manufacturing difficulty, saving the cost and the like.

Referring to fig. 9, the present invention further provides a display device 1, which includes an array substrate 10, an IC 20, and a printed circuit board 30. Wherein. The array substrate 10 has a non-display area B and a display area a. The main design point of the display device 1 in this embodiment is the array substrate 10, and therefore other components (such as a base, a frame, or other optical quality improving films) of the display device 1 are not described in detail herein. The display device 1 can be used for any display device or component with a display function, such as wearable equipment, a mobile phone, a tablet computer, a television, a display, a notebook computer, an electronic book, an electronic newspaper, a digital photo frame, a navigator and the like. The wearable device comprises a smart bracelet, a smart watch, a VR (Virtual Reality) and other devices.

The display panel and the method for manufacturing the same provided by the present invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely illustrative for facilitating understanding of the method of the present invention and its core ideas, and not restrictive. Descriptions of features or aspects in each exemplary embodiment should generally be considered as applicable to similar features or aspects in other exemplary embodiments. While the present invention has been described with reference to exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention cover the modifications and variations of this invention provided they come within the spirit and scope of the appended claims and their equivalents and improvements made thereto.