阅读说明：本技术 一种mosfet器件结构及制造方法 (MOSFET device structure and manufacturing method ) 是由 习毓 丁文华 陈骞 单长玲 刘�英 郝艺锦 李朴 于 2021-07-05 设计创作，主要内容包括：一种MOSFET器件结构及其制造方法,包括N+衬底1、N-外延层2、P-body扩散窗口3、N+JFET扩散窗口4、栅介质层5、栅极多晶硅6、源N+扩散窗口7、源P+扩散窗口8和栅源隔离层9；本发明涉及一种优化的MOSFET设计和制造方法,在版图、工艺条件和产品静态参数基本不变的情况下,采用MOSFET新结构可以使开关参数降低17％～23.8％；在版图不变的情况下,采用外延穿通的设计方法,可以使高压MOSFET的导通电阻降低12.5％～27.6％；在版图和其他工艺条件基本不变的情况下,采用图1新结构中“4.N+JFET扩散窗口”进行局部JFET注入,可以使低压MOSFET的导通电阻降低11.3％～25.4％。(A MOSFET device structure and a manufacturing method thereof comprise an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3, an N + JFET diffusion window 4, a gate dielectric layer 5, a grid polysilicon 6, a source N + diffusion window 7, a source P + diffusion window 8 and a grid source isolation layer 9; the invention relates to an optimized MOSFET design and manufacturing method, which can reduce the switching parameter by 17-23.8% by adopting a new MOSFET structure under the condition that the layout, the process condition and the static parameter of a product are basically unchanged; under the condition that the layout is not changed, the on-resistance of the high-voltage MOSFET can be reduced by 12.5% -27.6% by adopting an epitaxial punch-through design method; under the condition that the layout and other process conditions are basically unchanged, the 4.N + JFET diffusion window in the novel structure of the figure 1 is adopted for local JFET injection, so that the on-resistance of the low-voltage MOSFET can be reduced by 11.3% -25.4%.)

1. A MOSFET device structure is characterized by comprising an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3, an N + JFET diffusion window 4, a gate dielectric layer 5, gate polysilicon 6, a source N + diffusion window 7, a source P + diffusion window 8 and a gate source isolation layer 9; an N-epitaxial layer 2 is arranged on an N + substrate 1, unit cell main junction P-body diffusion windows 3 of devices are arranged on the left side and the right side of the N-epitaxial layer 2, a gate dielectric layer 5 is arranged in the longitudinal direction of the N + JFET diffusion windows 4, the P-body diffusion windows 3 and the N + JFET diffusion windows 4 between the two P-body diffusion windows 3, a gate polysilicon 6 and a gate source isolation layer 9 are sequentially arranged on the gate dielectric layer 5, a metal layer 10 is arranged on the gate source isolation layer 9, the gate dielectric layer 5 is provided with an active N + diffusion window 7, a source P + diffusion window 8 and a source N + diffusion window 7, the source P + diffusion window 8 and the source metal 10 are connected to form a source, the gate metal 11 is connected to the gate polysilicon 6 through an opening to form a gate, the drain metal is connected to the N + substrate 1 to form a drain, and the source metal 10 is connected to the junction terminal 12.

2. A MOSFET device structure according to claim 1, characterized in that the device structure is a stripe structure or a cell structure; the gate polysilicon 6 is etched into two sections over the cell.

3. A MOSFET device structure according to claim 1, characterized in that the N + substrate 1 material is Si, AS-doped or Sb-doped, with a resistivity of 0.002 Ω.cm to 0.004 Ω.cm; the N-epitaxial layer 2 material is Si material grown by an epitaxial method, doped with P and having resistivity of 0.4-70 omega cm.

4. The MOSFET device structure of claim 1, wherein the source metal 10 is AL/ALSiCU and the gate metal is AL/ALSiCU.

5. A method for manufacturing a MOSFET device structure, comprising the steps of:

the complete manufacturing process flow comprises the following steps: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxygen → field oxygen lithography + etching → photoresist removal → growth of sacrificial oxide layer → N + JFET lithography → injection of N + JFET → annealing of photoresist removal → growth of sacrificial oxide layer → growth of gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → P-body implantation → P-body diffusion → removal of excess residual oxygen → NSD lithography → NSD injection → photoresist removal → activation → deposition of isolation layer → reflow → lead hole lithography + etching → photoresist removal → PSD injection → reflow → aluminum sputtering of metal → aluminum etching + etching → photoresist removal → deposition of passivation layer → lithography + etching → back side of photoresist removal → back side thinning of alloy → back side metallization → CP testing and warehousing.

6. The method of claim 5, wherein the step of forming the MOSFET device structure,

determining the epitaxial layer resistivity and the epitaxial layer thickness: calculating the epitaxial concentration and thickness meeting a certain breakdown voltage by using a formula (1), wherein the breakdown voltage gives 10-20% of design margin;

the formula (1) shows that: selecting the optimal WB and NB, and determining the lower limit value of the epitaxial resistivity and the upper limit value of the epitaxial thickness:

lower limit of epitaxial resistivity

The upper limit value of the epitaxial concentration is calculated by the following formula (2),

the BVDSS has a design margin of 10% to 20%, and the lower limit of the corresponding resistivity can be calculated by the following formula (3):

wherein q is a unit charge q of 1.6 × 10^-19C，μ_nIs the electron mobility;

upper limit of drift region thickness

After the upper limit value of the epitaxial concentration is determined, the upper limit value of the epitaxial thickness can be calculated by the following equation (4):

the thickness Xmn of the depletion layer expanded in the high-resistance epitaxial region is calculated by the formula (5):

the thickness Xmp of the depletion layer widening in the P-well region is calculated by the equation (6):

7. the method for manufacturing a MOSFET device structure as claimed in claim 5, wherein the N + JFET diffusion window 4 is manufactured by the following steps: after the growth of the sacrificial oxide layer and before the injection of the N + JFET, adding a local N + JFET photoetching process, wherein the specific process manufacturing flow is as follows: and (4) growing a sacrificial oxide layer → N + JFET photoetching → N + JFET injection.

8. The method of claim 7, wherein the JFET common process flow comprises: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxygen → field oxygen lithography + etching → photoresist removal → growth of sacrificial oxide layer → injection of N + JFET → photoresist removal → annealing of N + JFET → growth of sacrificial oxide layer → gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → injection of P-body → diffusion of P-body → removal of excess oxygen residue → NSD lithography → NSD injection → photoresist removal → activation → isolation layer deposition → reflow → lead hole lithography + etching → photoresist removal → PSD injection → reflow → front side metal aluminum sputtering → aluminum lithography + etching → photoresist removal → passivation layer deposition → PAD lithography + etching → alloy removal → back side metallization → CP testing → warehousing.

Technical Field

The invention belongs to the technical field of semiconductor discrete devices, and particularly relates to a MOSFET device structure and a manufacturing method thereof.

Background

MOSFETs are widely used in the power supply field due to their high switching speed and low on-resistance. In recent years, with the demand for high frequency and high efficiency power supplies, there has been an increasing demand for power MOSFETs having faster speed and lower power consumption and on-resistance. In order to improve the operating efficiency of the circuit, circuit designers are mainly concerned about the quality of the device, i.e., rds (on) × Qgd. The gate leakage charge Qgd reflects the switching loss of the device, the switching loss is smaller when the Qgd is smaller, and the switching loss is larger when the Qgd is larger; the conduction loss of the device is reflected by the conduction resistance RDS (on), and the smaller the conduction loss of RDS (on), the larger the conduction loss of RDS (on).

The traditional power MOSFET has two important contradictions of on-resistance and breakdown voltage, on-resistance and switching time. In the case where the active regions have the same area, the higher the breakdown voltage, the higher the on-resistance, and the lower the breakdown voltage, the lower the on-resistance. The on-resistance and the switching time are related to the area of the active area, and the larger the area of the active area is, the smaller the on-resistance is, and the longer the switching time is; the smaller the active area, the higher the on-resistance and the shorter the switching time.

Disclosure of Invention

The present invention is directed to a MOSFET device structure and a method for manufacturing the same to solve the above-mentioned problems.

In order to achieve the purpose, the invention adopts the following technical scheme:

a MOSFET device structure comprises an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3, an N + JFET diffusion window 4, a gate dielectric layer 5, gate polysilicon 6, a source N + diffusion window 7, a source P + diffusion window 8 and a gate source isolation layer 9; an N-epitaxial layer 2 is arranged on an N + substrate 1, unit cell main junction P-body diffusion windows 3 of devices are arranged on the left side and the right side of the N-epitaxial layer 2, a gate dielectric layer 5 is arranged in the longitudinal direction of the N + JFET diffusion windows 4, the P-body diffusion windows 3 and the N + JFET diffusion windows 4 between the two P-body diffusion windows 3, a gate polysilicon 6 and a gate source isolation layer 9 are sequentially arranged on the gate dielectric layer 5, a metal layer 10 is arranged on the gate source isolation layer 9, the gate dielectric layer 5 is provided with an active N + diffusion window 7, a source P + diffusion window 8 and a source N + diffusion window 7, the source P + diffusion window 8 and the source metal 10 are connected to form a source, the gate metal 11 is connected to the gate polysilicon 6 through an opening to form a gate, the drain metal is connected to the N + substrate 1 to form a drain, and the source metal 10 is connected to the junction terminal 12.

Further, the device structure is a strip structure or a cellular structure; the gate polysilicon 6 is etched into two sections over the cell.

Furthermore, the N + substrate 1 is made of Si, is doped with AS or Sb, and has the resistivity of 0.002-0.004 ohm-cm; the N-epitaxial layer 2 material is Si material grown by an epitaxial method, doped with P and having resistivity of 0.4-70 omega cm.

Further, the source metal 10 is Al/ALSiCU, and the gate metal is Al/ALSiCU

Further, a method for manufacturing a MOSFET device structure includes the steps of:

the complete manufacturing process flow comprises the following steps: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxygen → field oxygen lithography + etching → photoresist removal → growth of sacrificial oxide layer → N + JFET lithography → injection of N + JFET → annealing of photoresist removal → growth of sacrificial oxide layer → growth of gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → P-body implantation → P-body diffusion → removal of excess residual oxygen → NSD lithography → NSD injection → photoresist removal → activation → deposition of isolation layer → reflow → lead hole lithography + etching → photoresist removal → PSD injection → reflow → aluminum sputtering of metal → aluminum etching + etching → photoresist removal → deposition of passivation layer → lithography + etching → back side of photoresist removal → back side thinning of alloy → back side metallization → CP testing and warehousing.

Further, determining the epitaxial layer resistivity and the epitaxial layer thickness: calculating the epitaxial concentration and thickness meeting a certain breakdown voltage by using a formula (1), wherein the breakdown voltage gives 10-20% of design margin;

the formula (1) shows that: selecting the optimal WB and NB, and determining the lower limit value of the epitaxial resistivity and the upper limit value of the epitaxial thickness:

lower limit of epitaxial resistivity

The upper limit value of the epitaxial concentration is calculated by the following formula (2),

the BVDSS has a design margin of 10% to 20%, and the lower limit of the corresponding resistivity can be calculated by the following formula (3):

wherein q is a unit charge q of 1.6 × 10^-19C，μ_nIs the electron mobility;

upper limit of drift region thickness

After the upper limit value of the epitaxial concentration is determined, the upper limit value of the epitaxial thickness can be calculated by the following equation (4):

the thickness Xmn of the depletion layer expanded in the high-resistance epitaxial region is calculated by the formula (5):

the thickness Xmp of the depletion layer widening in the P-well region is calculated by the equation (6):

further, the manufacturing method of the N + JFET diffusion window 4 comprises the following steps: after the growth of the sacrificial oxide layer and before the injection of the N + JFET, adding a local N + JFET photoetching process, wherein the specific process manufacturing flow is as follows: and (4) growing a sacrificial oxide layer → N + JFET photoetching → N + JFET injection.

Further, the JFET common injection process flow is as follows: epitaxial wafer → laser marking → growth of sacrificial oxide layer → field limiting ring lithography → injection of field limiting ring → photoresist removal → annealing of field limiting ring → removal of oxide layer → growth of field oxygen → field oxygen lithography + etching → photoresist removal → growth of sacrificial oxide layer → injection of N + JFET → photoresist removal → annealing of N + JFET → growth of sacrificial oxide layer → gate oxide layer → polysilicon deposition → polysilicon doping → polysilicon lithography + etching → photoresist removal → injection of P-body → diffusion of P-body → removal of excess oxygen residue → NSD lithography → NSD injection → photoresist removal → activation → isolation layer deposition → reflow → lead hole lithography + etching → photoresist removal → PSD injection → reflow → front side metal aluminum sputtering → aluminum lithography + etching → photoresist removal → passivation layer deposition → PAD lithography + etching → alloy removal → back side metallization → CP testing → warehousing.

Compared with the prior art, the invention has the following technical effects:

mechanism for reducing switch parameters

Miller capacitance Cgd is equivalent to a parallel plate capacitor, and is calculated according to the formulaEpsilon r is the relative dielectric constant, S is the area directly opposite to the capacitor plate, d is the distance of the capacitor plate, and k is the electrostatic force constant. With the new structure of fig. 1, Cgd is reduced by reducing the facing area S of the miller capacitance.

Mechanism for reducing epitaxial resistance

The epitaxial resistance is equivalent to the resistance of a thick wire, and is calculated according to the calculation formula of ohm theoretic resistanceρ is the resistivity of the resistor, L is the length of the resistor, and S is the cross-sectional area of the resistor. As can be seen from the above formula, the materialIs proportional to the resistivity and length of the material and inversely proportional to the area of the material. The epitaxial punch-through design method is to reduce the resistance R of the epitaxial layer in FIG. 2 by reducing the epitaxial resistivity p and the epitaxial thickness (corresponding to the resistance length L)_epi。

Mechanism for reducing JFET resistance through local JFET injection

By local JFET injection, the resistivity rho of the JFET area in figure 2 can be improved, the area S of the JFET area is increased, and the purpose of reducing the resistance R of the JFET area is achieved_JFETThe purpose of (1). Meanwhile, the length L of the channel in the figure 2 can be reduced by local JFET injection, and the effect of reducing the channel resistance Rch can also be indirectly achieved.

The invention relates to an optimized MOSFET design and manufacturing method, under the condition that the layout, the process condition and the static parameters of a product are basically unchanged, the switching parameters can be reduced by 17-23.8% by adopting the MOSFET new structure shown in figure 1; under the condition that the layout is not changed, the on-resistance of the high-voltage MOSFET can be reduced by 12.5% -27.6% by adopting an epitaxial punch-through design method; under the condition that the layout and other process conditions are basically unchanged, the 4.N + JFET diffusion window in the novel structure of the figure 1 is adopted for local JFET injection, so that the on-resistance of the low-voltage MOSFET can be reduced by 11.3% -25.4%.

Drawings

FIG. 1 is a schematic diagram of a unit cell of the structure of the present invention;

wherein, 1, N + substrate; an N-epitaxial layer; a P-body diffusion window; an N + JFET diffusion window; 5. a gate dielectric layer; 6. grid polysilicon; 7. a source N + diffusion window; 8. a source P + diffusion window; 9. a gate-source isolation layer; 10 metal layers.

FIG. 2 is a resistor composition of a MOSFET chip;

FIG. 3 is a layout diagram of the structure of the present invention;

9, a grid source isolation layer; 10 source metal layer; 11. a gate metal; and 12 knots.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

Technical scheme for reducing switch parameters

Referring to fig. 1, an optimized MOSFET design and fabrication method is disclosed. The basic unit structure of the device is a strip structure or a cellular structure, and comprises an N + substrate 1, an N-epitaxial layer 2, a P-body diffusion window 3, an N + JFET diffusion window 4, a gate dielectric layer 5, a gate polysilicon 6 and a gate polysilicon 6 which are etched into two sections on a cellular, a source N + diffusion window 7, a source P + diffusion window 8 and a gate source isolation layer 9, wherein the N-epitaxial layer 2 is arranged on the N + substrate 1, the left side and the right side of the N-epitaxial layer 2 are provided with single cell main junction P-body diffusion windows 3 of the device, the gate dielectric layer 5 is arranged in the longitudinal direction of the N + JFET diffusion window 4, the P-body diffusion window 3 and the N + JFET diffusion window 4 between the two P-body diffusion windows 3, the gate polysilicon 6 and the gate source isolation layer 9 are sequentially arranged on the gate dielectric layer 5, the gate dielectric layer is provided with the source N + diffusion window 7 and the source P + diffusion window 8, the source N + diffusion window 7, the source P + diffusion window 8 and the source metal 10 are connected to form a source electrode, the gate metal is connected with the gate polysilicon 6 to form a gate electrode, and the drain metal is connected with the N + substrate 1 to form a drain electrode.

Design method for epitaxial punch-through for reducing on-resistance

The epitaxial punch-through design method adopts an epitaxial punch-through design concept, and utilizes a formula (1) to calculate the epitaxial concentration and thickness meeting a certain breakdown voltage, wherein the breakdown voltage is provided with 10-20% of design margin in order to meet the reliability of a device.

The formula (1) shows that: for a certain breakdown voltage, infinite (NB, WB) combinations exist, which can meet the requirements, and one group is selected in the design to minimize the on-resistance. To select the optimal WB and NB, the lower limit of the epitaxial resistivity and the upper limit of the epitaxial thickness must be determined.

Lower limit of epitaxial resistivity

The upper limit value of the epitaxial concentration can be calculated by the following formula (2),

in the design, the BVDSS generally leaves a design margin of 10% to 20% in consideration of the reliability of the device. The lower limit value of the corresponding resistivity can be calculated by the following equation (3):

wherein q is a unit charge q of 1.6 × 10^-19C，μ_nIs electron mobility, which is related to the epitaxial concentration.

Upper limit of drift region thickness

After the upper limit value of the epitaxial concentration is determined, the upper limit value of the epitaxial thickness can be calculated by the following equation (4):

namely: the epitaxial thickness exceeding WB does not contribute to the breakdown voltage, but rather causes an increase in the on-resistance Ron.

The thickness Xmn of the depletion layer widening in the high-resistance epitaxial region can be calculated by the formula (5):

the thickness Xmp of the depletion layer widening in the P-well region can be calculated by the equation (6):

the P-well junction depth Xjp is greater than Xmp to avoid channel punch-through while maintaining breakdown voltage.

Injection technical scheme of three local JFETs

The manufacturing method of the N + JFET diffusion window 4 comprises the following steps: after the growth of the sacrificial oxide layer and before the injection of the N + JFET, adding a local N + JFET photoetching process, wherein the specific process manufacturing flow is as follows: the sacrificial oxide layer growth → N + JFET photoetching → N + JFET injection, and the process manufacturing flow before the sacrificial oxide layer growth and after the N + JFET injection is consistent with the JFET common injection flow.

The N + JFET diffusion window 4 is arranged between the two P-body diffusion windows 3, the length of the N + JFET diffusion window 4 is 1.2-7 mu m for products with different breakdown voltages, and the technological parameters are as follows: injecting AsH3 as an injection material, with the injection dosage of 1e 15-1.5 e15, the injection energy of 80 Kev-90 Kev, the activation temperature of 850-900 ℃ and the activation time of 10-15 min.

The technical scheme takes an N-channel MOSFET as an example and is suitable for a P-channel MOFET.

The structure of the invention is realized without additionally adding process equipment, is compatible with the prior MOSFET planar process, and is suitable for irradiating MOSFET products.

In the process manufacturing process, two steps of processes are required to be added: the method comprises the steps of adding a local N + JFET photoetching process after a sacrificial oxide layer grows and before N + JFET injection; and the etching process of local grid polysilicon on the JFET is added in one step.

The scheme can reduce the on-resistance of the MOSFET device, reduce the grid charge and improve the quality FOM of the device.