阅读说明：本技术 显示设备 (Display device ) 是由 金载能 郑昌容 于 2020-03-20 设计创作，主要内容包括：提供一种显示设备,所述显示设备包括包含具有彼此间隔开的多个像素电路的显示区域的基底。无机材料层布置在显示区域中,并且包括多个像素电路中的相邻的像素电路之间的凹槽。有机填料设置在凹槽中。无机材料层包括蚀刻停止层和至少一个绝缘材料层。蚀刻停止层包括半导体材料或导电材料。蚀刻停止层设置在凹槽的侧壁的一部分或底表面上。(A display device is provided that includes a substrate including a display area having a plurality of pixel circuits spaced apart from each other. The inorganic material layer is disposed in the display region and includes a groove between adjacent ones of the plurality of pixel circuits. The organic filler is disposed in the groove. The inorganic material layer includes an etch stop layer and at least one insulating material layer. The etch stop layer includes a semiconductor material or a conductive material. An etch stop layer is disposed on a portion of the sidewalls or bottom surface of the recess.)

1. A display device, the display device comprising:

a substrate including a display area having a plurality of pixel circuits spaced apart from each other;

an inorganic material layer disposed in the display region and having a groove between adjacent pixel circuits of the plurality of pixel circuits; and

an organic filler disposed in the groove,

wherein the inorganic material layer comprises an etch stop layer and at least one insulating material layer,

the etch stop layer comprises a semiconductor material or a conductive material, and

the etch stop layer is disposed on a portion of a sidewall or a bottom surface of the recess.

2. The display device of claim 1, wherein:

the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode; and is

The etch stop layer is disposed on the same layer as the semiconductor layer and includes the same material as that of the semiconductor layer.

3. The display device of claim 1, wherein:

the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode; and is

The etch stop layer is disposed on the same layer as the gate electrode and includes the same material as that of the gate electrode.

4. The display device of claim 1, wherein:

each of the plurality of pixel circuits includes a driving thin film transistor and a storage capacitor arranged to overlap each other; and is

The etch stop layer is disposed on the same layer as an electrode of the storage capacitor and includes the same material as that of the electrode of the storage capacitor.

5. The display device of claim 1, wherein:

the inorganic material layer includes a barrier layer disposed on the substrate; and is

The blocking layer is continuously disposed throughout the plurality of pixel circuits.

6. The display device of claim 1, wherein the organic filler extends to an upper surface of the inorganic material layer.

7. The display device according to claim 1, further comprising a first connection wiring which is overlapped with the plurality of pixel circuits and is arranged on the organic filler.

8. The display device of claim 7, wherein:

the adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction;

the first scanning line of the first pixel circuit and the second scanning line of the second pixel circuit are separated by the organic filler; and is

The first scan line and the second scan line are connected to each other by the first connection wiring.

9. The display device according to claim 8, wherein an elongation of the first connection wiring is larger than an elongation of the first scan line and an elongation of the second scan line.

10. The display device of claim 9, further comprising:

an interlayer insulating layer covering the first connection wiring; and

a second connection wiring arranged on the interlayer insulating layer and configured to connect the plurality of pixel circuits to each other.

11. The display device of claim 10, further comprising:

an opening in the interlayer insulating layer, the opening exposing the organic filler; and

an upper organic filler disposed in the opening,

wherein the first connection wiring and the second connection wiring extend in different directions from each other.

12. The display device according to claim 1, wherein an upper surface of the organic filler has a convex shape.

13. A display device, the display device comprising:

a substrate including a display area having a plurality of pixel circuits spaced apart from each other;

an inorganic material layer disposed in the display region and having a groove in a region between adjacent ones of the plurality of pixel circuits;

the organic filler is arranged in the groove; and

a recess positioned on a sidewall of the groove.

14. The display device of claim 13, wherein:

the inorganic material layer includes a barrier layer disposed on the substrate; and is

The blocking layer is disposed under the recess and is continuously disposed throughout the plurality of pixel circuits.

15. The display device according to claim 13, wherein the organic filler is arranged to surround at least a part of the plurality of pixel circuits.

16. The display device according to claim 13, further comprising a first connection wiring which is overlapped with the plurality of pixel circuits and is arranged on the organic filler.

17. The display device of claim 16, wherein:

the adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction;

the first scanning line of the first pixel circuit and the second scanning line of the second pixel circuit are separated by the organic filler; and is

The first scan line and the second scan line are connected to each other by the first connection wiring.

Technical Field

Exemplary embodiments relate to a display apparatus.

Background

A display apparatus generally includes a display device and a plurality of electronic devices for controlling electrical signals applied to the display device. The electronic device may include a Thin Film Transistor (TFT), a storage capacitor, and a plurality of wirings.

The number of thin film transistors electrically connected to the display device and the number of wirings transmitting electrical signals to the thin film transistors can be increased to precisely control emission or non-emission of the display device and the degree of emission of the display device. Accordingly, much research has been performed on achieving high integration of the display device and thus reducing errors.

Disclosure of Invention

One or more exemplary embodiments provide a display device that is strong to external shock and flexible.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

According to one or more exemplary embodiments, a display device includes a substrate including a display area having a plurality of pixel circuits spaced apart from each other. The inorganic material layer is disposed in the display region and includes a groove between adjacent ones of the plurality of pixel circuits. The organic filler is disposed in the groove. The inorganic material layer includes an etch stop layer and at least one insulating material layer. The etch stop layer includes a semiconductor material or a conductive material. An etch stop layer is disposed on a portion of the sidewalls or bottom surface of the recess.

In an exemplary embodiment, the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode, and the etch stop layer may be disposed on the same layer as the semiconductor layer and include the same material as that of the semiconductor layer.

In an exemplary embodiment, the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode, and the etch stop layer may be disposed on the same layer as the gate electrode and include the same material as that of the gate electrode.

In an exemplary embodiment, the plurality of pixel circuits may each include a driving thin film transistor and a storage capacitor. The driving thin film transistor and the storage capacitor may be disposed to overlap each other, and the etch stop layer may be disposed on the same layer as the electrode of the storage capacitor and include the same material as the electrode of the storage capacitor.

In an exemplary embodiment, the inorganic material layer may include a blocking layer disposed on the substrate, and the blocking layer may be continuously disposed throughout the plurality of pixel circuits.

In an exemplary embodiment, the organic filler may be disposed to surround at least a portion of the plurality of pixel circuits.

In an exemplary embodiment, the organic filler may extend to an upper surface of the inorganic material layer.

In an exemplary embodiment, the display device may further include a first connection wiring overlapping the plurality of pixel circuits and disposed on the organic filler.

In an exemplary embodiment, the adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in the first direction. The first scan line of the first pixel circuit is separated from the second scan line of the second pixel circuit by an organic filler. The first scan line and the second scan line are connected to each other by a first connection wiring.

In an exemplary embodiment, the first connection wiring may have an elongation greater than that of the scan line.

In an exemplary embodiment, the display apparatus may further include: an interlayer insulating layer covering the first connection wiring; and a second connection wiring arranged on the interlayer insulating layer and connecting the plurality of pixel circuits to each other.

In an exemplary embodiment, the first connection wiring and the second connection wiring may extend in different directions, respectively.

In an exemplary embodiment, the insulating material layer may be etched by a fluoride-based gas, and the etch stop layer may be etched by a chloride-based gas.

In an exemplary embodiment, the display device may further include an encapsulation layer sealing the display region and including at least one inorganic encapsulation layer and at least one organic encapsulation layer.

According to an exemplary embodiment of the inventive concept, a display apparatus includes a substrate including a display area having a plurality of pixel circuits spaced apart from each other. The inorganic material layer is disposed in the display region and includes a groove in a region between adjacent ones of the plurality of pixel circuits. The organic filler is disposed in the groove. The recess is positioned on a sidewall of the groove.

In an exemplary embodiment, the inorganic material layer may include a barrier layer disposed on the substrate, and the barrier layer may be disposed under the groove and continuously disposed throughout the plurality of pixel circuits.

In an exemplary embodiment, the organic filler may be disposed to surround at least a portion of the plurality of pixel circuits.

In an exemplary embodiment, the display device may further include a first connection wiring overlapping the plurality of pixel circuits and disposed on the organic filler.

In an exemplary embodiment, the adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in the first direction. The first scan line of the first pixel circuit is separated from the second scan line of the second pixel circuit by an organic filler. The first scan line and the second scan line are connected to each other by a first connection wiring.

In an exemplary embodiment, the first connection wiring may have an elongation greater than that of the scan line.

In another exemplary embodiment of the inventive concept, a method for manufacturing a display device having a plurality of pixel circuits includes forming a lower inorganic material layer on a substrate, the lower inorganic material layer including a barrier layer. An etch stop layer is formed on the lower inorganic material layer. The etch stop layer has a first etch condition. An upper inorganic material layer is formed on the etch stop layer. The upper inorganic material layer has a different etching condition from the etch stop layer. A first etching process is performed on a region of the upper inorganic material layer between adjacent ones of the plurality of pixel circuits to form a first opening in the upper inorganic material layer. A second etching process is performed on a region of the etch stop layer between adjacent pixel circuits to form a second opening in the etch stop layer. A third etching process is performed on a region of the lower inorganic material layer between adjacent pixel circuits to form a third opening in the lower inorganic material layer, the third opening exposing the barrier layer. The first opening, the second opening and the third opening form a recess. An organic filler is formed in the groove.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the exemplary embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a top plan view illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 2 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 3 is an equivalent circuit diagram of a pixel provided in a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 4 is a plan view illustrating positions of a plurality of thin film transistors and storage capacitors in adjacent pixel circuits according to an exemplary embodiment of the inventive concept;

fig. 5A is a sectional view taken along lines I-I 'and II-II' of fig. 4 according to an exemplary embodiment of the inventive concept;

fig. 5B is a cross-sectional view taken along line III-III' of fig. 4 according to an exemplary embodiment of the inventive concept;

fig. 5C is a sectional view taken along the line III-III' of fig. 4 according to another exemplary embodiment of the inventive concept;

fig. 6A to 6F are sectional views sequentially illustrating a process of forming a display apparatus according to an exemplary embodiment of the inventive concept;

fig. 7 is a sectional view taken along lines I-I 'and II-II' of fig. 4, according to an exemplary embodiment of the inventive concept;

fig. 8 is a sectional view taken along lines I-I 'and II-II' of fig. 4, according to an exemplary embodiment of the inventive concept;

fig. 9 is a sectional view taken along lines I-I 'and II-II' of fig. 4, according to an exemplary embodiment of the inventive concept; and

fig. 10 is a sectional view taken along lines I-I 'and II-II' of fig. 4, according to an exemplary embodiment of the inventive concept.

Detailed Description

Reference will now be made in detail to the exemplary embodiments illustrated in the drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present exemplary embodiment may have different forms and should not be construed as being limited to the description set forth herein. Accordingly, the exemplary embodiments are described below merely by reference to the figures to explain various aspects of the specification. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. When a statement such as "at least one of … …" is placed after a list of elements, the entire list of elements is modified and the individual elements in the list are not modified.

Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Like reference numerals designate like or corresponding elements, and thus their description will be omitted.

In the exemplary embodiments set forth herein, terms such as "first", "second", and the like are used to distinguish one component from another component, and are not intended to limit the components.

In exemplary embodiments, expressions used in the singular include expressions in the plural unless they have a clear different meaning in context.

In exemplary embodiments, terms such as "including", "having", and the like, are intended to mean that there are features disclosed in the specification or components thereof, and are not intended to exclude the possibility that one or more other features or components may be present or may be added.

In exemplary embodiments, when a layer, region, or component is referred to as being "on" (e.g., disposed on, positioned on, etc.) another layer, region, or component, the layer, region, or component may be directly on the other layer, region, or component, or intervening layers, regions, or components may be present therebetween.

For convenience of explanation, the sizes of components in the drawings may be exaggerated. In other words, since the size and thickness of components in the drawings may be arbitrarily illustrated for convenience of explanation, the following exemplary embodiments are not limited thereto.

While certain exemplary embodiments may be practiced differently, the specific process sequence may be performed differently than described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described.

In the following exemplary embodiments, when a layer, region or component is connected to another layer, region or component, the layer, region or component may be directly connected to the other layer, region or component, or may be indirectly connected to the other layer, region or component and another layer, region or component may be disposed therebetween. For example, in the specification, when a layer, region or component is electrically connected to another layer, region or component, the layer, region or component may be electrically connected to the other layer, region or component in a direct manner, or may be electrically connected to the other layer, region or component in an indirect manner, with another layer, region or component therebetween.

Fig. 1 is a top plan view illustrating a display apparatus according to an exemplary embodiment of the inventive concept.

Referring to fig. 1, pixels PX included in various types of display devices such as organic light emitting devices (OLEDs, hereinafter, also referred to as organic light emitting diodes) may be arranged in a display area DA of a substrate 110. Various types of wirings for supplying electrical signals to the display area DA may be positioned in the peripheral area PA of the substrate 110. Hereinafter, for convenience of explanation, a display apparatus including an OLED as a display device is described. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the inventive concept can be applied to various types of display devices such as a liquid crystal display device, an electrophoretic display device, an inorganic EL display device, and the like.

Fig. 2 is a block diagram illustrating a display apparatus according to an exemplary embodiment of the inventive concept.

Referring to fig. 2, the display device according to an exemplary embodiment includes a display unit 10 including a plurality of pixels PX, a scan driver 20, a data driver 30, an emission control driver 40, and a controller 50.

The display unit 10 is arranged in the display area DA, and includes a plurality of pixels PX positioned at intersections of a plurality of scanning lines SL1 to SLn +1, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn arranged approximately in the form of a matrix. The plurality of scan lines SL1 to SLn +1 and the plurality of emission control lines EL1 to ELn extend in the second direction as the row direction and are arranged in the first direction as the column direction. The plurality of data lines DL1 to DLm and the driving voltage line elddl are extended in the first direction and arranged in the second direction. "n" and "m" are natural numbers. However, in the pixel line, the n value of the plurality of scan lines SL1 to SLn +1 may be different from the n value of the plurality of emission control lines EL1 to ELn. Further, in other exemplary embodiments, the scan lines, the data lines, and the emission control lines may have various different arrangements.

In the exemplary embodiment shown in fig. 2, each pixel PX is connected to three scan lines among the plurality of scan lines SL1 to SLn + 1. The scan driver 20 generates three scan signals and supplies the three scan signals to each pixel PX through the plurality of scan lines SL1 to SLn + 1. The scan driver 20 may sequentially supply scan signals to the scan lines SL2 to SLn, the previous scan line SL1 to SLn-1, or the next scan line SL3 to SLn + 1.

The initialization voltage line IL may receive an initialization voltage applied from an external power supply VINT and supply the initialization voltage to each pixel PX. Hereinafter, the scan line, the previous scan line, the emission control line, the data line, the initialization voltage line, and the driving voltage line are also denoted by reference numerals "121", "122", "123", "151", "131", and "152", respectively. The "driving voltage" may also be referred to as a "driving power voltage".

Further, each pixel PX is connected to a data line among the plurality of data lines DL1 to DLm. Each pixel PX is also connected to an emission control line among the plurality of emission control lines EL1 through ELn.

The data driver 30 supplies a data signal to each pixel PX through a plurality of data lines DL1 to DLm. Each time a scan signal is supplied to the scan lines SL2 to SLn, a data signal is supplied to the pixel PX selected by the scan signal.

The emission control driver 40 generates an emission control signal and supplies the emission control signal to each pixel PX through a plurality of emission control lines EL1 to ELn. The emission control signal controls an emission period of the pixel PX. However, in some exemplary embodiments, the emission control driver 40 may be omitted depending on the internal structure of the pixel PX.

The controller 50 changes the plurality of image signals IR, IG, and IB into a plurality of image data signals DR, DG, and DB, and supplies the image data signals DR, DG, and DB to the data driver 30. In addition, the controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK and generates control signals to control the operations of the scan driver 20, the data driver 30, and the emission control driver 40. The controller 50 supplies control signals to the scan driver 20, the data driver 30, and the emission control driver 40, respectively. For example, the controller 50 generates and provides the scan driving control signal SCS to control the scan driver 20, generates and provides the data driving control signal DCS to control the data driver 30, and generates and provides the emission driving control signal ECS to control the emission control driver 40.

Each of the plurality of pixels PX receives the driving power voltage ELVDD and the common power voltage ELVSS from the outside (e.g., an external device). The driving power voltage ELVDD may be a high-level voltage, and the common power voltage ELVSS may be a voltage lower than the driving power voltage ELVDD or a ground voltage. The driving power voltage ELVDD is supplied to each pixel PX through the driving voltage line elvdl.

Each of the plurality of pixels PX emits light having a certain luminance by a driving current supplied to the display device in response to the data signals supplied through the plurality of data lines DL1 to DLm.

Fig. 3 is an equivalent circuit diagram of a pixel provided in a display apparatus according to an exemplary embodiment of the inventive concept.

Referring to fig. 3, each pixel PX includes a signal line including a scan line 121, a previous scan line 122, an emission control line 123, and a data line 151. Each pixel PX further includes an initialization voltage line 131, a pixel circuit PC connected to the driving voltage line 152, and a display device, exemplified by an organic light emitting diode OLED, connected to the pixel circuit PC.

The pixel circuit PC includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7 and a storage capacitor Cst.

Fig. 3 illustrates an exemplary embodiment in which a signal line, an initialization voltage line 131, and a driving voltage line 152 are disposed in each pixel PX. However, exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, at least one of the signal lines and/or the initialization voltage line 131 may be shared by adjacent pixels.

The plurality of thin film transistors may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7.

The signal line includes: a scan line 121 supplying a scan signal Sn; a previous scan line 122 supplying a previous scan signal Sn-1 to the first and second initializing thin film transistors T4 and T7; an emission control line 123 supplying an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6; and data lines 151 crossing the scan lines 121 and supplying data signals Dm. The driving voltage line 152 supplies a driving power voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line 131 supplies an initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode.

The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first electrode Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line 152 via the operation controlling thin film transistor T5. The driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting device OLED via the emission controlling thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm and drives the current I in response to the switching operation of the switching thin film transistor T2_OLEDTo the organic light emitting device OLED.

The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line 121. The switching source electrode S2 of the switching thin film transistor T2 is connected to the data line 151. The switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is also connected to the driving voltage line 152 via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn supplied through the scan line 121, and performs a switching operation to supply the data signal Dm supplied through the data line 151 to the driving source electrode S1 of the driving thin film transistor T1.

The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line 121. The compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1, and is also connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the first electrode Cst1 of the storage capacitor Cst, the first initialization source electrode S4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn supplied through the scan line 121, and electrically connects the driving gate electrode G1 and the driving drain electrode D1 in the driving thin film transistor T1 to each other, thereby diode-connecting the driving thin film transistor T1.

The first initializing gate electrode G4 of the first initializing thin film transistor T4 is connected to the previous scan line 122. The first initializing drain electrode D4 of the first initializing thin film transistor T4 is connected to the second initializing drain electrode D7 of the second initializing thin film transistor T7 and the initializing voltage line 131. The first initializing source electrode S4 of the first initializing thin film transistor T4 is connected to the compensating drain electrode D3 of the compensating thin film transistor T3 and the driving gate electrode G1 of the driving thin film transistor T1. The first initializing thin film transistor T4 is turned on in response to the previous scan signal Sn-1 supplied through the previous scan line 122 and supplies an initializing voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby performing an initializing operation to initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line 123. The operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line 152. The operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

An emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line 123. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En supplied through the emission control line 123 such that the driving power voltage ELVDD is supplied to the organic light emitting diode OLED and the driving current I_OLEDFlows through the organic light emitting diode OLED.

The second initializing gate electrode G7 of the second initializing thin film transistor T7 is connected to the previous scan line 122. The second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the pixel electrode of the organic light emitting diode OLED. The second initializing drain electrode D7 of the second initializing thin film transistor T7 is connected to the first initializing drain electrode D4 of the first initializing thin film transistor T4 and the initializing voltage line 131. The second initializing thin film transistor T7 is turned on in response to the previous scan signal Sn-1 supplied through the previous scan line 122 and initializes the pixel electrode of the organic light emitting diode OLED.

In fig. 3, the first and second initializing thin film transistors T4 and T7 are connected to the previous scan line 122. However, the exemplary embodiments are not limited thereto. In another exemplary embodiment, the first initializing thin film transistor T4 may be connected to the previous scan line 122 and driven in response to the previous scan signal Sn-1, and the second initializing thin film transistor T7 may be connected to another signal line (e.g., a next scan line) and driven in response to a signal supplied thereto. However, the positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 may be exchanged with each other according to the type of transistor (p-type or n-type). Further, in other exemplary embodiments, the number of transistors, their functions, and arrangement may be modified from the exemplary embodiment shown in fig. 3.

The specific operation of the corresponding pixel PX according to an exemplary embodiment is as follows:

in the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line 122, the first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1, and the driving thin film transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line 131.

In the data programming period, when the scan signal Sn is supplied through the scan line 121, the switching thin film transistor T2 and the compensating thin film transistor T3 are turned on in response to the scan signal Sn. At this time, the driving thin film transistor T1 is diode-connected through the turned-on compensation thin film transistor T3 and biased in a forward direction.

A compensation voltage Dm + Vth (Vth is a negative value), which is a value obtained by subtracting the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied from the data line 151, is applied to the driving gate electrode G1 of the driving thin film transistor T1.

The driving power voltage ELVDD and the compensation voltage Dm + Vth are applied to both ends of the storage capacitor Cst, respectively, and charges corresponding to a difference between the driving power voltage ELVDD and the compensation voltage Dm + Vth are stored in the storage capacitor Cst.

In the emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on in response to the emission control signal En supplied from the emission control line 123. Generating a driving current I depending on a voltage difference between a voltage of the gate electrode G1 of the driving thin film transistor T1 and a driving power voltage ELVDD_OLED. Drive current I_OLEDIs supplied to the organic light emitting diode OLED through the emission controlling thin film transistor T6.

Fig. 4 is a plan view showing the positions of a plurality of thin film transistors and storage capacitors in adjacent pixel circuits. Fig. 5A is a sectional view taken along lines I-I 'and II-II' of fig. 4.

Referring to fig. 4 and 5A, a display device according to an exemplary embodiment of the inventive concept includes an inorganic material layer having grooves GR in regions between a plurality of pixel circuits (e.g., a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3), and an organic filler 161 disposed in the grooves GR and filling the grooves GR. The etch stop layer ES is disposed on a portion of the sidewalls or bottom surface of the groove GR.

The display apparatus according to an exemplary embodiment may include: a first connection wire 140 disposed on the organic fillers 161 and crossing the organic fillers 161 in a first direction; and/or a second connection wire 150 disposed on the organic filler 161 and crossing the organic filler 161 in the second direction.

In exemplary embodiments of the inventive concept, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES are disposed under the first connection wiring 140, and include an inorganic material. The barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES may be collectively referred to as an inorganic material layer. The inorganic material layer includes grooves GR located in regions between adjacent pixels. For example, as shown in fig. 4 and 5A, the groove GR may be located in a region between the first pixel circuit PX1 and the second pixel circuit PX2 in the first direction. The groove GR may also be located in a region between the first pixel circuit PX1 and the third pixel circuit PX3 in the second direction.

In example embodiments of the inventive concept, the etch stop layer ES may represent a layer having an etch rate different from that of other layers (e.g., the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114) included in the inorganic material layer. The etch stop layer ES may also mean a layer etched by an etching condition different from that of the above-mentioned layer.

In some exemplary embodiments, the etching is performedThe stop layer ES may include a semiconductor material or a metal. In these embodiments, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include, for example, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Or silicon oxynitride (SiON) insulating material.

Fig. 5A shows an exemplary embodiment in which the inorganic material layer includes grooves GR. For example, the barrier layer 101 may be continuously formed throughout the first and second pixel circuits PC1 and PC2 adjacent to each other. The buffer layer 111, the etch stop layer ES, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may have openings 111a, ESa, 112a, 113a, and 114a, respectively, in a region between adjacent pixels to form portions of the groove GR in the region.

Accordingly, the inorganic material layer including the barrier layer 101, the buffer layer 111, the etch stop layer ES, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include a groove GR in a region between adjacent pixels. The groove GR may represent a groove formed in the inorganic material layer.

In other exemplary embodiments of the inventive concept, the inorganic material layer may include a groove GR having a shape different from that of the groove GR shown in fig. 5A, and the groove GR may be variously modified. For example, in one embodiment, the bottom of the buffer layer 111 may remain, and the opening 111a may be formed in a region above the bottom of the buffer layer 111.

In an exemplary embodiment, the width GRW of the groove GR in the inorganic material layer may be several μm. For example, the width GRW of the groove GR in the inorganic material layer may be about 5 μm to about 10 μm.

The groove GR may be formed by using an additional mask process and etching process after the third gate insulating layer 114 is formed. In the present exemplary embodiment, the etch stop layer ES may be provided for the accuracy of the etching process. The steps of etching the stop layer ES and forming the groove GR by the etching process will be described later.

The grooves GR in the inorganic material layer may be filled with an organic filler 161. The first and second connection wirings 140 and 150 may be disposed on the organic filler 161 (e.g., directly on the organic filler 161 or directly over the organic filler 161) in a region in which the organic filler 161 is positioned.

The groove GR of the inorganic material layer and the organic filler 161 may be at least partially located between the plurality of pixel circuits. In fig. 4, the groove GR of the inorganic material layer and the organic filler 161 are positioned (e.g., in a plane formed by the first direction and the second direction) to surround each of the first pixel circuit PC1 and the second pixel circuit PC 2. For example, the organic fillers 161 are arranged to surround the outer circumference of the first pixel circuit PC1 and the outer circumference of the second pixel circuit PC2 to form a series of connected rectangular shapes surrounding the pixels. However, exemplary embodiments of the inventive concept are not limited thereto.

For example, the groove GR of the inorganic material layer and the organic filler 161 therein may be formed to extend from a region between the first and second pixel circuits PC1 and PC2 in the second direction without surrounding each of the first and second pixel circuits PC1 and PC 2. In addition, the grooves GR of the inorganic material layer and the organic filler 161 may be variously modified. For example, the groove GR of the inorganic material layer and the organic filler 161 may be formed to extend in the first direction from a region between the plurality of pixel circuits.

The grooves GR of the inorganic material layer and the organic filler 161 may minimize impact on the display device due to external shock. Since the inorganic material layer has a higher robustness than that of the organic filler 161, there is a high possibility that cracks may be generated due to external shock. When a crack is generated in the inorganic material layer, cracks may also be generated in various signal lines disposed in the middle or the top of the inorganic material layer. Therefore, there is a high possibility that defects such as disconnection may be generated due to cracks in the inorganic material layer.

However, in the display apparatus according to the exemplary embodiments of the inventive concept, since the inorganic material layer has the groove GR including the organic filler 161 in the region between the plurality of pixels, there is a low possibility of crack propagation when there is an external shock. Further, since the organic filler 161 has lower solidity than the inorganic material layer, the organic filler 161 can absorb stress due to external shock and effectively minimize any stress directed to the first and second connection wirings 140 and 150 positioned on the organic filler 161.

The first and second connection wirings 140 and 150 disposed on the organic filler 161 may connect the plurality of pixel circuits to each other. For example, as shown in fig. 5A, the first connection wiring 140 may connect the first pixel PX1 to the adjacent second pixel PX 2. The first and second connection wirings 140 and 150 may be disposed on the inorganic material layer in a region where the organic filler 161 is not positioned. The first and second connection wirings 140 and 150 may be used as lines for supplying electrical signals to the plurality of pixel circuits.

The first and second connection wirings 140 and 150 may extend in a length (e.g., the first connection wiring 140 in the first direction and the second connection wiring 150 in the second direction) greater than that of the other lines. Therefore, stress to the display device due to vibration is more likely to be applied to the first and second connection wirings 140 and 150 than other elements of the display device.

In an exemplary embodiment, the first and second connection wirings 140 and 150 include a material having a high elongation. For example, the first and second connection wirings 140 and 150 may include aluminum. However, exemplary embodiments of the inventive concept are not limited thereto. Accordingly, the first and second connection wirings 140 and 150 including a material having a high elongation may absorb shock while preventing an error such as a crack or a disconnection from occurring. The first and second connection wirings 140 and 150 may have a multi-layered structure as necessary. In some exemplary embodiments, a stacked structure including Ti/Al/Ti may be applied to the first and second connection wirings 140 and 150. In some exemplary embodiments, the first and second connection wirings 140 and 150 may have a higher elongation than the material of the layer disposed thereunder.

Hereinafter, referring to fig. 4 and 5A, a display apparatus according to an exemplary embodiment will be described in detail.

The substrate 110 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. For example, in embodiments in which the substrate 110 is flexible or bendable, the substrate 110 may include a high molecular weight resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto. The substrate 110 may have a single layer or a multi-layer structure including the above-mentioned materials. In embodiments having a multilayer structure, the substrate 110 may further include an inorganic layer. In some exemplary embodiments, the substrate 110 may have a structure including a combination of an organic material and an inorganic material.

The display device may further include a barrier layer 101 between the substrate 110 and the buffer layer 111. For example, as shown in the exemplary embodiment of fig. 5A, barrier layer 101 may be disposed directly on substrate 110. The barrier layer 101 may prevent impurities (such as impurities from the substrate 110) from penetrating into the semiconductor layer, or minimize impurities (such as impurities from the substrate 110) penetrating into the semiconductor layer. In an exemplary embodiment, the barrier layer 101 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material. The barrier layer 101 may include a single layer structure or a multi-layer structure including an inorganic material and an organic material.

The buffer layer 111 may be disposed on the barrier layer 101. For example, as shown in the exemplary embodiment of fig. 5A, the buffer layer 111 may be disposed directly on the barrier layer 101. The buffer layer 111 may improve the smoothness of the upper surface of the substrate 110. In an exemplary embodiment, the buffer layer 111 may include an inorganic material such as silicon oxide, silicon nitride, and/or silicon oxynitride. However, exemplary embodiments of the inventive concept are not limited thereto.

Semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are disposed on the buffer layer 111. For example, as shown in the exemplary embodiment of fig. 5A, the semiconductor layer may be directly disposed on the buffer layer 111. In an exemplary embodiment, the semiconductor layers may include the same material. For example, the semiconductor layer may include polysilicon, amorphous silicon, or an oxide semiconductor. However, exemplary embodiments of the inventive concept are not limited thereto. The semiconductor layers may be connected to each other and may be bent in various shapes.

The semiconductor layer may include a channel region, a source region, and a drain region. For example, as shown in fig. 5A, the semiconductor layers of the driving thin film transistor T1 and the emission controlling thin film transistor T6 may include respective channel regions a1, a6, respective source regions S1, S6, and respective drain regions D1, D6. The source regions S1 and S6 and the drain regions D1 and D6 are disposed on sides adjacent to the channel regions a1 and a6, respectively. The source and drain regions may be doped with impurities, and the impurities may include n-type impurities or p-type impurities. The source region and the drain region correspond to the source electrode and the drain electrode, respectively. Hereinafter, the terms "source region" and "drain region" will be used instead of the source electrode and the drain electrode.

A first gate insulating layer 112 is positioned on the semiconductor layer. For example, as shown in the exemplary embodiment of fig. 5A, the first gate insulating layer 112 may be directly disposed on the semiconductor layer. The first gate insulating layer 112 may include an inorganic material including an oxide material or a nitride material. For example, the first gate insulating layer 112 may include silicon dioxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium dioxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Zinc oxide (ZnO), and the like. However, exemplary embodiments of the inventive concept are not limited thereto.

In this embodiment, the semiconductor layers of the plurality of pixel circuits are formed separately from each other. For example, the semiconductor layer of the first pixel circuit PC1 is spaced apart from the semiconductor layer of the second pixel circuit PC2 (e.g., spaced apart in the first direction). However, in other exemplary embodiments of the inventive concept, at least one semiconductor layer may be integrally formed between a plurality of pixel circuits.

The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are disposed on the first gate insulating layer 112. The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are disposed on the same layer and include the same material. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may each include a single layer or a plurality of layers. However, exemplary embodiments of the inventive concept are not limited thereto.

The driving gate electrode G1 is an island-type electrode, and is arranged to cover the driving channel region a1 in the driving semiconductor layer (e.g., in the direction of the thickness of the substrate 110). The driving gate electrode G1 may function not only as a gate electrode of the driving thin film transistor T1 but also as the first electrode Cst1 of the storage capacitor Cst. For example, the driving gate electrode G1 and the first electrode Cst1 may be integrally formed.

Portions or protrusions of the scan line 121, the previous scan line 122, and the emission control line 123 correspond to gate electrodes of the thin film transistors T2 to T7.

For example, portions of the scan line 121 overlapping the switching channel region and the compensation channel region correspond to the switching gate electrode G2 and the compensation gate electrode G3, respectively. In the previous scan line 122, regions overlapping the first and second initializing channel regions correspond to the first and second initializing gate electrodes G4 and G7, respectively. In the emission control line 123, regions overlapping the operation control channel region and the emission control channel region correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

In the present exemplary embodiment, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of each of the plurality of pixel circuits are formed separately from each other. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the drive gate electrode G1 of the first pixel circuit PC1 may be formed to be discontinuous and spaced apart (e.g., discontinuous and spaced apart in the first direction) from the scan line 121, the previous scan line 122, the emission control line 123, and the drive gate electrode G1 of the second pixel circuit PC2, respectively.

In this embodiment, the scan line 121, the previous scan line 122, and the emission control line 123 of the first pixel circuit PC1 may be connected to the scan line 121, the previous scan line 122, and the emission control line 123 of the second pixel circuit PC2, respectively, through the first connection wiring 140 disposed on another layer.

The second gate insulating layer 113 is disposed on the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1. For example, the second gate insulating layer 113 may be directly disposed on the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1. The second gate insulating layer 113 may include an inorganic material including an oxide material or a nitride material. For example, the second gate insulating layer 113 may include SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂ZnO, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

The second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 are positioned on the second gate insulating layer 113. The second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 are disposed on the same layer and include the same material. For example, the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 may include a material including Mo, Cu, Ti, etc., and may be formed as a multi-layer or a single layer including the above-mentioned materials. However, exemplary embodiments of the inventive concept are not limited thereto.

In the present exemplary embodiment, the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 of each of the plurality of pixel circuits are discontinuous and spaced apart from each other. For example, the second electrode Cst2 of the storage capacitor Cst of the first pixel circuit PC1 and the second electrode Cst2 of the storage capacitor Cst of the second pixel circuit PC2 are spaced apart from each other (e.g., spaced apart from each other in the first direction) and separated from each other. The initialization voltage line 131 of the first pixel circuit PC1 and the initialization voltage line 131 of the second pixel circuit PC2 are spaced apart from each other (e.g., spaced apart from each other in the first direction) and separated from each other.

Third gate insulating layer 114 are disposed on the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131. For example, the third gate insulating layer 114 may be disposed directly on the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131. The third gate insulating layer 114 may include an inorganic material including an oxide material or a nitride material. For example, the third gate insulating layer 114 may include SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂ZnO, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

The first connection wiring 140 extending in the first direction is disposed on the third gate insulating layer 114. For example, as shown in fig. 5A, the first connection wiring 140 may be directly disposed on the third gate insulating layer 114. The first connection wiring 140 extends from the first pixel circuit PC1 to the second pixel circuit PC2, and connects the pixel circuits to each other. The first connection wiring 140 may connect a plurality of pixel circuits arranged in the first direction.

In the present exemplary embodiment, conductive layers of the semiconductor layer, the scan line 121, the previous scan line 122, the emission control line 123, the initialization voltage line 131, the first electrode Cst1 and the second electrode Cst2 of the storage capacitor Cst, and the like are discontinuously and separately formed in each pixel circuit. Therefore, it is possible to prevent the stress that may be generated in one pixel circuit from being propagated to another pixel circuit. In addition, since the first connection wiring 140 may include a material having a high elongation, an error due to stress may be minimized.

The first connection wiring 140 may include an emission control connection line 141, a grid connection line 142, a scan connection line 143, a previous scan connection line 144, and an initialization voltage connection line 145. Although the line I-I' of fig. 5A shows the mesh connection line 142 with respect to the first connection wiring 140, a similar structure may be used for the emission control connection line 141, the scan connection line 143, the previous scan connection line 144, and the initialization voltage connection line 145.

The emission control connection line 141 connects the emission control line 123 of the first pixel circuit PC1 with the emission control line 123 of the second pixel circuit PC2 through contact holes CNT1a and CNT2a formed to penetrate the third gate insulating layer 114 and the second gate insulating layer 113. The emission control connection line 141 may overlap the emission control line 123 of the first pixel circuit PC1 and the emission control line 123 of the second pixel circuit PC2 (e.g., overlap in a direction of the thickness of the substrate 110) and extend in the first direction.

The grid connection line 142 connects the second electrode Cst2 of the first pixel circuit PC1 and the second electrode Cst2 of the second pixel circuit PC2 via contact holes CNT3a and CNT2b formed through the third gate insulating layer 114. Since the second electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line 152 and receives the driving voltage, the grid connection line 142 may transmit the driving voltage to the plurality of pixels arranged in the first direction. Accordingly, the driving voltage lines having the mesh structure may be formed by the mesh connection lines 142 without an additional area for accommodating separate driving voltage lines extending in the first direction. Accordingly, this configuration provides an additional region for the storage capacitor Cst to provide a high-definition display device.

The scan connection line 143 connects the scan line 121 of the first pixel circuit PC1 and the scan line 121 of the second pixel circuit PC2 through contact holes CNT4a and CNT4b formed through the third gate insulating layer 114 and the second gate insulating layer 113. The scan link line 143 may overlap the scan line 121 of the first pixel circuit PC1 and the scan line 121 of the second pixel circuit PC2 (e.g., overlap in a direction of a thickness of the substrate 110) and extend in the first direction.

The previous scan link line 144 connects the previous scan line 122 of the first pixel circuit PC1 with the previous scan line 122 of the second pixel circuit PC2 via contact holes CNT5a and CNT5b formed through the third gate insulating layer 114 and the second gate insulating layer 113. The previous scan connection line 144 may overlap (e.g., overlap in a direction of a thickness of the substrate 110) the previous scan line 122 of the first pixel circuit PC1 and the previous scan line 122 of the second pixel circuit PC 2.

The initialization voltage connection line 145 connects the initialization voltage line 131 of the first pixel circuit PC1 to the initialization voltage line 131 of the second pixel circuit PC2 through contact holes CNT6a and CNT6b formed through the third gate insulating layer 114. The initialization voltage connection line 145 may overlap the initialization voltage line 131 of the first pixel circuit PC1 and the initialization voltage line 131 of the second pixel circuit PC2 (e.g., overlap in a direction of a thickness of the substrate 110) and extend in the first direction.

As described above, the first connection wiring 140 may supply an electrical signal to the plurality of pixel circuits by connecting adjacent pixel circuits (e.g., the first pixel circuit PC1 and the second pixel circuit PC2) in a region disposed on the organic filler 161 or above the organic filler 161 between the adjacent pixel circuits.

The interlayer insulating layer 115 is disposed on the first connection wiring 140. For example, the interlayer insulating layer 115 may be directly disposed on the first connection wiring 140. The interlayer insulating layer 115 may include an inorganic material including an oxide material or a nitride material. For example, the interlayer insulating layer 115 may include SiO₂、SiN_x、SiON、Al₂O₃、TiO₂、Ta₂O₅、HfO₂ZnO, etc. However, exemplary embodiments of the inventive concept are not limited thereto. In some example embodiments, the interlayer insulating layer 115 may include an organic material such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane. In an exemplary embodiment in which the interlayer insulating layer 115 includes an organic material, stress applied to wirings disposed above the interlayer insulating layer 115 and below the interlayer insulating layer 115 may be reduced.

The second connection wiring 150 extending in the second direction is positioned on the interlayer insulating layer 115. The second connection wiring 150 is insulated from the first connection wiring 140 by the interlayer insulating layer 115. For example, as shown in fig. 5A, the second connection wiring 150 may be directly disposed on the interlayer insulating layer 115. The second connection wiring 150 may include a data line 151, a driving voltage line 152, a first node connection line 153, a second node connection line 154, and an intermediate connection line 155.

The data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the intermediate connection line 155 are disposed on the same layer and include the same material. For example, the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the intermediate connection line 155 may include a conductive material having a high elongation.

Although the line II-II' of fig. 5A shows the intermediate connection line 155 with respect to the second connection wiring 150, a similar structure may be used for the data line 151, the driving voltage line 152, the first node connection line 153, and the second node connection line 154.

The data line 151 is connected to the switching thin film transistor T2 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The data line 151 may connect a plurality of pixel circuits arranged in the second direction.

The driving voltage line 152 is connected to the operation controlling thin film transistor T5 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. In addition, the driving voltage line 152 is connected to the second electrode Cst2 of the storage capacitor Cst via a contact hole penetrating the interlayer insulating layer 115 and the third gate insulating layer 114. The driving voltage line 152 may connect a plurality of pixel circuits arranged in the second direction.

The first node connection line 153 is connected to the first and second initializing thin film transistors T4 and T7 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The first node connection line 153 is also connected to the initialization voltage line 131 via a contact hole penetrating the interlayer insulating layer 115 and the third gate insulating layer 114.

The second node connection line 154 connects the driving gate electrode G1 with the compensation drain region of the compensation thin film transistor T3 via a contact hole. The driving gate electrode G1 is an island-type electrode that may be electrically connected to the compensation thin film transistor T3.

The intermediate connection line 155 may be connected to the second initializing thin film transistor T7 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. As shown in fig. 5A, the intermediate connection line 155 may be connected to the emission control thin film transistor T6 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112.

The data line 151, the driving voltage line 152, and the intermediate connection line 155 may connect pixel circuits (e.g., the first pixel circuit PC1 and the third pixel circuit PC3) adjacent to each other in the second direction and span the groove GR and the organic filler 161 therebetween.

The planarization layer 116 is disposed on the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the intermediate connection line 155. For example, the planarization layer 116 may be directly disposed on the data lines 151, the driving voltage lines 152, the first node connection lines 153, the second node connection lines 154, and the intermediate connection lines 155. The planarization layer 116 may include an organic material such as acryl (acryl), BCB, PI, or HMDSO. However, exemplary embodiments of the inventive concept are not limited thereto. Alternatively, the planarization layer 116 may include an inorganic material. The planarization layer 116 may have a function of substantially planarizing an upper portion of the protective film covering the thin film transistors T1 to T7. The planarization layer 116 may be provided as a single layer or a plurality of layers.

Referring to fig. 5A, the organic filler 161 is disposed to at least partially fill the groove GR of the inorganic material layer between the first and second pixel circuits PC1 and PC 2. The organic filler 161 may not completely fill the groove GR. In addition, some grooves GR may not include the organic filler 161 therein.

However, in the exemplary embodiment, the organic filler 161 completely fills the groove GR to increase the absorption of external impact. In some exemplary embodiments, the organic filler 161 may be formed to extend to an upper surface of the inorganic material layer. In this embodiment, the upper surface of the organic filler 161 may be provided in a convex shape in consideration of the properties of the organic filler 161. For example, the maximum height h of the organic filler 161 may extend from the upper surface of the barrier layer 101 to above the third gate insulating layer 114. The maximum height h of the organic filler 161 may be formed to be greater than the depth d of the groove GR extending from the upper surface of the barrier layer 101 to the upper surface of the third gate insulating layer 114.

An angle of a line extending from the upper surface of the organic filler 161 to the upper surface of the inorganic material layer may be within 45 degrees. For example, the angle of a line extending from the upper surface of the organic filler 161 to the upper surface of the inorganic material layer may be in the range of 10 ° to 45 °. When the slope of the boundary region between the inorganic material layer and the upper surface of the organic filler 161 is not flat, the conductive material of the first connection wiring 140 may remain in the boundary region without being removed when the process of forming the first connection wiring 140 by patterning the conductive layer is performed. Therefore, the conductive material remaining due to the non-gentle slope of the boundary region between the inorganic material layer and the upper surface of the organic filler 161 may cause a short circuit between the other conductive layers. Therefore, it is preferable that the upper surface of the organic filler 161 is formed to have a gentle slope with respect to the upper surface of the inorganic material layer.

In an exemplary embodiment, the organic filler 161 may include one or more materials from among acrylic resin, methacrylic resin (methacrylic), polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinylsulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the inventive concept are not limited thereto.

The organic filler 161 may be disposed in the groove GR of the inorganic material layer in a region between the first and second pixel circuits PC1 and PC2, and may separate the first and second pixel circuits PC1 and PC2 from each other in a portion under the first connection wiring 140. The groove GR and the organic filler 161 therein prevent stress from propagating from the first pixel circuit PC1 to the second pixel circuit PC2 and/or prevent cracks from forming from the first pixel circuit PC1 to the second pixel circuit PC 2.

The organic light emitting diode OLED includes a pixel electrode 310, a counter electrode 330, and an intermediate layer 320 positioned between the pixel electrode 310 and the counter electrode 330. The intermediate layer 320 includes an emission layer (EML). The organic light emitting diode OLED may be disposed on the planarization layer 116.

The pixel electrode 310 is connected to the intermediate connection line 155 via a contact hole CNT1b defined in the planarization layer 116, and is connected to the emission control drain region D6 of the emission control thin film transistor T6 through the intermediate connection line 155.

The pixel defining layer 117 may be disposed on the planarization layer 116. The pixel defining layer 117 defines pixels by having an opening corresponding to each sub-pixel. For example, the opening exposes at least a central region of the pixel electrode 310. The pixel defining layer 117 also prevents an arc or the like from occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel defining layer 117 may include an organic material, for example, PI, HMDSO, or the like. However, exemplary embodiments of the inventive concept are not limited thereto.

The intermediate layer 320 of the organic light emitting diode OLED may include a low molecular weight material or a high molecular weight material. When the interlayer 320 includes a low molecular weight material, the Hole Injection Layer (HIL), the emission layer (EML), the Electron Transport Layer (ETL), the Electron Injection Layer (EIL), and the like may each have a single layer structure or a multi-layer stack structure, and the low molecular weight material may include materials such as copper phthalocyanine (CuPc), N '-di (naphthalene-1-yl) -N, N' -diphenyl-benzidine (NPB), tris (8-hydroxyquinoline) aluminum (Alq)₃) Various organic materials of (2). Such a layer may be formed by a vacuum deposition method. However, exemplary embodiments of the inventive concept are not limited thereto.

An exemplary embodiment in which the intermediate layer 320 includes a high molecular weight material may generally have a structure including a Hole Transport Layer (HTL) and an emission layer (EML). In this embodiment, the HTL may comprise poly (3, 4-ethylenedioxythiophene) (PEDOT), and the EML may comprise high molecular weight materials such as poly (phenylene vinylene) and polyfluorene. The intermediate layer 320 may be formed by using a screen printing method, an inkjet printing method, a Laser Induced Thermal Imaging (LITI) method, or the like.

However, the intermediate layer 320 is not limited thereto, and may have various structures. In addition, the intermediate layer 320 may include a layer integrally formed over the plurality of pixel electrodes 310, and may further include a layer patterned to correspond to each of the pixel electrodes 310.

The counter electrode 330 is disposed in an upper portion of the display area DA (e.g., in an upper portion in the direction of the thickness of the substrate 110). The counter electrode 330 may be disposed to cover the display area DA, as shown in fig. 5A. For example, the counter electrode 330 may be integrally formed with respect to the organic light emitting diodes OLED of the plurality of pixel circuits.

Since the organic light emitting diode OLED may be easily damaged due to moisture or oxygen from the outside, the encapsulation layer 400 may be used for protection to cover the organic light emitting diode OLED. The encapsulation layer 400 may cover the display area DA and extend to an outer area of the display area DA. In an exemplary embodiment, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. However, exemplary embodiments of the inventive concept are not limited thereto.

The first inorganic encapsulation layer 410 may cover the counter electrode 330 and include ceramic, metal oxide (e.g., indium oxide (In)₂O₃) Tin oxide (SnO)₂) Indium Tin Oxide (ITO)), metal nitrides, metal carbides, metal oxynitrides, silicon oxide, silicon nitride, and/or silicon oxynitride, and the like. However, exemplary embodiments of the inventive concept are not limited thereto. In some embodiments, additional layers (e.g., cap layers, etc.) may be disposed between the first inorganic encapsulation layer 410 and the counter electrode 330 as desired. Since the first inorganic encapsulation layer 410 is formed over the structure having the non-uniform thickness, the upper surface of the first inorganic encapsulation layer 410 is not uniformly formed.

The organic encapsulation layer 420 covers the first inorganic encapsulation layer 410. The upper surface of the organic encapsulation layer 420 may be approximately flat (e.g., approximately smooth). The upper surface of the organic encapsulation layer 420 may be approximately smooth in a portion corresponding to the display area DA. The organic encapsulation layer 420 may include one or more materials from among acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinylsulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the inventive concept are not limited thereto.

The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420. The second inorganic encapsulation layer 430 may include ceramic, metal oxide(e.g., In)₂O₃、SnO₂ITO), metal nitrides, metal carbides, metal oxynitrides, silicon oxide, silicon nitride, and/or silicon oxynitride, and the like. However, exemplary embodiments of the inventive concept are not limited thereto.

As described above, the encapsulation layer 400 includes the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430. The multi-layer structure may prevent cracks occurring in the encapsulation layer 400 from being connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Accordingly, it is possible to prevent or minimize the formation of a path through which external moisture or oxygen may permeate into the display area DA.

A spacer for preventing the mask from being chipped may be further provided on the pixel defining layer 117. In addition, various functional layers such as a polarizing layer and a black matrix that reduce reflection of external light, a color filter, and/or a touch screen layer including touch electrodes may be disposed on the encapsulation layer 400.

In the present embodiment, the groove GR is provided in the inorganic material layer arranged between the pixel circuits adjacent to each other. In this embodiment, the etch stop layer ES is disposed on a portion of the sidewall or bottom surface of the groove GR.

The etch stop layer ES may represent a layer having an etch rate different from that of other layers (e.g., the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114) included in the inorganic material layer. The etch stop layer ES may also represent a layer having an etch condition different from that of other layers included in the inorganic material layer.

In some exemplary embodiments, the etch stop layer ES may include a semiconductor material or a metal. In this embodiment, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include, for example, SiO_x、SiN_xOr an insulating material of SiON.

Referring to fig. 5A, the etch stop layer ES and the semiconductor layer of the driving thin film transistor T1 may be disposed on the same layer and include the same material. For example, the etch stop layer ES may be disposed on the buffer layer 111 to form a portion of the sidewall of the groove GR. Alternatively, the etch stop layer ES may be disposed in other layers to surround the groove GR and/or the organic filler 161. The width ESW of the etch stop layer ES from the first side edge to the opposite second side edge may be greater than the width GRW of the groove GR.

The etch stop layer ES may include an opening ESa corresponding to the groove GR. The opening ESa may form part of the groove GR.

In the present exemplary embodiment, the etch stop layer ES may serve to prevent damage to the barrier layer 101 by adjusting the depth of the groove GR. For example, the etch stop layer ES may be provided for the accuracy of an etching process performed for forming the groove GR.

Fig. 5B is a cross-sectional view taken along line III-III' of fig. 4 according to another exemplary embodiment.

Referring to fig. 5B, a first end of the intermediate connection line 155 may be connected to the first semiconductor layer ACT1 of the first pixel circuit PC1 through a contact hole CNT14 penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. A region of the first semiconductor layer ACT1 connected to the intermediate connection line 155 may serve as a second initializing source region of the second initializing thin film transistor T7 of the first pixel circuit PC 1.

An opposite second end of the intermediate connection line 155 may be connected to the third semiconductor layer ACT3 of the third pixel circuit PC3 via a contact hole CNT15 penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. A region of the third semiconductor layer ACT3 connected to the intermediate connection line 155 may serve as an emission control drain region of the emission control thin film transistor T6 of the third pixel circuit PC 3.

The intermediate connection line 155, which is one of the second connection wirings 150, passes over the organic filler 161 arranged in the groove GR between the first pixel circuit PC1 and the third pixel circuit PC3, and connects the first pixel circuit PC1 spaced apart in the second direction and the third pixel circuit PC 3. The organic filler 161 may be disposed in the groove GR in the region of the inorganic material layer between the first pixel PX1 and the third pixel PX3, and may separate the first pixel circuit PC1 from the third pixel circuit PC3 in the region under the intermediate connection line 155, which prevents propagation of stress or cracks.

The etch stop layer ES is disposed on a portion of the sidewall and/or the bottom surface of the groove GR, and may prevent the barrier layer 101 from being damaged.

Fig. 5C is a cross-sectional view of the display apparatus taken along line III-III' of fig. 4 according to another exemplary embodiment.

Referring to fig. 5C, the display device according to an exemplary embodiment may further include an interlayer insulating layer 115 having an opening 115a in a region between the plurality of pixel circuits. The opening 115a includes an upper organic filler 163 disposed therein to fill the opening 115 a. The upper organic filler 163 may overlap the organic filler 161 in the thickness direction of the substrate 110. The upper organic filler 163 may be directly disposed on the organic filler 161. Accordingly, the second connection wiring 150 including the intermediate connection line 155 passes over the organic filler 161 and the upper organic filler 163 disposed between the first pixel circuit PC1 and the third pixel circuit PC3, and may connect the first pixel circuit PC1 spaced apart in the second direction with the third pixel circuit PC 3.

When the interlayer insulating layer 115 includes the openings 115a formed in the regions between the plurality of pixels PX, the stress applied to the interlayer insulating layer 115 may be prevented from being diffused. In addition, since the upper organic filler 163 is filled in the opening 115a, the upper organic filler 163 may absorb stress applied to the display device.

The upper organic filler 163 may include the same material as that of the organic filler 161. The upper organic filler 163 may include one or more materials from among acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinylsulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the inventive concept are not limited thereto.

Hereinafter, the function of the etch stop layer ES will be described with reference to fig. 6A to 6F. Fig. 6A to 6F are sectional views sequentially showing processes including forming the groove GR and forming the first connection wiring 140.

Referring to fig. 6A, an etch stop layer ES is first formed in each of the first pixel circuit PC1, the second pixel circuit PC2, and a region between the first pixel circuit PC1 and the second pixel circuit PC 2. In some exemplary embodiments, the etch stop layer ES and the semiconductor layer of the driving thin film transistor T1 may be disposed on the same layer and include the same material.

In some exemplary embodiments, the etch stop layer ES may include polysilicon or amorphous silicon. In other exemplary embodiments, the etch stop layer ES may include an oxide of at least one material from among indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). However, exemplary embodiments of the inventive concept are not limited thereto. A first gate insulating layer 112, a second gate insulating layer 113, and a third gate insulating layer 114 are sequentially stacked on the etch stop layer ES.

A Photoresist (PR) pattern is formed on the third gate insulating layer 114 to form a groove GR. The groove GR may be formed in a region corresponding to the etch stop layer ES.

Referring to fig. 6B, openings 114a, 113a, and 112a are formed in the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 by first etching, respectively, by using the PR pattern formed on the third gate insulating layer 114 as a mask. In this embodiment, the first etching may be dry etching using a fluoride-based gas. For example, the gas for the first etching may be carbon tetrafluoride (CF)₄) And H₂Combined gas of (1), trifluoromethane (CHF)₃) Hexafluoroethane (C)₂F₆) Octafluoropropane (C)₃F₈) Octafluorocyclobutane (C)₄F₈) Or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto.

Since the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 may have the same etching conditions.

In contrast, since the etch stop layer ES includes a material having an etching condition different from that of the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112, the etch stop layer ES may not be etched according to the first etching condition.

Referring to fig. 6C, the etch stop layer ES is then etched by a second etch to form an opening ESa. The second etching may be dry etching using a chloride (Cl) based gas or a combined gas of a chloride based gas and an oxygen based gas. However, exemplary embodiments of the inventive concept are not limited thereto. In this embodiment, only the etch stop layer ES may be removed in reaction to the second etching condition.

Referring to fig. 6D, the buffer layer 111 is then etched by a third etch and an opening 111a exposing the barrier layer 101 is formed to complete the groove GR. In this embodiment, the third etching may be dry etching using a fluoride (F) -based gas. For example, the gas for the third etching may be CF₄And H₂Combined gas of (1), CHF₃、C₂F₆、C₃F₈、C₄F₈Or a combination thereof. However, exemplary embodiments of the inventive concept are not limited thereto.

Since the thickness of the buffer layer 111 is much thinner than the sum of the thicknesses of the first, second, and third gate insulating layers 112, 113, and 114, the opening 111a of the buffer layer 111 may be easily formed while minimizing damage to the barrier layer 101 due to the third etching.

When the buffer layer 111 to the third gate insulating layer 114 are simultaneously etched without using the etch stop layer ES, the thickness of etching is large and the rate of over-etching is high. Therefore, there will be a strong risk of accidentally etching the barrier layer 101 when all layers are etched simultaneously. When the barrier layer 101 is etched and an opening is formed in the barrier layer 101, impurities or moisture may penetrate into the barrier layer 101 through the substrate 110 and cause deterioration of a semiconductor or the like.

However, exemplary embodiments of the inventive concept include the etch stop layer ES, which allows the depth of the groove GR to be precisely adjusted when forming the groove GR. Accordingly, the barrier layer 101 may be prevented from being damaged (e.g., etched) during the process of forming the groove GR.

As shown in fig. 6E, the groove GR is then filled by coating the organic filler 161 on the substrate 110. External shock applied to the display device may be absorbed by the organic filler 161. The organic filler 161 may include one or more materials from among acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, PET, PEN, polycarbonate, PI, PES, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the inventive concept are not limited thereto.

As shown in fig. 6F, a first connection wiring 140 is then formed on the organic filler 161 and the third gate insulating layer 114. The first connection wiring 140 may be connected to the conductive layer. For example, the first connection wiring 140 may be connected to the second electrode Cst2 of the storage capacitor Cst disposed under the third gate insulating layer 114 through contact holes CNT3a and CNT2b penetrating the third gate insulating layer 114.

Various modifications may be made to the contact holes CNT3a and CNT2b shown in fig. 6F. For example, the contact holes CNT3a and CNT2b may be formed simultaneously when forming the groove GR, or alternatively, the contact holes CNT3a and CNT2b may be formed before forming the groove GR or after forming the groove GR.

The display device according to an exemplary embodiment may be used to provide a flexible display device including an inorganic material layer having a groove GR and an organic filler 161 filling the groove GR in a region between a plurality of pixel circuits, and a wiring included in the pixel circuits, the pixel circuits being connected by a connection wiring disposed on the organic filler 161.

Further, when the groove GR is formed, using the etch stop layer ES allows the depth of the groove GR to be finely adjusted. Accordingly, damage to the barrier layer 101 can be minimized.

Fig. 7 is a sectional view of the display apparatus taken along lines I-I 'and II-II' of fig. 4 according to another exemplary embodiment. In fig. 7, since the same reference numerals as those of fig. 5A denote the same components, a description thereof will be omitted.

The display device according to the exemplary embodiment of fig. 7 includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., the first pixel circuit PC1 and the second pixel circuit PC2) and an organic filler 161 filling the groove GR. In this embodiment, the inorganic material layer includes insulating material layers (i.e., the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114) and an etch stop layer ES, which are respectively provided on a portion of the sidewalls or the bottom surface of the groove GR, having different etching conditions.

In the exemplary embodiment of fig. 7, the etch stop layer ES may form a bottom surface of the groove GR. In other words, the etch stop layer ES may be disposed in a region between the first and second pixel circuits PC1 and PC2, and the groove GR may be formed as an opening of the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The bottom surface of the groove GR may be located between the lowermost portion of the first gate insulating layer 112 and the uppermost portion of the first gate insulating layer 112.

In the exemplary embodiment shown in fig. 7, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 include an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES may include a material having an etch condition different from that of the insulating material. For example, in an exemplary embodiment, the etch stop layer ES may include a semiconductor layer.

In some example embodiments, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 may be etched by a fluoride-based gas, and the etch stop layer ES may be etched by a chloride-based gas.

As described above, the etch stop layer ES protects the barrier layer 101 thereunder from being etched, and the penetration of foreign substances through the substrate 110 may be minimized by the barrier layer 101.

The display device according to an exemplary embodiment may be used to provide a flexible display device including an organic filler 161 filling the groove GR and a wiring included in the pixel circuit connected by a connection wiring disposed on the organic filler 161.

Fig. 8 is a sectional view taken along lines I-I 'and II-II' of fig. 4 according to another exemplary embodiment. In fig. 8, the same reference numerals as those of fig. 5A denote the same components, and a description thereof will be omitted.

The display device according to the exemplary embodiment of fig. 8 includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., the first pixel circuit PC1 and the second pixel circuit PC2) and an organic filler 161 filling the groove GR. In this embodiment, the inorganic material layer includes insulating material layers (i.e., the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114) and an etch stop layer ES' each having different etching conditions. The etch stop layer ES' is disposed on a portion of the sidewalls or bottom surface of the groove GR.

Referring to fig. 8, the etch stop layer ES' and the gate electrodes G1 and G6 may be disposed on the same layer and include the same material. For example, the etch stop layer ES' may be disposed between the first gate insulating layer 112 and the second gate insulating layer 113. In addition, the etch stop layer ES' may include Mo, Cu, Ti, etc., and include a single layer or a plurality of layers.

The etch stop layer ES' may form a portion of the sidewall of the groove GR. For example, the etch stop layer ES' may form a portion of the sidewall of the groove GR (e.g., in the direction of the thickness of the substrate 110) higher than the bottom portion of the groove GR. The etch stop layer ES' may be understood as being arranged to surround the groove GR or the organic filler 161.

In the present exemplary embodiment, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 include an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES' may include a material having an etch condition different from that of the insulating material. However, exemplary embodiments of the inventive concept are not limited thereto.

In some example embodiments, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 may be etched by a fluoride-based gas, and the etch stop layer ES' may be etched by a chloride-based gas. However, exemplary embodiments of the inventive concept are not limited thereto.

As described above, damage to the barrier layer 101 under the etch stop layer ES 'may be minimized by the etch stop layer ES', and thus, penetration of foreign substances through the substrate 110 may be minimized.

The display device according to an exemplary embodiment may be used to provide a flexible display device including an organic filler 161 filling the groove GR and a wiring included in the pixel circuit connected by a connection wiring disposed on the organic filler 161.

Fig. 9 is a partial sectional view illustrating a display apparatus according to another exemplary embodiment. In fig. 9, since the same reference numerals as those of fig. 5A denote the same components, a description thereof will be omitted.

The display device according to the exemplary embodiment of fig. 9 includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., the first pixel circuit PC1 and the second pixel circuit PC2) and an organic filler 161 filling the groove GR. The inorganic material layer includes insulating material layers (i.e., the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114) and an etch stop layer ES ″ respectively having different etching conditions, the etch stop layer ES ″ being disposed on a portion of sidewalls or bottom surfaces of the groove GR.

In the present exemplary embodiment, the etch stop layer ES ″ may be disposed on the same layer as the second electrode Cst2 of the storage capacitor Cst, and include the same material as the second electrode Cst2 of the storage capacitor Cst. The etch stop layer ES ″ may be disposed between the second gate insulating layer 113 and the third gate insulating layer 114. In addition, the etch stop layer ES ″ may include Mo, Cu, Ti, etc., and may include a single layer or a plurality of layers.

The etch stop layer ES "may form a portion of the sidewalls of the groove GR. For example, the etch stop layer ES ″ may form a middle portion of the sidewall of the groove GR (e.g., a middle portion in a direction of the thickness of the substrate 110). The etch stop layer ES "may be understood as being arranged around the groove GR or the organic filler 161.

In the present exemplary embodiment, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 include an insulating material such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES ″ may include a material having an etch condition different from that of the insulating material. However, exemplary embodiments of the inventive concept are not limited thereto.

In some example embodiments, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 may be etched by a fluoride-based gas, and the etch stop layer ES ″ may be etched by a chloride-based gas.

As described above, damage to the barrier layer 101 under the etch stop layer ES ″ may be minimized by the etch stop layer ES ″, and thus, penetration of foreign substances through the substrate 110 may be minimized. However, exemplary embodiments of the inventive concept are not limited thereto.

The display device according to an exemplary embodiment may be used to provide a flexible display device including an organic filler 161 filling the groove GR and a wiring included in the pixel circuit connected by a connection wiring disposed on the organic filler 161.

Fig. 10 is a cross-sectional view illustrating a portion of a display apparatus according to another exemplary embodiment. In fig. 10, since the same reference numerals as those of fig. 5A denote the same components as those of fig. 5A, a description thereof will be omitted.

Referring to fig. 10, the display apparatus according to an exemplary embodiment includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., a first pixel circuit PC1 and a second pixel circuit PC2) and an organic filler 161 filling the groove GR.

In this embodiment, a recess GRh extending parallel to the upper surface of the substrate 110 may be provided on the side wall of the groove GR. In fig. 10, the recess GRh is disposed between the buffer layer 111 and the first gate insulating layer 112. However, exemplary embodiments of the inventive concept are not limited thereto. For example, the recess GRh may be disposed between the first gate insulation layer 112 and the second gate insulation layer 113. The recess GRh may also be disposed between the second gate insulation layer 113 and the third gate insulation layer 114.

After the depth of the groove GR is precisely controlled using the etch stop layer, the recess GRh may be formed by removing the etch stop layer. Since the etch stop layer may include a semiconductor material or a metal layer and may be etched by a chloride-based gas, the etch stop layer may be completely removed according to etching conditions. Accordingly, the recess GRh may be formed in the area where the etch stop layer has been removed.

The recess GRh may form part of the groove GR. Since the groove GR is filled with the organic filler 161, the recess GRh may also be filled with the organic filler 161.

The display device according to an exemplary embodiment may be used to provide a flexible display device including an organic filler 161 filling the groove GR and a wiring included in the pixel circuit connected by a connection wiring disposed on the organic filler 161.

As described above, since the display device according to the exemplary embodiment includes the inorganic material layer having the groove in the region between the plurality of pixels and the organic filler filling the groove, the display device may be robust and flexible in response to external shock.

In addition, since the groove includes the etch stop layer, the depth of the groove can be easily controlled.

The scope of the exemplary embodiments is not limited to the advantages mentioned above.

It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other exemplary embodiments. While one or more exemplary embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.