阅读说明：本技术 一种基于高k栅介质与低温欧姆接触工艺的SiC MOSFET的制备 (Preparation of SiC MOSFET (Metal-oxide-semiconductor field Effect transistor) based on high-k gate dielectric and low-temperature ohmic contact process ) 是由 程新红 刘少煜 郑理 俞跃辉 于 2020-06-17 设计创作，主要内容包括：本发明涉及一种基于高k栅介质与低温欧姆接触工艺的SiC MOSFET的制备方法,包括：将外延N型轻掺SiC层的SiC衬底清洗；在SiC衬底的外延层使用离子注入和退火的方式形成N+源区、P型沟道区和P+终端区；在外延层沉积高k栅介质层,然后沉积栅金属,并通过刻蚀图形化；在外延层沉积钝化层介质,并通过刻蚀图形化；在外延层和重掺衬底沉积低温欧姆接触金属层,退火形成欧姆接触；在外延层和重掺衬底加厚金属。该方法降低了栅界面处的碳簇密度,提高了沟道迁移率。(The invention relates to a preparation method of a SiC MOSFET (metal oxide semiconductor field effect transistor) based on a high-k gate dielectric and low-temperature ohmic contact process, which comprises the following steps of: cleaning the SiC substrate of the epitaxial N-type lightly doped SiC layer; forming an N + source region, a P-type channel region and a P + terminal region on an epitaxial layer of the SiC substrate in an ion implantation and annealing mode; depositing a high-k gate dielectric layer on the epitaxial layer, then depositing gate metal, and patterning by etching; depositing a passivation layer medium on the epitaxial layer, and patterning by etching; depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, and annealing to form ohmic contact; the metal is thickened on the epitaxial layer and the heavily doped substrate. The method reduces the density of carbon clusters at the gate interface and improves the channel mobility.)

1. A preparation method of a SiC MOSFET based on a high-k gate dielectric and low-temperature ohmic contact process comprises the following steps:

(1) cleaning the SiC substrate of the epitaxial N-type lightly doped SiC layer;

(2) forming an N + source region, a P-type channel region and a P + terminal region on an epitaxial layer of the SiC substrate in an ion implantation and annealing mode;

(3) depositing a high-k gate dielectric layer on the epitaxial layer;

(4) depositing gate metal on the surface of the high-k gate dielectric layer, and patterning the gate metal and the dielectric by etching;

(5) depositing a passivation layer medium on the epitaxial layer, and patterning by etching;

(6) depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, and annealing to form ohmic contact;

(7) the metal is thickened on the epitaxial layer and the heavily doped substrate.

2. The method as claimed in claim 1, wherein the thickness of the SiC substrate in step (1) is 200-400 μm, and the doping concentration is 1 × 10¹⁶-1×10²¹cm^-3The thickness of the epitaxial N-type lightly doped SiC layer is 5-30 μm, and the doping concentration is 1 × 10¹⁴-1×10¹⁷cm^-3。

3. The method according to claim 1, wherein the ions implanted in step (2) are N ions, P ions or Al ions; the annealing temperature is 1500-1900 ℃.

4. The method of claim 1, wherein in step (3), the high-k gate dielectric is Al₂O₃、SiO₂、Si₃N₄、HfO₂、AlN、La₂O₅Or AlON or a laminated structure thereof; the thickness of the high-k gate dielectric layer is 5-80 nm; deposition methods include MOCVD, PECVD, ALD, MBE, electron beam evaporation or radio frequency sputtering.

5. The method according to claim 1, wherein in the step (4), the gate metal is at least one of TiN, Ni and Al; the deposition method comprises electron beam evaporation or magnetron sputtering; the etching method comprises reactive ion etching or H₂SO₄And (5) wet etching.

6. The method of claim 1, wherein the passivation layer dielectric in step (5) is SiO₂Or Si₃N₄(ii) a Deposition methods include LPCVD or PECVD; the etching method comprises fluorine-based RIE etching, ICP etching or DHF wet etching.

7. The method of claim 1, wherein in step (6), a low temperature ohmic contact metal layer is deposited on the epitaxial layer and the heavily doped substrate, and the annealing step is performed to form an ohmic contact as follows: sequentially depositing a carbon layer with the thickness of 1-50nm and a nickel layer with the thickness of 10-500nm, and realizing ohmic contact through annealing, wherein the deposition method comprises chemical vapor deposition, magnetron sputtering or electron beam evaporation, and the annealing temperature is 700-950 ℃.

8. The method according to claim 1, wherein the thickened metal in the step (7) is any one of Ti, Al and Ni or a laminated metal thereof, and the thickness of the thickened metal is 1-10 μm.

9. A SiC MOSFET made by the method of claim 1.

10. Use of a SiC MOSFET made according to the method of claim 1.

Technical Field

The invention belongs to the field of semiconductor power devices, and particularly relates to a preparation method of a SiC MOSFET (metal oxide semiconductor field effect transistor) based on a high-k gate dielectric and low-temperature ohmic contact process.

Background

The silicon carbide material has larger forbidden band width, higher breakdown electric field, larger thermal conductivity and stable physical characteristics, and is an excellent manufacturing material for high-power, high-voltage and high-temperature power semiconductor devices. Because the silicon carbide has the functions of realizing N and P types by doping and generating SiO by natural oxidation₂Due to the characteristics of the silicon-based semiconductor, the preparation process has high compatibility and similarity with the traditional silicon power device process, and a mature process is developed on the basis.

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a widely used electronic device. The bipolar transistor is a majority carrier device, minority carrier injection is avoided when the bipolar transistor works, and therefore the bipolar transistor has higher response speed. Meanwhile, the silicon carbide power MOSFET can provide a very large safe working area, and a plurality of unit structures can be used in parallel, so that the high power density advantage is achieved.

However, the silicon carbide MOSFET prepared by the thermal oxidation process still has some problems: silicon oxide produced by thermal oxidation of silicon carbide may have carbon residues in the form of dangling bonds and carbon clusters at the interface, which may result in a higher interface state at the SiC/SiO2 interface, reduced device mobility, and poor electrical conductivity. Simultaneous SiO₂Has a relative dielectric constant of 3.9 and SiC of about 9.7, which results in a device operating with SiC/SiO₂SiO at the interface₂One side has a high electric field strength, which imposes a limit on the reliability of the device. For example: advanced processing for mobility improvement in 4H-SiCMOSFETs, A review, C.Maria et al, Mat.Sci.Semicon.Proc., 2018; improved channel mobility for 4H-SiC MOSFETs flowing high temperature polypeptides in nitride oxides, G.Y.Chung et al, IEEE Electron Device letters, 2001; silicon carbide, A unique platform for metal-oxide-semiconductor graphics, G.Liu et al, Applied graphics Reviews,2015。

disclosure of Invention

The invention aims to solve the technical problem of providing a preparation method of a SiC MOSFET based on a high-k gate dielectric and low-temperature ohmic contact process so as to overcome the defect of low mobility of the traditional SiC MOSFET.

The invention provides a preparation method of a SiC MOSFET (metal oxide semiconductor field effect transistor) based on a high-k gate dielectric and low-temperature ohmic contact process, which comprises the following steps of:

(1) cleaning the SiC substrate of the epitaxial N-type lightly doped SiC layer;

(2) forming an N + source region, a P-type channel region and a P + terminal region on an epitaxial layer of the SiC substrate in an ion implantation and annealing mode;

(3) depositing a high-k gate dielectric layer on the epitaxial layer;

(4) depositing gate metal on the surface of the high-k gate dielectric layer, and patterning the gate metal and the dielectric by etching;

(5) depositing a passivation layer medium on the epitaxial layer, and patterning by etching;

(6) depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, and annealing to form ohmic contact;

(7) the metal is thickened on the epitaxial layer and the heavily doped substrate.

The thickness of the SiC substrate in the step (1) is 200-400 μm, and the doping concentration is 1 × 10¹⁶-1×10²¹cm^-3。

The thickness of the epitaxial N-type lightly doped SiC layer in the step (1) is 5-30 mu m, and the doping concentration is 1 × 10¹⁴-1×10¹⁷cm^-3。

The cleaning process in the step (1) comprises the following steps: standard RCA cleaning; and carrying out high-temperature oxidation on the silicon carbide epitaxial wafer to form a sacrificial oxide layer, and then corroding the sacrificial oxide layer until the surface oxide layer is completely removed.

The ions injected by the ions in the step (2) are N ions, P ions or Al ions. Ion implantation 10¹⁵-10¹⁸cm^-3P-type ion of doping concentration, ion implantation 10¹⁵-10¹⁹cm^-3Doping concentration of N-type ions.

The above-mentionedIn the step (3), the high-k gate dielectric is Al₂O₃、SiO₂、Si₃N₄、HfO₂、AlN、La₂O₅Or AlON or a laminated structure thereof; the thickness of the high-k gate dielectric layer is 5-80 nm.

The deposition method in the step (3) comprises MOCVD, PECVD, ALD, MBE, electron beam evaporation or radio frequency sputtering.

The etching method in the steps (3) and (5) comprises fluorine-based RIE etching, ICP etching or DHF wet etching.

And (4) in the step (4), the gate metal is at least one of TiN, Ni and Al.

The deposition method in the step (4) comprises electron beam evaporation or magnetron sputtering; the etching method comprises reactive ion etching or H₂SO₄And (5) wet etching.

The passivation layer medium in the step (5) is SiO₂Or Si₃N₄(ii) a Deposition methods include LPCVD or PECVD.

The thickness of the passivation layer in the step (5) is 100-2000 nm.

And (3) depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate in the step (6), and annealing to form ohmic contact: sequentially depositing a carbon layer with the thickness of 1-50nm and a nickel layer with the thickness of 10-500nm, and realizing ohmic contact through annealing, wherein the deposition method comprises chemical vapor deposition, magnetron sputtering or electron beam evaporation, and the annealing temperature is 700-950 ℃.

In the step (7), the thickened metal is any one of Ti, Al and Ni or laminated metal thereof, and the thickness of the thickened metal is 1-10 mu m.

The invention also provides the SiC MOSFET prepared by the method.

The invention also provides an application of the SiC MOSFET prepared by the method.

The invention relates to a manufacturing method of a high-k gate dielectric layer, which is characterized in that a physical or chemical vapor deposition method is used for depositing the high-k gate dielectric layer on the surface of a cleaned clean silicon carbide epitaxial wafer. These growings are low temperature film growth (150-Impurity content in the layer while reducing the SiC/SiO₂The interface state is caused by carbon cluster and impurity. With Al₂O₃For example, the k value is 9-10, the forbidden bandwidth is 8.7-8.8eV, and due to the high k value and forbidden bandwidth, the device can bear lower electric field intensity in application, so that the early breakdown of the gate dielectric is avoided. The invention relates to a method for manufacturing low-temperature ohmic contact, which can realize ohmic contact by depositing a carbon/nickel laminated structure on a heavily doped silicon carbide surface and carrying out multiple annealing. In the traditional silicon carbide ohmic contact manufacturing process, high-temperature rapid annealing (1000 ℃) needs to be carried out on the SiC/Ni structure, and the high temperature can cause crystallization of a high-k gate dielectric, so that the problems of large leakage current and the like are caused. According to the invention, carbon is introduced into the nickel-based ohmic contact, so that the Schottky barrier height between metal semiconductors is reduced, and the ohmic contact is prepared under the relatively low-temperature annealing condition.

Advantageous effects

Compared with the traditional SiC power MOSFET, the silicon carbide MOSFET prepared on the basis of the high-k gate dielectric and the low-temperature ohmic contact process has the advantages that the high-k dielectric is used as the gate dielectric, the carbon cluster density at the interface is reduced, and the channel mobility is improved. Experimental data shows that the interface state density of the Al-based high-k gate dielectric grown by ALD deposition can reach 10¹¹-10¹²cm^-2eV^-1Lower than SiO produced by thermal oxidation₂Interface state density of (4 × 10)¹²-10¹³cm^-2eV^-1). The mobility can also be from 25-30cm²the/Vs is increased to 30-50cm²/Vs。

Meanwhile, when the device works in a reverse voltage-resistant area, the high-k dielectric has high dielectric constant, so that the electric field concentration effect in the gate dielectric is avoided, and the early breakdown of the gate dielectric is prevented. In general, Al-based high-k dielectrics are contrasted with thermally oxidized SiO₂Its dielectric constant will increase from 3.9 to 7-10. According to Gauss's law, SiO when SiC reaches the critical breakdown field (3MV/cm)₂The electric field strength in medium is 8.3MV/cm, while the electric field strength in high-k dielectrics is only 3-4MV/cm, which is obviously more difficult to use as gate dielectricsThereby, the characteristic of high critical breakdown electric field of SiC can be fully utilized.

Drawings

FIG. 1 is a schematic cross-sectional view of an epitaxial layer of an SiC substrate of the present invention after forming an N + source region and a P-type channel region.

FIG. 2 is a schematic cross-sectional structure of a device after deposition of a high-k gate dielectric layer in accordance with the present invention.

FIG. 3 is a schematic cross-sectional view of the device after deposition and etching of a gate metal layer according to the present invention.

Fig. 4 is a schematic cross-sectional structure of a device after the deposition of a passivation layer according to the present invention.

Fig. 5 is a schematic diagram of a cell of a SiC high-k gate dielectric MOSFET device of the present invention.

Detailed Description

The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.

The invention will be described in the context of an embodiment of a high-k gate dielectric silicon carbide Metal Oxide Semiconductor Field Effect Transistor (MOSFET). However, embodiments of the present invention may also be applied to various types of metal oxide semiconductor field effect transistors.

Silicon carbide substrate source: dongguan Tian semiconductor technology Co., Ltd. All the medicines are not subjected to secondary purification and are directly used in the synthesis process and the preparation process of devices.