阅读说明：本技术 Njfet器件及制备方法 (NJFET device and preparation method ) 是由 张忆 苏贵东 汪强 刘文军 陈竹江 刘欢 于 2020-04-30 设计创作，主要内容包括：NJFET器件及制备方法,涉及半导体技术,本发明的NJFET器件包括P衬底、隔离介质、N外延区、P型埋层、深磷注入区、源区、漏区、沟道区、栅区、二氧化硅氧化层,其特征在于,还包括P阱,所述P型埋层、深磷注入区、源区、漏区、沟道区和栅区嵌入P阱。本发明可以使现有P衬底N外延SOI互补双极工艺支持NJFET器件,使得该工艺可以同时包含PJFET和NJFET器件两种互补的JFET器件。(The invention discloses an NJFET device and a preparation method thereof, and relates to the semiconductor technology. The invention can make the prior P substrate N epitaxial SOI complementary bipolar process support the NJFET device, so that the process can simultaneously comprise two complementary JFET devices of a PJFET device and an NJFET device.)

The NJFET device comprises a P substrate, an isolation medium, an N epitaxial region, a P-type buried layer, a deep phosphorus injection region, a source region, a drain region, a channel region, a gate region and a silicon dioxide oxide layer, and is characterized by further comprising a P well, wherein the P-type buried layer, the deep phosphorus injection region, the source region, the drain region, the channel region and the gate region are embedded into the P well.

2. The method of making an NJFET device of claim 1, comprising the steps of:

1) filling a bottom layer isolation medium on a wafer of a P-type substrate;

2) generating an N-type epitaxial region in an epitaxial growth mode;

3) generating a doped semiconductor buried layer;

4) generating a silicon dioxide oxide layer;

5) generating a source electrode and a drain electrode of the NJFET in an N-type injection mode;

6) generating a grid electrode of the NJFET in a P-type injection mode;

7) forming a channel region by a doping injection mode;

8) generating a back gate of the NJFET in a deep phosphorus injection mode;

9) generating a side wall isolation medium by a filling mode;

characterized in that the step 3) is as follows: and in the N-type epitaxial region, generating a P well in a P-type injection mode, and generating a doped semiconductor buried layer in the P well, wherein the doped semiconductor buried layer is a P-type buried layer.

Technical Field

The present invention relates to semiconductor technology.

Background

Under the existing SOI bipolar process condition, the NJFET device is prepared by an N substrate P epitaxial process, the PJFET device is prepared by a P substrate N epitaxial SOI complementary bipolar process, two types of devices need two different process environments, and the cost is high.

Disclosure of Invention

The invention aims to solve the technical problem of providing a technology for developing an NJFET device on the basis of an SOI (silicon on insulator) complementary bipolar process of P substrate N epitaxy.

The technical scheme adopted by the invention for solving the technical problems is that the NJFET device comprises a P substrate, an isolation medium, an N epitaxial region, a P-type buried layer, a deep phosphorus injection region, a source region, a drain region, a channel region, a gate region and a silicon dioxide oxide layer, and is characterized by further comprising a P well, wherein the P-type buried layer, the deep phosphorus injection region, the source region, the drain region, the channel region and the gate region are embedded into the P well.

The invention also provides a preparation method of the NJFET device, which comprises the following steps:

1) filling an underlayer isolation medium on the wafer of the P-type substrate,

2) an N-type epitaxial region is generated by means of epitaxial growth,

3) generating a doped semiconductor buried layer, and forming a doped semiconductor buried layer,

4) a silicon dioxide oxide layer is generated,

5) the source and drain of the PJFET are generated by means of P-type injection,

6) the gate of the PJFET is generated by means of N-type implantation,

7) the channel region is formed by means of a dopant implantation,

8) the back gate of the PJFET is generated by a deep phosphorus injection mode,

9) the sidewall spacer dielectric is created by means of filling,

characterized in that the step 3) is as follows: and in the N-type epitaxial region, generating a P well in a P-type injection mode, and generating a doped semiconductor buried layer in the P well, wherein the doped semiconductor buried layer is a P-type buried layer.

The invention overcomes the defects of the prior art, and develops the NJFET device on the prior P substrate N epitaxial SOI complementary bipolar process, so that the process is more flexible to apply, and can meet the more special requirements of integrated circuit design. The invention can make the prior P substrate N epitaxial SOI complementary bipolar process support the NJFET device, so that the process can simultaneously comprise two complementary JFET devices of a PJFET device and an NJFET device, can be flexibly processed and applied in circuit design, and can complete the complex design which can not be completed by a single JFET device.

Drawings

Fig. 1 is a schematic diagram of a prior art device structure.

Fig. 2 is a schematic diagram of the device structure of the present invention. The shaded area in fig. 2 is the P-well.

Description of reference numerals:

BN N type buried layer, BP: p-type buried layer, DC: deep phosphorus implant region, TR: partition wall, OX: silicon dioxide oxide layer, IN: lightly doped N-type implanted region, IP: lightly doped P-type implanted region, IV: channel region, NC: and an N-type injection region.

Detailed Description

See fig. 1, 2. The invention adds an etching procedure and an injection (or diffusion) procedure on the basis of a PJFET (P-junction field effect transistor) procedure of an SOI (silicon on insulator) complementary bipolar process of a P substrate N epitaxy, generates a P well (a shaded area in figure 2) on the N epitaxy, and manufactures a main structure of an NJFET (N-junction field effect transistor) device in the P well; injecting N-type light doping into the P well to form an NJFET channel; on the basis, P lightly doped shallow junction injection is carried out again to form a grid upper electrode plate of the NJFET; the junction depth of the N-type light doping is larger than that of the P-type light doping by controlling the ion implantation energy or increasing the high-temperature annealing time of the N-type light doping; the threshold voltage of the NJFET is adjusted by controlling the junction depth difference of the N-type light doping and the P-type light doping and the concentration of the N-type light doping.

The NJFET device comprises a P substrate, an isolation medium, an N epitaxial region, a P-type buried layer, a deep phosphorus injection region, a source region, a drain region, a channel region, a grid region, a silicon dioxide oxide layer and a P well, wherein the P-type buried layer, the deep phosphorus injection region, the source region, the drain region, the channel region and the grid region are embedded into the P well.

The preparation method of the NJFET device comprises the following steps:

1) filling an underlayer isolation medium on the wafer of the P-type substrate,

2) an N-type epitaxial region is generated by means of epitaxial growth,

3) in the N-type epitaxial region, a P-well (shaded region in the figure) is generated by means of P-type implantation, and a doped semiconductor buried layer is generated in the P-well, wherein the doped semiconductor buried layer is a P-type buried layer (BP in the figure),

4) a silicon dioxide oxide layer OX is generated,

5) the source and drain of the PJFET are created in the P-well by means of N-type injection (NC in the figure),

6) the gate (IP in the figure) of the PJFET is created by means of P-type injection,

7) the channel region (IV in the figure) is formed by means of a doping implantation,

8) the back gate (DC in the figure) of the PJFET is generated by means of deep phosphorus implantation,

9) the sidewall isolation dielectric is generated by means of filling.

The invention develops the NJFET device on the basis of the traditional P substrate N epitaxial SOI complementary bipolar process, and is compatible with the existence of two complementary JFET devices, namely a PJFET and an NJFET, so that the circuit design is more flexible; the threshold voltage of the NJFET device is more accurate and controllable, the NJFET device is more widely applied, and the NJFET device can be used as circuit structures such as a differential pair input stage, a mirror current source or level shift in circuit design.

The present invention is an improvement on the existing process, and the description has fully described the necessary technical content for implementation, so details such as specific process parameters and the like are not repeated.