阅读说明：本技术 一种基于三输入tfet器件的一位全加器 (One-bit full adder based on three-input TFET device ) 是由 胡建平 高晗晔 叶浩 张子豪 于 2020-05-08 设计创作，主要内容包括：本发明公开了一种基于三输入TFET器件的一位全加器,包括第十四个TFET管,七个TFET管采用P型三输入TFET器件实现,七个TFET管采用N型三输入TFET器件实现,N型三输入TFET器件三个栅极中任意两个或三个接入的输入信号均为1时,N型三输入TFET器件的源极和漏极之间导通,P型三输入TFET器件三个栅极中任意两个接入或者三个接入的输入信号为0时,P型三输入TFET器件的源极和漏极之间导通；优点是电路结构较为简单,电路面积和功耗较小,速度较快。(The invention discloses a one-bit full adder based on a three-input TFET device, which comprises a fourteenth TFET tube, wherein seven TFET tubes are realized by adopting a P-type three-input TFET device, seven TFET tubes are realized by adopting an N-type three-input TFET device, when any two or three input signals of three grids of the N-type three-input TFET device are all 1, a source electrode and a drain electrode of the N-type three-input TFET device are conducted, and when any two or three input signals of three grids of the P-type three-input TFET device are 0, a source electrode and a drain electrode of the P-type three-input TFET device are conducted; the advantages are simple circuit structure, small circuit area and power consumption, and high speed.)

1. A one-bit full adder based on a three-input TFET device, comprising a first TFET transistor, a second TFET transistor, a third TFET transistor, a fourth TFET transistor, a fifth TFET transistor, a sixth TFET transistor, a seventh TFET transistor, an eighth TFET transistor, a ninth TFET transistor, a tenth TFET transistor, an eleventh TFET transistor, a twelfth TFET transistor, a thirteenth TFET transistor, and a fourteenth TFET transistor, wherein the first TFET transistor, the third TFET transistor, the fifth TFET transistor, the seventh TFET transistor, the ninth TFET transistor, the eleventh TFET transistor, and the thirteenth TFET transistor are implemented by using P-type three-input TFET devices, the second TFET transistor, the fourth TFET transistor, the sixth TFET transistor, the eighth TFET transistor, the tenth TFET transistor, the twelfth TFET, and the fourteenth TFET transistors are implemented by using P-type three-input TFET devices, and the gate TFET transistors of the first TFET transistor, the second TFET transistor, the third TFET transistor, the twelfth transistor, the fourteenth transistor, the gate TFET, the thirteenth gate TFET, the fourteenth, and the TFET transistors are implemented by using P-type three-input TFET devices, and the gate TFET, The N-type three-input TFET device comprises a first grid, a second grid, a third grid, a source and a drain, wherein when any two accessed input signals of the first grid, the second grid and the third grid of the N-type three-input TFET device are 1, and the other accessed input signals are 0, or the three accessed input signals are 1, the source and the drain of the N-type three-input TFET device are conducted, the P-type three-input TFET device comprises a first grid, a second grid, a third grid, a source and a drain, and when any two accessed input signals of the first grid, the second grid and the third grid of the P-type three-input TFET device are 0, and the other accessed input signals are 1, or the three accessed input signals are 0, the source and the drain of the P-type three-input TFET device are conducted;

the source electrode of the first TFET tube, the source electrode of the third TFET tube, the source electrode of the fifth TFET tube, the source electrode of the seventh TFET tube, the source electrode of the ninth TFET tube, the source electrode of the eleventh TFET tube, and the source electrode of the thirteenth TFET tube are all connected to a power supply, the source electrode of the second TFET tube, the source electrode of the fourth TFET tube, the source electrode of the sixth TFET tube, the source electrode of the eighth TFET tube, the source electrode of the tenth TFET tube, the source electrode of the twelfth TFET tube, and the source electrode of the fourteenth TFET tube are all connected to a ground, the first gate electrode of the first TFET tube, the first gate electrode of the second TFET tube, the first gate electrode of the fifth TFET tube, the second gate electrode of the fifth TFET tube, the third gate electrode of the fifth TFET tube, the first gate electrode of the sixth TFET tube, the third gate electrode of the sixth TFET tube, and the third TFET tube are all connected to a power supply, The first gate of the eleventh TFET transistor and the second gate of the twelfth TFET transistor are connected and the connection terminal thereof is the first input terminal of the one-bit full adder, the first input terminal of the one-bit full adder is used for receiving a first input signal, the second gate of the first TFET transistor, the second gate of the second TFET transistor, the first gate of the seventh TFET transistor, the second gate of the eighth TFET transistor, the first gate of the ninth TFET transistor, the second gate of the ninth TFET transistor, the third gate of the ninth TFET transistor, the first gate of the tenth TFET transistor, the second gate of the tenth TFET transistor and the third gate of the tenth TFET transistor are connected and the connection terminal thereof is the second input terminal of the one-bit full adder, the second input terminal of the one-bit full adder is used for receiving a second input signal, and the connection terminal thereof is the first input terminal of the one-bit full adder, the gate of the third TFET transistor and the third TFET transistor are connected and the connection terminal thereof is the first input terminal of the one-bit full adder, the one-bit full adder is used for receiving a second input signal, and the second input signal, the third gate of the second TFET transistor, the second gate of the seventh TFET transistor, the third gate of the eighth TFET transistor, the second gate of the eleventh TFET transistor, the third gate of the twelfth TFET transistor, the second gate of the thirteenth TFET transistor, and the second gate of the fourteenth TFET transistor are connected and their connection terminals are the carry input terminal of the one-bit full adder, the carry input terminal of the one-bit full adder is used for receiving a carry signal of a low bit output, the drain of the first TFET transistor, the drain of the second TFET transistor, the first gate of the third TFET transistor, the second gate of the third TFET transistor, the third gate of the third TFET transistor, the first gate of the fourth TFET transistor, the second gate of the fourth TFET transistor, and the third gate of the fourth TFET transistor are connected, the drain of the third TFET transistor and the drain of the fourth TFET transistor are connected and their connection terminals are the drain of the one-bit full adder A terminal, configured to output a carry signal to a high bit, where a drain of the fifth TFET transistor, a drain of the sixth TFET transistor, a third gate of the seventh TFET transistor and a first gate of the eighth TFET transistor are connected, a drain of the seventh TFET transistor, a drain of the eighth TFET transistor, a first gate of the thirteenth TFET transistor and a third gate of the fourteenth TFET transistor are connected, a drain of the ninth TFET transistor, a drain of the tenth TFET transistor, a third gate of the eleventh TFET transistor and a first gate of the twelfth TFET transistor are connected, a drain of the eleventh TFET transistor, a drain of the twelfth TFET transistor, a third gate of the thirteenth TFET transistor and a first gate of the fourteenth TFET transistor are connected, a drain of the thirteenth TFET transistor and a drain of the fourteenth TFET transistor are connected, and a connection terminal of the one bit adder and an output terminal of the one bit adder is connected to the terminal, and the sum output end of the one-bit full adder is used for outputting a sum signal.

Technical Field

The present invention relates to a one-bit full adder, and more particularly, to a one-bit full adder based on a three-input TFET device.

Background

With the rapid development of integrated circuit technology, the conventional CMOS process has been unable to meet the ever-increasing demands in terms of miniaturization, low power consumption, and the like of the current digital circuit. In recent years, new nano-devices have emerged that can replace CMOS devices. Among them, TFET (tunneling field effect transistor) devices are different from the current injection mechanism of conventional CMOS devices, and exhibit good subthreshold swing, and some logic circuits implemented based on TFET devices also exhibit some characteristics superior to CMOS circuits. TFET devices are the most promising devices for integrated circuit design applications instead of CMOS devices.

The full adder is used as a basic unit of an electronic system, can complete addition and participate in subtraction, multiplication, division and other operations, and is widely applied to large-scale integrated circuit design. The full adder is an important unit of a digital signal processor, a microprocessor and a single chip microcomputer system with higher performance requirements, and the influence of the quality of the performance of the full adder on the performance of the whole system is particularly important. One-bit full adders widely used in carry critical paths of multi-bit adders are one of the important factors affecting the performance of multi-bit adders.

A conventional circuit of a one-bit full adder based on CMOS devices is shown in fig. 1. The one-bit full adder is composed of 22P-type CMOS transistors and 22N-type CMOS transistors. The one-bit full adder calculates output through a logic equation, a static complementary gate-level circuit structure is adopted, three logic blocks are needed for generation of a carry signal and a summation signal, and six-level delay is generated. More P-type CMOS transistors are stacked between the two output signals, and the load capacitance of the carry signal is larger. The above situation makes the one-bit full adder use more CMOS transistors, the circuit structure is more complex, the circuit area and power consumption are larger, and the speed is slower.

Disclosure of Invention

The invention aims to solve the technical problem of providing a one-bit full adder based on a three-input TFET device, which has the advantages of simple circuit structure, small circuit area and power consumption and high speed.

The technical scheme adopted by the invention for solving the technical problems is as follows: a one-bit full adder based on a three-input TFET device comprises a first TFET tube, a second TFET tube, a third TFET tube, a fourth TFET tube, a fifth TFET tube, a sixth TFET tube, a seventh TFET tube, an eighth TFET tube, a ninth TFET tube, a tenth TFET tube, an eleventh TFET tube, a twelfth TFET tube, a thirteenth TFET tube and a fourteenth TFET tube, wherein the first TFET tube, the third TFET tube, the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the thirteenth TFET tube are respectively realized by a P-type three-input TFET device, the second TFET tube, the fourth TFET tube, the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the fourteenth TFET tube are respectively realized by a third TFET tube, a gate device, a gate, The third gate, the source and the drain of the N-type three-input TFET device are connected when any two of the first gate, the second gate and the third gate of the N-type three-input TFET device are connected with an input signal 1 and the other one of the first gate, the second gate and the third gate of the N-type three-input TFET device is connected with an input signal 0 or the three connected input signals are all 1, the P-type three-input TFET device is provided with a first gate, a second gate, a third gate, a source and a drain, and the source and the drain of the P-type three-input TFET device are connected when any two of the first gate, the second gate and the third gate of the P-type three-input TFET device are connected with an input signal 0 and the other one of the first gate, the second gate and the third gate of the P-type three-input TFET device is connected with an input signal 1 or the three connected input; the source electrode of the first TFET tube, the source electrode of the third TFET tube, the source electrode of the fifth TFET tube, the source electrode of the seventh TFET tube, the source electrode of the ninth TFET tube, the source electrode of the eleventh TFET tube, and the source electrode of the thirteenth TFET tube are all connected to a power supply, the source electrode of the second TFET tube, the source electrode of the fourth TFET tube, the source electrode of the sixth TFET tube, the source electrode of the eighth TFET tube, the source electrode of the tenth TFET tube, the source electrode of the twelfth TFET tube, and the source electrode of the fourteenth TFET tube are all connected to a ground, the first gate electrode of the first TFET tube, the first gate electrode of the second TFET tube, the first gate electrode of the fifth TFET tube, the second gate electrode of the fifth TFET tube, the third gate electrode of the fifth TFET tube, the first gate electrode of the sixth TFET tube, the third gate electrode of the sixth TFET tube, and the third TFET tube are all connected to a power supply, The first gate of the eleventh TFET transistor and the second gate of the twelfth TFET transistor are connected and the connection terminal thereof is the first input terminal of the one-bit full adder, the first input terminal of the one-bit full adder is used for receiving a first input signal, the second gate of the first TFET transistor, the second gate of the second TFET transistor, the first gate of the seventh TFET transistor, the second gate of the eighth TFET transistor, the first gate of the ninth TFET transistor, the second gate of the ninth TFET transistor, the third gate of the ninth TFET transistor, the first gate of the tenth TFET transistor, the second gate of the tenth TFET transistor and the third gate of the tenth TFET transistor are connected and the connection terminal thereof is the second input terminal of the one-bit full adder, the second input terminal of the one-bit full adder is used for receiving a second input signal, and the connection terminal thereof is the first input terminal of the one-bit full adder, the gate of the third TFET transistor and the third TFET transistor are connected and the connection terminal thereof is the first input terminal of the one-bit full adder, the one-bit full adder is used for receiving a second input signal, and the second input signal, the third gate of the second TFET transistor, the second gate of the seventh TFET transistor, the third gate of the eighth TFET transistor, the second gate of the eleventh TFET transistor, the third gate of the twelfth TFET transistor, the second gate of the thirteenth TFET transistor, and the second gate of the fourteenth TFET transistor are connected and their connection terminals are the carry input terminal of the one-bit full adder, the carry input terminal of the one-bit full adder is used for receiving a carry signal of a low bit output, the drain of the first TFET transistor, the drain of the second TFET transistor, the first gate of the third TFET transistor, the second gate of the third TFET transistor, the third gate of the third TFET transistor, the first gate of the fourth TFET transistor, the second gate of the fourth TFET transistor, and the third gate of the fourth TFET transistor are connected, the drain of the third TFET transistor and the drain of the fourth TFET transistor are connected and their connection terminals are the drain of the one-bit full adder A terminal, configured to output a carry signal to a high bit, where a drain of the fifth TFET transistor, a drain of the sixth TFET transistor, a third gate of the seventh TFET transistor and a first gate of the eighth TFET transistor are connected, a drain of the seventh TFET transistor, a drain of the eighth TFET transistor, a first gate of the thirteenth TFET transistor and a third gate of the fourteenth TFET transistor are connected, a drain of the ninth TFET transistor, a drain of the tenth TFET transistor, a third gate of the eleventh TFET transistor and a first gate of the twelfth TFET transistor are connected, a drain of the eleventh TFET transistor, a drain of the twelfth TFET transistor, a third gate of the thirteenth TFET transistor and a first gate of the fourteenth TFET transistor are connected, a drain of the thirteenth TFET transistor and a drain of the fourteenth TFET transistor are connected, and a connection terminal of the one bit adder and an output terminal of the one bit adder is connected to the terminal, and the sum output end of the one-bit full adder is used for outputting a sum signal.

Compared with the prior art, the invention has the advantages that a one-bit full adder is constructed by the first TFET tube, the second TFET tube, the third TFET tube, the fourth TFET tube, the fifth TFET tube, the sixth TFET tube, the seventh TFET tube, the eighth TFET tube, the ninth TFET tube, the tenth TFET tube, the eleventh TFET tube, the twelfth TFET tube, the thirteenth TFET tube and the fourteenth TFET tube, the first TFET tube, the third TFET tube, the fifth TFET tube, the seventh TFET tube, the ninth TFET tube, the eleventh TFET tube and the thirteenth TFET tube are respectively realized by adopting a P-type three-input TFET device, the second TFET tube, the fourth TFET tube, the sixth TFET tube, the eighth TFET tube, the tenth TFET tube, the twelfth TFET tube and the fourteenth TFET tube are respectively realized by adopting an N-type three-input TFET device, the N-type three-input device has a first grid electrode, a second grid electrode, a third electrode, a source electrode and a third electrode, a drain electrode, a third electrode, a grid electrode, a drain electrode, a third electrode, when the other accessed input signal is 0 or all three accessed input signals are 1, the source electrode and the drain electrode of the N-type three-input TFET device are conducted, the P-type three-input TFET device is provided with a first grid electrode, a second grid electrode, a third grid electrode, a source electrode and a drain electrode, and when any two accessed input signals of the first grid electrode, the second grid electrode and the third grid electrode of the P-type three-input TFET device are 0 and the other one accessed input signal is 1 or all three accessed input signals are 0, the source electrode and the drain electrode of the P-type three-input TFET device are conducted; when a first input signal A accessed by a first input end of a one-bit full adder, a second input signal B accessed by a second input end and a carry signal C accessed by a carry input end are all '1', for a carry output end of the one-bit full adder, at the moment, because a second TFET tube and a third TFET tube are conducted, a level signal of the carry output end of the one-bit full adder is pulled high, the carry output end of the one-bit full adder outputs a high level 1, and for a sum output end of the one-bit full adder, because a sixth TFET tube, an eighth TFET tube, a tenth TFET tube, a twelfth TFET tube and a thirteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled high, and the sum output end of the one-bit full adder outputs a high level 1; when a first input signal A accessed by a first input end of a one-bit full adder, a second input signal B accessed by a second input end and a carry signal C accessed by a carry input end are all '0', for a carry output end of the one-bit full adder, because a first TFET tube and a fourth TFET tube are conducted at the moment, a level signal of the carry output end of the one-bit full adder is pulled down, the carry output end of the one-bit full adder outputs a low level 0, and for a sum output end of the one-bit full adder, because a fifth TFET tube, a seventh TFET tube, a ninth TFET tube, an eleventh TFET tube and a fourteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled down, and the sum output end of the one-bit full adder outputs a low level 0; when a first input signal A accessed by a first input end of a one-bit full adder is '0', a second input signal B accessed by a second input end and a carry signal C accessed by a carry input end are both '1', for a carry output end of the one-bit full adder, because a second TFET tube and a third TFET tube are conducted at the moment, a level signal of the carry output end of the one-bit full adder is pulled high, the carry output end of the one-bit full adder outputs a high level 1, and for a sum output end of the one-bit full adder, because a fifth TFET tube, an eighth TFET tube, a tenth TFET tube, an eleventh TFET tube and a fourteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled low, and the sum output end of the one-bit full adder outputs a low level 0; when a second input signal B accessed by a second input end of the one-bit full adder is '0', a first input signal A accessed by a first input end and a carry signal C accessed by a carry input end are both '1', for a carry output end of the one-bit full adder, because a second TFET tube and a third TFET tube are conducted at the moment, a level signal of the carry output end of the one-bit full adder is pulled high, the carry output end of the one-bit full adder outputs a high level 1, and for a sum output end of the one-bit full adder, because a sixth TFET tube, a seventh TFET tube, a ninth TFET tube, a twelfth TFET tube and a fourteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled low, and the sum output end of the one-bit full adder outputs a low level 0; when the carry signal C accessed by the carry input end of the one-bit full adder is '0', the first input signal A accessed by the first input end and the second input signal B accessed by the second input end are both '1', for the carry output end of the one-bit full adder, the level signal of the carry output end of the one-bit full adder is pulled high due to the conduction of the second TFET tube and the third TFET tube, the carry output end of the one-bit full adder outputs a high level 1, and for the sum output end of the one-bit full adder, the level signal of the sum output end of the one-bit full adder is pulled low due to the conduction of the sixth TFET tube, the seventh TFET tube, the tenth TFET tube, the eleventh TFET tube and the fourteenth TFET tube, and the sum output end of the one-bit full adder outputs a low level 0; when a first input signal A accessed by a first input end of a one-bit full adder is '1', a second input signal B accessed by a second input end and a carry signal C accessed by a carry input end are both '0', for a carry output end of the one-bit full adder, because a first TFET tube and a fourth TFET tube are conducted at the moment, a level signal of the carry output end of the one-bit full adder is pulled down, the carry output end of the one-bit full adder outputs low level 0, and for a sum output end of the one-bit full adder, because a sixth TFET tube, a seventh TFET tube, a ninth TFET tube, a twelfth TFET tube and a thirteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled up, and the sum output end of the one-bit full adder outputs high level 0; when a second input signal B accessed by a second input end of the one-bit full adder is '1', a first input signal A accessed by a first input end and a carry signal C accessed by a carry input end are both '0', for a carry output end of the one-bit full adder, because a first TFET tube and a fourth TFET tube are conducted at the moment, a level signal of the carry output end of the one-bit full adder is pulled down, the carry output end of the one-bit full adder outputs low level 0, and for a sum output end of the one-bit full adder, because a fifth TFET tube, an eighth TFET tube, a tenth TFET tube, an eleventh TFET tube and a thirteenth TFET tube are conducted at the moment, a level signal of the sum output end of the one-bit full adder is pulled up, and the sum output end of the one-bit full adder outputs high level 0; when the carry signal C accessed by the carry input end of the one-bit full adder is '1', the first input signal A accessed by the first input end and the second input signal B accessed by the second input end are both '0', for the carry output end of the one-bit full adder, the level signal of the carry output end of the one-bit full adder is pulled down due to the conduction of the first TFET tube and the fourth TFET tube, the carry output end of the one-bit full adder outputs low level 0, for the sum output end of the one-bit full adder, the level signal of the sum output end of the one-bit full adder is pulled up due to the conduction of the fifth TFET tube, the eighth TFET tube, the ninth TFET tube, the twelfth TFET tube and the thirteenth TFET tube, and the sum output end of the one-bit full adder outputs high level 0; the one-bit full adder can completely realize the corresponding logic function, realizes the full adder function through fourteen TFET tubes, and has the advantages of simpler circuit structure, smaller circuit area and power consumption and higher speed.

Drawings

FIG. 1 is a circuit diagram of a prior art one-bit full adder based on CMOS devices;

fig. 2 is a circuit diagram of a one-bit full adder based on a three-input TFET device according to the present invention;

fig. 3 is a simulation waveform diagram of the bsiimmg standard process based one-bit full adder based on the three-input TFET device of the present invention at the standard voltage (1 v).

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.