阅读说明：本技术 基于晶体管的puf设备 (Transistor-based PUF device ) 是由 J·E·D·赫维茨 于 2020-03-06 设计创作，主要内容包括：本公开涉及基于晶体管的PUF设备。本公开涉及用于生成持久性随机数的PUF设备和方法。生成的数是随机的,因为每个特定的PUF设备实例都应生成与所有其他PUF设备的实例随机不同的数,并且是持久的,因为每个PUF设备的特定实例都应在可接受的误差纠正公差内重复生成相同的数。通过选择一个或多个PUF单元(每个均包括设计相同的匹配的晶体管对)并比较该对的导通特性(例如,导通阈值电压或栅-源电压)来确定持久性随机数。每个选定的晶体管对的导通特性差异是由晶体管之间的随机制造差异引起的。这会导致PUF设备的每个不同实例之间的随机性,并且随着时间的推移应该相对稳定以提供所生成数的持久性。(The present disclosure relates to transistor-based PUF devices. The present disclosure relates to PUF devices and methods for generating persistent random numbers. The generated numbers are random because each particular instance of a PUF device should generate a number that is randomly different from all other instances of PUF devices, and persistent because each particular instance of a PUF device should repeatedly generate the same number within an acceptable error correction tolerance. Persistent random numbers are determined by selecting one or more PUF cells (each comprising a matched pair of transistors of identical design) and comparing the turn-on characteristics (e.g., turn-on threshold voltage or gate-source voltage) of the pair. The difference in the turn-on characteristics of each selected transistor pair is caused by random manufacturing differences between the transistors. This results in randomness between each different instance of the PUF device and should be relatively stable over time to provide persistence of the generated numbers.)

1. A physically unclonable function, PUF, device comprising:

a plurality of PUF cells, each PUF cell comprising:

a plurality of transistors, wherein the plurality of transistors comprises:

a pair of matched transistors for comparison of transistor turn-on characteristics, an

A selection mechanism for selecting the PUF cells, and wherein the plurality of transistors in each PUF cell are all of the same transistor type; and

a determination unit configured to:

selecting, in each of at least one of the plurality of PUF cells, at least one of the plurality of PUF cells using the selection mechanism;

for each selected PUF cell, determining a transistor difference value based at least in part on a comparison of conduction characteristics of matched transistor pairs in the selected PUF cell, wherein the transistor difference value is indicative of random manufacturing differences between the matched transistor pairs in the selected PUF cell; and

determining a PUF output based at least in part on the at least one determined transistor difference.

2. The apparatus of claim 1, wherein the selection mechanism comprises gate terminals of the transistor pair, and

wherein the determination unit is configured to select a PUF cell by applying a selection potential to one or more gate terminals of a matched pair of transistors in the PUF cell.

3. The apparatus of claim 1, wherein the selection mechanism comprises one or more selection transistors coupled with a matched transistor pair, and

wherein the determination unit is configured to control operation of the one or more selection transistors by applying a selection potential to the one or more selection transistors to select a PUF cell.

4. The apparatus of claim 1, wherein the comparison of the turn-on characteristics of the matched transistor pairs comprises a comparison of gate-to-source voltages of the matched transistor pairs.

5. The device of claim 1, wherein the determination unit is configured to determine the transistor difference value for the selected PUF cell by:

(a) applying a first input signal to a first transistor of the matched transistor pair;

applying a second input signal to a second transistor of the matched transistor pair; and

determining a first transistor comparison value by comparing a turn-on characteristic of the first transistor when the first input signal is applied and a turn-on characteristic of the second transistor when the second input signal is applied; then the

(b) Applying a second input signal to a first transistor of the matched transistor pair;

applying a first input signal to a second transistor of the matched transistor pair; and

determining a second transistor comparison value by comparing a turn-on characteristic of the first transistor when the second input signal is applied and a turn-on characteristic of the second transistor when the first input signal is applied; and then

(c) Determining the transistor difference value based on the first transistor comparison value and the second transistor comparison value.

6. The device of claim 5, wherein the determination unit is configured to:

in (a), simultaneously applying the first input signal to the first transistor and the second input signal to the second transistor; and

in (b), the second input signal is simultaneously applied to the first transistor and the first input signal is simultaneously applied to the second transistor.

7. The apparatus of claim 5, wherein the determining unit further comprises:

at least one first current source configured to output a first current signal; and

a second current source configured to output a second current signal;

wherein the first input signal comprises the first current signal and the second input signal comprises the second current signal.

8. The apparatus of claim 5, wherein the first input signal comprises a first voltage signal and the second input signal comprises a second voltage signal.

9. The apparatus of claim 8, wherein at least one of the first voltage signal and the second voltage signal varies over time.

10. The apparatus of claim 8, wherein the determination unit is configured to:

during determination of a first transistor comparison value for a selected PUF cell, applying the first voltage signal to a gate terminal of the first transistor and applying the second voltage signal to a gate terminal of the second transistor; and

during determining a second transistor comparison value for a selected PUF cell, the second voltage signal is applied to the gate terminal of the first transistor and the first voltage signal is applied to the gate terminal of the first transistor to rotate the PUF cell.

11. The device of claim 10, wherein the selection mechanism comprises gate terminals of the matched pair of transistors, and wherein the first voltage signal and the second voltage signal also serve as selection potentials for selecting the PUF cell.

12. The apparatus of claim 1, wherein the matched transistor pair (210)_x,y) Is configured as a differential pair, and

wherein the matched pair of transistors forms an input of a comparator.

13. The apparatus of claim 12, wherein the transistor difference value comprises a digital value indicative of random manufacturing differences between the matched transistor pair, and

wherein the determining unit comprises an analog-to-digital converter for determining the difference of the transistors, an

Wherein the analog-to-digital converter comprises a comparator.

14. The apparatus of claim 1, wherein each matched transistor pair comprises a first transistor and a second transistor, an

Wherein the first transistor includes a first sub-transistor and a second sub-transistor, an

Wherein the second transistor includes a third sub-transistor and a fourth sub-transistor, an

Wherein the first, second, third, and fourth sub-transistors are arranged in a semiconductor layout such that a centroid of the first transistor is substantially the same as a centroid of the second transistor.

15. The apparatus of claim 14, wherein the first, second, third, and fourth sub-transistors are arranged in a semiconductor layout such that:

when the first transistor conducts current, channel current in the first sub-transistor flows in a first direction in the semiconductor and channel current in the second sub-transistor flows in a second direction in the semiconductor, and

when the second transistor conducts current, a channel current in one of the third sub-transistor and the fourth sub-transistor flows in a first direction and a channel current in the other of the third sub-transistor and the fourth sub-transistor flows in a second direction, and

wherein in the semiconductor layout the first direction and the second direction are substantially opposite spatial directions.

16. The apparatus of claim 14 or 15, wherein the semiconductor layout of the matched transistor pair is arranged such that the first and third sub-transistors share a drain terminal and the second and fourth sub-transistors share another drain terminal.

17. A method of determining a physically unclonable function, PUF, output using a plurality of PUF cells, each PUF cell including a plurality of transistors of a same transistor type, the plurality of transistors including matched transistor pairs and a selection mechanism for selecting the PUF cell, the method comprising:

selecting one or more PUF cells in each of at least one of the plurality of PUF cells using a selection mechanism;

for each selected PUF cell, determining a transistor difference value based at least in part on a comparison of conduction characteristics of matched transistor pairs in the selected PUF cell, wherein the transistor difference value is indicative of random manufacturing differences between the matched transistor pairs in the selected PUF cell; and

determining a PUF output based at least in part on the at least one determined transistor difference.

18. The method of claim 17, wherein determining the transistor difference for the selected PUF cell comprises:

applying a first input signal and a second input signal to a first transistor of the matched pair of transistors and a second transistor of the matched pair of transistors, respectively;

determining a first transistor comparison value by comparing the turn-on characteristics of the matched transistor pair;

applying the first input signal and the second input signal to the second transistor and the first transistor, respectively;

determining a second transistor comparison value by comparing turn-on characteristics of the matched transistor pair; and

determining the transistor difference value based on the first transistor comparison value and the second transistor comparison value.

19. The method of claim 18, wherein the first input signal comprises a first current and/or a first voltage signal, and

wherein the second input signal comprises a second current and/or a second voltage signal.

20. The method of claim 18, wherein rotating the PUF cell includes applying a selection potential to one or more of the gate terminals of the matched transistor pair in the PUF cell.

Technical Field

The present disclosure relates to transistor-based Physically Unclonable Functions (PUFs).

Background

A physically unclonable function or "PUF" is a physical entity that is capable of generating an output ("response") for a given input ("challenge") that is specific to that particular PUF, such that it can be considered a "fingerprint". This capability is usually achieved by designing PUFs whose output pattern depends on features that differ randomly in each device due to subtle variations in manufacturing. Thus, even with full knowledge of its circuit layout, a PUF cannot easily be duplicated with the correct fingerprint. The response may be used for a variety of different purposes, such as in cryptographic operations to secure communications with the device containing the PUF, or for methods of authenticating the identity of the device including the PUF, and the like.

Disclosure of Invention

The present disclosure relates to PUF devices for generating persistent random numbers. The numbers are random because each particular instance of a PUF device should generate a randomly different number than all other instances of PUF devices, and persistent because each particular instance of a PUF device should repeatedly generate the same number within an acceptable error correction tolerance. The random number is determined by selecting one or more PUF cells (each comprising a matched pair of transistors of identical design) and comparing the turn-on characteristics (e.g., turn-on threshold voltage or gate-source voltage) of the pair. The difference in the turn-on characteristics of each selected transistor pair is caused by random manufacturing differences between the transistors, which results in randomness between each different instance of the PUF device, which should be relatively stable over time, which helps to generate the persistence of the numbers.

The PUF device may include one or more PUF cells, each PUF cell including: physical features that differ randomly from device to device due to minor variations in manufacturing; and some determination circuits configured to read out a PUF value from each PUF cell. The PUF device may be configured such that the determination circuit may read out a random PUF value from each PUF cell and generate a persistent random number based on the PUF value. The persistent random number is then used as part of determining a "response" to the "challenge". For example, the PUF device may receive a "challenge" from another circuit, the determination circuit may then read a persistent random number from the PUF cell, and the PUF device may then determine a "response" based on the "challenge" and the "persistent random number" (e.g., but perform some cryptographic operation, such as a hash or XOR, or encrypt using the "challenge" and the persistent random number). The persistent random number is random because its value depends on small random manufacturing deviations between different PUF devices. Thus, although different instances of PUF devices are identical in design, each instance should generate a different persistent random number. The random number is "permanent" in that it should remain the same or within an acceptable range over time. For example, the permanent random number generated by one or more PUF cells of a PUF device should be the same (or remain within an acceptable range, e.g. so that it can be corrected using the error correction code ECC) each time it is generated, so that it can serve as a reliable fingerprint for the device.

In a first aspect of the disclosure, there is provided a physically unclonable function, PUF, device comprising: a plurality of PUF cells, each PUF cell comprising a plurality of transistors, wherein the plurality of transistors comprises a pair of matched transistors for transistor turn-on characteristic comparison, and a selection mechanism for selecting the PUF cell, and wherein the plurality of transistors in each PUF cell are all of the same transistor type; and a determination unit configured to select at least one of the plurality of PUF cells using the selection mechanism in each of the at least one of the plurality of PUF cells; for each selected PUF cell, determining a transistor difference value based at least in part on a comparison of conduction characteristics of matched transistor pairs in the selected PUF cell, wherein the transistor difference value is indicative of random manufacturing differences between the matched transistor pairs in the selected PUF cell; and determining the PUF output based at least in part on the at least one determined transistor difference.

The selection mechanism may comprise gate terminals of said pair of transistors, and wherein the determination unit is configured to select a PUF cell by applying a selection potential to one or more gate terminals of a matching pair of transistors of said PUF cell.

The selection mechanism may comprise one or more selection transistors coupled with the matched pair of transistors, and wherein the determination unit is configured to control operation of the one or more selection transistors by applying a selection potential to the one or more selection transistors to select the PUF cell.

The comparison of the turn-on characteristics of the matched transistor pairs may include a comparison of gate-source voltages of the matched transistor pairs.

The determination unit may be configured to determine the transistor difference value for the selected PUF cell by: (a) applying a first input signal to a first transistor of the matched transistor pair; applying a second input signal to a second transistor of the matched transistor pair; and determining a first transistor comparison value by comparing a turn-on characteristic of the first transistor when the first input signal is applied and a turn-on characteristic of the second transistor when the second input signal is applied; then (b) applying a second input signal to a first transistor of the matched transistor pair; applying a first input signal to a second transistor of the matched transistor pair; and determining a second transistor comparison value by comparing a turn-on characteristic of the first transistor when the second input signal is applied and a turn-on characteristic of the second transistor when the first input signal is applied; and then (c) determining the transistor difference value based on the first transistor comparison value and the second transistor comparison value (e.g., based on a sum, average, or difference of the first and second transistor comparison values).

The determining unit (170) may be configured to, in (a), simultaneously apply the first input signal to the first transistor and the second input signal to the second transistor; and in (b), simultaneously applying the second input signal to the first transistor and the first input signal to the second transistor.

The determination unit (170) may further include: at least one first current source (232)_x) Configured to output a first current signal; and a second current source (234)_x) Configured to output a second current signal; wherein the first input signal comprises the first current signal and the second input signal comprises the second current signal.

The first input signal may comprise the first voltage signal and the second input signal comprises the second voltage signal.

At least one of the first voltage signal and the second voltage signal varies over time.

The determination unit may be configured to apply the first voltage signal to a gate terminal of the first transistor and apply the second voltage signal to a gate terminal of the second transistor during the determination of the first transistor comparison value for the selected PUF cell; and during determining a second transistor comparison value for a selected PUF cell, applying the second voltage signal to the gate terminal of the first transistor and applying the first voltage signal to the gate terminal of the first transistor to rotate the PUF cell.

The selection mechanism may comprise gate terminals of said matched pair of transistors, and wherein said first voltage signal and said second voltage signal also serve as selection potentials for selecting said PUF cell.

The matched transistor pair may be configured as a differential pair, and wherein the matched transistor pair forms an input of the comparator.

The transistor difference value may comprise a digital value indicative of random manufacturing differences between the matched transistor pairs, and wherein the determining unit comprises an analog-to-digital converter for determining the transistor difference value, and wherein the analog-to-digital converter comprises a comparator.

Each matched transistor pair may comprise a first transistor and a second transistor, and wherein the first transistor comprises a first sub-transistor and a second sub-transistor, and wherein the second transistor comprises a third sub-transistor and a fourth sub-transistor, and wherein the first, second, third and fourth sub-transistors are arranged in a semiconductor layout such that a centroid of the first transistor is substantially the same as a centroid of the second transistor.

The first, second, third and fourth sub-transistors may be arranged in a semiconductor layout such that: channel current in the first sub-transistor flows in a first direction in the semiconductor and channel current in the second sub-transistor flows in a second direction in the semiconductor when the first transistor conducts current, and channel current in one of the third and fourth sub-transistors flows in the first direction and channel current in the other of the third and fourth sub-transistors flows in the second direction when the second transistor conducts current, and wherein in the semiconductor layout the first and second directions are substantially opposite spatial directions.

The semiconductor layout of the matched transistor pair may be arranged such that the first and third sub-transistors share a drain terminal and the second and fourth sub-transistors share another drain terminal.

In a second aspect of the disclosure, a method of determining a Physically Unclonable Function (PUF) output using a plurality of PUF cells, each PUF cell comprising a plurality of transistors of a same transistor type, the plurality of transistors comprising a matched pair of transistors and a selection mechanism for selecting the PUF cell, the method comprising selecting one or more PUF cells (105) using the selection mechanism in each of at least one of the plurality of PUF cells_x,y) (ii) a For each selected PUF cell, determining a transistor difference value based at least in part on a comparison of conduction characteristics of matched transistor pairs in the selected PUF cell, wherein the transistor difference value is indicative of random manufacturing differences between the matched transistor pairs in the selected PUF cell; and determining the PUF output based at least in part on the at least one determined transistor difference.

Determining the transistor difference for the selected PUF cell may include: applying a first input signal and a second input signal to a first transistor of the matched pair of transistors and a second transistor of the matched pair of transistors, respectively; determining a first transistor comparison value by comparing the turn-on characteristics of the matched transistor pair; applying the first input signal and the second input signal to the second transistor and the first transistor, respectively; determining a second transistor comparison value by comparing turn-on characteristics of the matched transistor pair; and determining the transistor difference value based on the first transistor comparison value and the second transistor comparison value.

The first input signal may comprise a first current and/or first voltage signal and the second input signal may comprise a second current and/or second voltage signal.

Selecting the PUF cell may include applying a selection potential to one or more of the gate terminals of the matched transistor pair in the PUF cell.

In a third aspect of the disclosure, there is provided a device (e.g. a PUF device) comprising: a pair of transistors, comprising: a first transistor; and a second transistor coupled to the first transistor to form the transistor pair; wherein the first transistor comprises a first sub-transistor and a second sub-transistor, and wherein the second transistor of the transistor pair comprises a third sub-transistor and a fourth sub-transistor.

The first, second, third, and fourth sub-transistors may be arranged in a semiconductor layout such that a centroid of the first transistor is substantially the same as a centroid of the second transistor.

The semiconductor layout of the transistor pair may be arranged such that the first and third sub-transistors share a drain terminal and the second and fourth sub-transistors share another drain terminal.

The first, second, third, and fourth sub-transistors may be arranged in a semiconductor layout such that: channel current in the first sub-transistor flows in a first direction in the semiconductor and channel current in the second sub-transistor flows in a second direction in the semiconductor when the first transistor conducts current, and channel current in one of the third and fourth sub-transistors flows in the first direction and channel current in the other of the third and fourth sub-transistors flows in the second direction when the second transistor conducts current, and wherein in the semiconductor layout the first and second directions are substantially opposite spatial directions.

The apparatus may further include: a further pair of transistors having the same semiconductor design as the pair of transistors, wherein the pair of transistors and the further pair of transistors are arranged in a semiconductor layout such that the second sub-transistor of the pair of transistors and the first sub-transistor of the further pair of transistors share a source terminal.

The drain terminal of the first transistor of the transistor pair and the drain terminal of the first transistor of the further pair of transistors may be coupled to a first common signal output line, and wherein the drain terminal of the second transistor of the transistor pair and the drain terminal of the first transistor of the further pair of transistors may be coupled to a second common signal output line.

The apparatus may further comprise a further pair of transistors, wherein the apparatus comprises: a first gate structure forming gates for the first transistor of the transistor and the first transistor of the further pair of transistors such that a gate potential of the first transistor of the transistor and a gate potential of the first transistor of the further pair of transistors are substantially the same; and a second gate structure forming gates for the second transistor of the transistor and the second transistor of the further pair of transistors such that a gate potential of the second transistor of the transistor and a gate potential of the second transistor of the further pair of transistors are substantially the same.

The first and second transistors may be MOS devices (e.g., PMOS devices).

The device may also include pairs of transistors arranged in a two-dimensional array.

Drawings

Aspects of the present disclosure are described, by way of example only, with reference to the following drawings, in which:

fig. 1 shows an exemplary schematic diagram of a PUF device according to an aspect of the present disclosure.

Fig. 2 shows an exemplary schematic diagram of an embodiment of a PUF cell and a determination unit of the PUF device of fig. 1.

Figure 3 shows an example schematic of the array of PUF cells of figure 2.

Fig. 4 shows an exemplary schematic diagram of another embodiment of the PUF cell and the determination unit of the PUF device of fig. 1.

Figure 5 shows a graph representing the operational signals in the PUF device of figure 4.

Figure 6 shows an example schematic of the array of PUF cells of figure 4.

Fig. 7 shows an exemplary schematic diagram of another embodiment of the PUF cell and the determination unit of the PUF device of fig. 1.

FIG. 8 shows a schematic diagram illustrating a pair of transistors and a portion of a comparator block;

figure 9 shows an example representation of an array of PUF cells comprising a pair of transistors of figure 8 and a determination cell comprising part of the comparator block of figure 8;

fig. 10A-10D show example schematic diagrams of an arrangement of a pair of transistors.

Fig. 11A shows an example schematic of a pair of transistors.

Fig. 11B shows an example schematic of a pair of transistors of fig. 11A implemented by sub-transistors.

Fig. 12 shows an exemplary semiconductor layout of the sub-transistor of fig. 11B.

Fig. 13 shows an example schematic of an array of the semiconductor layout of fig. 12.

Figure 14 shows an example schematic of a PUF cell that includes a pair of transistors and a separate selection mechanism.

Fig. 15 shows an example schematic of another embodiment of a PUF cell.

Fig. 16 shows an exemplary schematic of another embodiment of a PUF cell. And

figure 17 shows a graphical representation of a method for determining a PUF output using a plurality of PUF cells.

Detailed Description

The inventors have found many different challenges in implementing a PUF device having one or more PUF cells. First, each possible output of a PUF cell should have an equal or substantially equal probability. For example, if a PUF cell is configured to output a "1" or a "0" according to random manufacturing variations of the PUF cell, there should be a probability of the "1" or the "0" being equal or substantially equal. If not, the output of the PUF cell may not be sufficiently random. To achieve this, the circuit design and layout configuration of each PUF cell and the whole PUF device are required, which will not favor any one particular possible output value.

Secondly, PUF devices are preferably low cost in terms of power consumption and/or area used in an Integrated Circuit (IC) and/or time required to produce a PUF output, so that they can be more easily implemented in a device. For example, PUF devices are particularly useful for internet of things (IoT) device security, e.g., to authenticate the identity of an IoT device and/or to secure communications to/from an IoT device. In order to include a PUF device in an internet of things device, it is helpful that the PUF device is cheap and/or low power and/or small.

To address at least some of these challenges, a PUF device is disclosed herein that includes a plurality of PUF cells 105_x,y. Each PUF cell includes a plurality of transistors 210 all of the same transistor type_x,yAnd includes a selection mechanism and a matched pair of transistors 210_x,y. The matched transistor pairs are identical in design but inherently have some random manufacturing differences that will result in differences in their on-state characteristics. The selection mechanism of one or more particular PUF cells may be used to select for measurement and to select the difference between the on-state characteristics (e.g., gate-source voltage) for the matching transistor pairs in the selected one or more cells. Based on a comparison of the on-state characteristics of one or more PUF cells, a persistent random number may be generated as a PUF output.

By having multiple transistors in each cell of the same type (e.g., all p-type or all n-type), each PUF cell can be made very small in size, which can increase the density of the PUF cells, thereby reducing the overall size of the PUF device. In addition to this, the reduction in size can improve the randomness of the transistor on-state characteristics of each cell by mitigating any biasing of one or the other transistor across the cell caused by gradients such as doping gradients or oxide gradients. Further, by comparing the on-state characteristics of the matched transistor pair (for example, contrary to the failure characteristics), reliability can be improved since a high voltage is not applied and the gate oxide is not deteriorated, and the transistor pair can be used for other purposes, for example, as a selection mechanism, thereby reducing the size of each cell even further.

Fig. 1 shows an exemplary schematic diagram of a PUF device 100 according to an aspect of the present disclosure. The PUF device comprises a plurality of PUF cells 105_x,yA determination unit 170 and a challenge/response unit 180. Although only PUF cells 105 are shown_x,yBut it should be understood that any number of PUF cells (e.g., 8, 12, 20, 32, 128, 256, etc.) may be arranged in an array of any size and dimension or in any other suitable configuration.

The determination unit 170 is configured to use a plurality of PUF cells 105_x,yTo determine the PUF output. The PUF output is a persistent random number, as will be explained in detail in the "background" section of this disclosure.

The challenge/response unit 180 is configured to receive a "challenge" from an external entity, request and obtain a PUF output from the determination unit 170, and then determine and return a response based on the challenge and the PUF output. The challenge/response unit 180 may be configured to operate in any suitable manner, as will be apparent to those skilled in the art of PUF devices. The challenge/response unit 180 may form a separate unit or may be part of the determination unit 170. The disclosure relates specifically to PUF cells 105_x,yAnd the configuration and operation of the determination unit 170, as described in detail below. Accordingly, no further reference or explanation to the challenge/response unit 180 is given in this disclosure.

Fig. 2 shows a schematic diagram of an example embodiment of the PUF cell 105 and a determination unit 170 configured to determine a PUF value of the PUF cell 105.

Figure 3 shows a PUF cell 105_x,yEach array being configured in the same way as the PUF cell 105 shown in figure 2.

Returning to fig. 2, the PUF cell 105 includes a matched transistor pair 210. In the present disclosure, the term "matched" means that the pair of transistors have the same design. Although fig. 2 shows a representation of a pair of matched p-type FETs, it should be understood throughout this disclosure that in each of the various described aspects, the matched transistor pair 210 may be any transistor type, such as p-type, n-type, enhancement, depletion, FETs (e.g., MOSFETs, JFETs, MESFETs, etc.), BJTs (e.g., IGBTs, heterojunction bipolar transistors, etc.), etc. For simplicity, the present disclosure is directed specifically to FETs, but it should be understood that the terms "gate", "source" and "drain" as used herein encompass the terms "base", "emitter" and "collector" of BJTs.

Although the two transistors making up the matched transistor pair 210 have the same design, in practice there will inevitably be small random manufacturing variations between the two transistors. These manufacturing differences may include at least one of: differences in gate oxide thickness, differences in doping density, differences in carrier mobility, differences in device dimensions, and the like. These manufacturing variations can result in variations in transistor on-state characteristics/performance, such as variations in turn-on threshold voltage, variations in β, variations in back-gate effects, and the like. The term "on-state" is used throughout this disclosure to refer to the operational characteristics of a transistor that are relevant to its normal on-state operation, such as on-threshold voltage, gate-source voltage, drain current, linear resistivity, saturation point, transconductance. By taking the on-state characteristics into consideration, the reliability of the PUF device 100 can be improved, as opposed to off-state characteristics (e.g., off-state leakage current) or failure characteristics (e.g., dielectric breakdown), without gate oxide degradation or the like due to no application of high voltage. Furthermore, the matched transistor pair 210 may be used for other purposes besides characteristic comparison, such as forming part of a selection mechanism (described later).

The determination unit 170 is configured to determine transistor difference values based at least in part on a comparison of on-state characteristics of the matched transistor pair 210, wherein the transistor difference values are indicative of one or more random manufacturing differences between the matched transistor pair 210. In this implementation, the comparative on-state characteristic of the matched transistor pair 210 is the gate-source voltage (V) of the two transistors_GS). V of these two transistors as a result of one or many different random manufacturing differences_GSMay be different, for example, this may lead toResulting in different on-threshold voltages and/or β and/or back-gate effects for the transistors.

The drains of matched transistor pair 210 are connected to ground. The determination unit 170 comprises a selector circuit 220, the selector circuit 220 being configured to apply a suitable voltage to the gates of the matched transistor pair 210 in order to turn on the transistors. This voltage serves as the "selection potential", which is explained in more detail below with reference to fig. 3. The determination unit 170 further includes a first current source 232 and a second current source 234 configured to provide the same current as each other. Current from the first current source 232 may be applied as a first input signal to the source of a first transistor of the matched transistor pair 210, and current from the second current source 234 may be applied as a second input signal to the second source of a second transistor of the matched transistor pair 210. If the matched transistor pair 210 is truly identical, their source voltages will be identical. However, due to random manufacturing variations, the gate-to-source voltages of the two transistors may be different, and since the gate voltages applied to the matched transistor pair 210 are the same, the source voltages of the matched transistor pair 210 should be different.

The determination unit 170 further includes an ADC 250 configured to measure a difference in gate-source voltages and output a digital value indicative of the difference. However, it has been recognized that there may be some mismatch between the currents provided by the first current source 232 and the second current source 234. Thus, a chopper circuit 236 may be provided such that a first input signal (current from the first current source 232) may be applied to the first transistor, a second input signal (current from the second current source 234) may be applied to the second transistor and the first transistor comparison value determined by the ADC 250 by comparing the gate-source voltages of the matched transistor pair 210. The chopper circuit 236 may then switch the coupling of the first current source 232 and the second current source 234 such that the first input signal is applied to the second transistor, the second input signal is applied to the first transistor, and the ADC 250 compares the gate-source voltages of the matched transistor pair 210 to determine a second transistor comparison value.

The first and second transistor comparison values may be expressed as:

first transistor mismatch value Δ V_GS+ mismatch + noise 1

Mismatch value of the second transistor is equal to Δ V_GSMismatch + noise 2

The transistor difference of the PUF cell 105 may then be determined based on the first transistor comparison value and the second transistor comparison value, e.g. from a sum or average of the first transistor comparison value and the second transistor comparison value.

For example, the transistor difference can be expressed as:

the transistor difference is equal to the first mismatch value + the second mismatch value

＝2*ΔV_GS+ noise 1+ noise 2

Or

Transistor difference being the average of the first mismatch value and the second mismatch value

＝ΔV_GS+ (noise 1+ noise 2)/2

In this manner, any measurement error caused by the mismatch between the first current source 232 and the second current source 234 may be significantly reduced or eliminated to a first order. Furthermore, since noise 1 and noise 2 are largely uncorrelated, the signal-to-noise ratio can usually also be improved by about √ 2. It will be appreciated that the chopper circuit 236 is optional and the determination unit 170 may be configured to determine the transistor difference from a single comparison of the gate-source voltages, for example, if the first and second current sources are considered to be matched to a sufficiently high accuracy.

Further, optionally, a further chopper circuit 240 may be provided at the input of the ADC 250. Which may be similar to chopper circuit 236 and operate simultaneously with chopper circuit 236 to switch the coupling of the differential inputs to the comparators in ADC 250. However, in this case, the first transistor compares Δ V in the value due to switching to the input of the comparator in the ADC 250_GSThe sign of the component will be compared with Δ V in the value of the second transistor_GSThe signs of the components are different. For example, in the case where the chopper circuits 236 and 240 are used simultaneously:

first transistor mismatch value Δ V_GS+ mismatch + offset + noise 1

Mismatch value of the second transistor is- Δ V_GS+ mismatch + offset + noise 2

Where the offset is the offset of the ADC 250.

In this case, the transistor difference value may be determined by taking the difference between the first transistor comparison value and the second transistor comparison value. For example:

the transistor difference value is equal to the first mismatch value-the second mismatch value

＝2*ΔV_GS+ noise 1-noise 2

Using the chopper circuit 236 in this manner may help to cancel any offset in the ADC 250 and any mismatch between the first and second current sources 232, 234. Further, Δ V_GSThe components are increased by 2 times, and the low frequency components of noise 1 and noise 2 should cancel each other. However, it will be appreciated that the chopper circuit 240 is optional depending on the configuration of the ADC 250 and the quality of the components making up the ADC 250. Furthermore, the determination unit 170 may not comprise the ADC 250, but any other suitable circuitry may alternatively be used to determine the transistor difference, e.g. an analog only circuit.

The chopper circuit 236 and the additional chopper circuit 240 may be configured in any suitable manner to perform the switching/chopping functions described above. For example, they may each comprise one or more switches, which, as described above, may be controlled (e.g. by a control unit not shown in fig. 2) to switch/chop the couplings.

The transistor difference indicates which transistor of the matched transistor pair 210 has the larger/smaller V_GS. For example, if V of the first transistor_GSV is larger than that of the second transistor_GSThen it can simply be "1", if V of the first transistor is_GSV is smaller than that of the second transistor_GSThen it may simply be "0". Alternatively, it may also indicate the magnitude of the difference. For example, it may be V indicating the first transistor_GSV is larger than that of the second transistor_GSIs positive in magnitude, and may be a negative in magnitude, indicating V of the first transistor_GSV is smaller than that of the second transistor_GSThe number of the cells.

Turning to fig. 3, a plurality of PUF cells 105 are shown_x,yX-1, X and Y1, 2, Y-1, Y, such that the PUF cell 105_x,yThe total of (a) and (b) totals X Y. In this example, PUF cell 105_x,yArranged in an array comprising X columns and Y rows. The selector circuit 220 has Y outputs, one for each row of the array, and it can be seen that each output is coupled to all matched transistor pairs 210 in a particular row_x,yIs coupled to the gate of transistor pair 210 (e.g., a first output is coupled to transistor pair 210_x,1And a second output coupled to transistor pair 210_x,2Etc.). To select a PUF cell 105_x,yTo which the selector circuit 210 applies a selection potential (e.g., a potential that exceeds the turn-on threshold voltage of the transistor) to turn on the matched transistor pair 210 in that row_x,y. A non-selection potential is applied to all other rows (e.g., a potential less than the turn-on threshold voltage of the transistors). Thus, it can be seen that in this example, each matched transistor pair 210_x,yNot only for determining transistor differences, but also as its PUF cell 105_x,yThe selection mechanism of (1). By coupling each matched transistor pair 210_x,yFor both purposes, the size of the array of PUF cells may be reduced compared to an array comprising a pair of transistors for determining the PUF value and one or more further transistors for selecting the PUF cell.

It can also be seen that the determination unit 170 comprises X first and second current sources 232_xAnd 234_xX chopper circuits 236_xX additional chopper circuits 240_xAnd X ADCs 250_x. Thus, the X pairs of transistors 210 in the selected row may be determined in parallel_x,yThereby increasing the operating speed. Furthermore, one column of the PUF array may share each set of first and second current sources 232_xAnd 234_x Chopper circuit 236_xAnd a further chopper circuit 240_xAnd ADC 250_xThereby reducing the number of required components and thus the overall size, cost and power consumption of the PUF device 100.

The determination unit 170 shown in fig. 3 further comprisesA PUF output unit 310 that: a) from each ADC 250_xReceiving a determined transistor difference, or b) from each ADC_xThe determined first and second transistor comparison values are received, and then a transistor difference value is determined based on the first and second transistor comparison values (e.g., by averaging them).

The determination unit 170 may be configured to determine the PUF cell 105 by selecting a row of PUF cells 105_x,yAnd determines a transistor difference value for each selected PUF cell to operate. Subsequently, the PUF cell 105 may be selected_x,yAnd for which the transistor difference is determined. Selector circuit 220, chopper circuit 236_xAnd a further chopper circuit 240_xMay be controlled in any suitable manner, e.g. by the PUF output unit 310 or any other suitable controller. For simplicity, the control interconnect is not shown in FIG. 3.

The PUF output determined by the PUF output unit 310 is a persistent random number, which may be, for example, a multi-bit number. For example, if the PUF device 100 is configured such that each PUF cell 105_x,yFor determining the value of one bit of a multibit PUF output, then if there are 128 PUF cells 105_x,yThen the output unit 310 may generate a 128-bit PUF output, with each PUF cell 105_x,yDetermines the value of each bit (i.e., "0" or "1"). For example, if it is a particular PUF cell 105_x,yThe determined transistor difference value indicates V of the first transistor_GSV is larger than that of the second transistor_GSThe corresponding bit in the PUF output may be set to 1. If it represents V of the first transistor_GSV is smaller than that of the second transistor_GSAnd therefore the corresponding bit in the PUF output may be set to 0. Since the result of each transistor comparison depends on the matched transistor pair 210_x,yFrom the random manufacturing differences between them, it can be seen that the PUF output should be random, since each different instance of the PUF device 100 is likely to produce a randomly different PUF output. Furthermore, the result of each transistor comparison should generally remain constant over time (i.e., if the V of the first transistor is determined)_GSV is smaller than that of the second transistor_GSThe value should not change over time) or remain acceptableIn range (e.g., a small number of matched transistor pairs 105_x,yMay be acceptable because the ECC may correct these changes) so that the PUF output is persistent.

In some implementations, PUF cell 105_x,yCan exceed the number of bits in the PUF output. In this case, all PUF cells 105 may be enrolled during enrollment of the PUF device 100_x,yThe transistor comparison described above is performed. Transistor pair 210 matched thereto_x,yIs found in V_GSPUF cell 105 with the largest difference in_x,yAnd may then be enrolled for future determination of PUF output. From then on, the remaining PUF cells 105 may effectively be ignored_x,y. By using only at V_GSPUF cell 105 with the largest difference in_x,yThe endurance of the PUF output may be improved because the variation over time in the magnitude of the difference in the transistor on-state characteristics (e.g., caused by component drift, measurement noise, etc.) is less likely to cause which of the two transistors has the greatest V_GSA change in (c).

Although the above specifically focuses on V_GSBut it should be understood that the on-state characteristics of other transistors may be compared in accordance with the present disclosure.

FIG. 15 shows an example configuration of a PUF cell 105 in which the transistor on-state characteristic being compared is the channel or drain current I_D. In such an arrangement, the matched transistor pair 210 may be selected by the selector circuit 220 and they may share a single current source 1510, as described above with reference to fig. 2 and 3. If the matched transistor pair 210 is identical, the channel current I through the first transistor of the pair_D1Will be in contact with the channel current I of the second transistor of the pair_D2The same is true. However, due to random manufacturing differences, I_D1And I_D2There may be a difference between them. The determination unit 170 comprises a current measurement unit 1520, the current measurement unit 1520 being configured to measure a difference between the currents, based on which the PUF output (similar to the description above with reference to fig. 3) can be determined. Optionally, the determination unit 170 may include a stamp 240, so that current measurement may be mitigatedAny imbalance in cell 1520. In this case, the current measurement unit 1520 may be configured to be based on I_D1And I_D2Then the chopper 240 switches the input to the current measurement unit 1520, and the current measurement unit 1520 then determines the second transistor comparison value. The transistor difference value may then be determined based on the first and second transistor comparison values, for example, by taking an average or sum of the first and second transistor comparison values without chopping 240, or by taking the difference between the first and second transistor comparison values with chopping 240.

Furthermore, although in the arrangements of fig. 2, 3 and 15, the two transistors in the matched transistor pair 210 are selected simultaneously, so their transistor on-state characteristics can be directly compared to each other, in an alternative embodiment, each transistor can be selected at a separate time and its transistor on-characteristics measured. The two measurements can then be compared to determine a transistor difference.

One particular example embodiment of such an arrangement is shown in fig. 16. The determination unit 170 comprises a current source 1610 and a selector circuit 1620, the selector circuit 1620 being configured to apply a selection potential to a first transistor of the matched transistor pair 1620 and to apply a non-selection potential to a second transistor of the matched transistor pair 210, so that only the first transistor of the pair is conducting. The MUX 1630 is configured to output a source voltage of the first transistor to the ADC1640 such that the ADC1640 can measure a transistor on-state characteristic of the first transistor, in this example the source voltage. The selector circuit 1620 may then apply a selection potential to the second transistor and apply a non-selection potential to the first transistor. Then, the MUX 1630 outputs the source voltage of the second transistor to the ADC1640 so that the ADC can measure the transistor on-state characteristics of the second transistor. The on-state characteristics of the first and second transistors may then be compared, for example, by the PUF output cell or some other suitable cell coupled to the ADC1640 and configured to receive and record a measure of the on-state characteristics of the transistors. The operation of selector circuit 1620 and MUX 1630 may be controlled by any suitable entity, e.g., by a control unit in determination unit 170. Furthermore, the skilled person will appreciate that by appropriately changing the configuration, for example the configuration illustrated above with reference to fig. 16, it is possible to select each transistor separately in matched transistor pairs and measure their transistor on-state characteristics, extending to all other arrangements described herein.

Fig. 4 illustrates another example configuration of a PUF device 100 in accordance with an aspect of the present disclosure. In the PUF device 100 shown in fig. 4, the PUF cell 105 includes a matched transistor pair 210 configured as a source follower in the same manner as in fig. 2. Furthermore, the determination unit 170 comprises a first current source 232, a second current source 234 and a chopper 236, the operation of which is as described above with reference to fig. 2. For example, the operation of first current source 232, second current source 234, and chopper 236 may be controlled, but PUF output cell 310 or any other suitable module/unit may be controlled.

However, in contrast to the arrangement shown in fig. 2, the determining unit 170 in this example further comprises a DAC 410 and a comparator 430, the operation of the DAC 410 being controlled by the PUF output unit 310. Hereinafter, the DAC 410, PUF output cell 310 and comparator 430 are configured to operate together as a slope converter ADC to compare transistor on-state characteristics of the matched transistor pair 210. Now, the operation of the determination unit 170 will be described with reference to fig. 5.

The DAC 410 outputs two "ramp signals" -a first ramp signal 411 that ramps from + full scale to-full scale, and a second ramp signal 412 that ramps from-full scale to + full scale. The PUF output unit 310 controls this operation by, for example, supplying the increased/decreased digital counter value to the DAC 410, converting the digital counter value of the DAC 410 into an analog ramp signal. To this end, the PUF output unit 310 may include at least one counter whose value is incremented or decremented. This can be seen in the "DAC ramp signal" diagram of fig. 5, which shows two repetitions of the ramp signal-one repetition for "transition 1" and another repetition for "transition 2". The selector circuit 420 is configured to output a pair of voltage signals 422. During "transition 1", for the selected row y, a first input signal is applied to the first transistor of the matched transistor pair 210, the first input signal comprising a first current signal from the first current source 232 and a first voltage signal from the selector circuit 420. The first voltage signal is a first ramp signal 411. A second input signal is applied to a second transistor of the matched transistor pair 210, the second input signal comprising a second current signal from the second current source 234 and a second voltage signal from the selector circuit 420. The second voltage signal is a second ramp signal 412.

It will be appreciated that the source voltage of the matched transistor pair 210 should vary with the ramp signal applied to the gates of the transistors. The input terminals of the comparators 430 are respectively coupled to the source terminals of the matched transistor pair 210. As will be understood by those skilled in the art, the output of comparator 430 should change from a low level to a high level when the signal at one input terminal becomes greater than the signal at the other input terminal, and vice versa. Referring to fig. 5, if the matched transistor pair 210 is absolutely identical, you can expect the output of comparator 430 to change substantially (i.e., substantially at the midpoint between-full scale and + full scale) at the instant the two ramp signals 411 and 412 cross. However, due to random manufacturing differences between the two transistors, their turn-on threshold voltages may be different, which means that their gate-source voltages may be different for the same gate voltage. Therefore, the timing at which the source voltages intersect and the output of the comparator 430 changes is unlikely to be the same as the timing at which the ramp voltages 411 and 412 intersect. This is represented by Δ in FIG. 5₁Shows that₁Is the difference between the gate voltages of the pair of transistors 210 that match at the time when the output of the comparator 430 changes. This change in the comparator 430 output may trigger the PUF output cell 310 to store an M-bit value that is used to control the counter of the DAC 410. At the moment the comparator 430 output changes, the M-bit value of the counter indicates the difference between the on threshold voltages of the matched transistor pair 210. This M-bit value is referred to herein as a "transition 1".

However, transition 1 may suffer from any mismatch between the first current source 232 and the second current source 234 and/or comparator 430_xAny inherent offset between the input terminals and/or any delay within the circuit.

In some cases, these inaccuracies may be small and negligible. In this case, transition 1 may be used as a transistor difference value that indicates a random manufacturing difference between the matched transistor pair 210 that has resulted in a difference between the turn-on threshold voltage/gate-source voltage of the matched transistor pair 210. In this case, no conversion 2 is needed at all, and the PUF output may be determined based at least in part on the transistor difference (as described previously with reference to fig. 2 and 3).

However, in other cases, any one or more of these contributions to inaccuracy may be too large to be ignored without causing an undesirable reduction in the randomness of the transistor differences and thus reducing the effectiveness of the PUF device 100 to produce sufficiently random PUF values. In this case, a second conversion may be performed, wherein the input signal of the PUF cell 105 and, optionally, the input terminal of the comparator 430 are switched.

In the second conversion, a first input signal is applied to the second transistor, the first input signal including a first current signal from the first current source 232 and a first voltage signal from the selector circuit 420. The first voltage signal is a first ramp signal 411. A second input signal is applied to the first transistor, the second input signal including a second current signal from the second current source 234 and a second voltage signal from the selector circuit 420. The second voltage signal is a second ramp signal 412. This switching of the current signals may be accomplished by the chopper circuit 236 in the same manner as previously described with reference to fig. 2 and 3. The switching of the voltage signals may be accomplished by the selector circuit 420 changing which of the ramp signals 411 and 422 is applied to which of the pair of voltage signals 422. Optionally, the chopper circuit 240 may also switch the input to the comparator 430, although in some cases the offset of the comparator 430 may be small enough to be negligible and the chopper circuit 240 may be omitted. To this end, the PUF output unit 310 may be configured to control the chopper circuit 236, the chopper circuit 240, and the selector circuit 420.

Fig. 5 shows a second transition and it can be seen that the difference between the ramp voltages is delta at the moment the output of comparator 430 changes₂. At that time, PUF output cell 310 may be triggered to store an M-bit count value that indicates the difference between the on threshold voltages of the matched transistor pair 210. From here on, this M-bit value is referred to as "transition 2".

The M-bit count value for transition 1 may be expressed as:

conversion 1 ═ Δ V_GS+ mismatch/offset + delay + noise 1

In this example, transition 1 is the first transistor comparison value.

The M-bit count value for transition 2 may be expressed as:

conversion 2 ═ Δ V_GS+ mismatch/offset + delay + noise 2

In this example, transition 2 is the second transistor comparison value.

It can be seen that Δ V is due to the switching of the input voltage signal_GSThe sign of (c) changes between transition 1 and transition 2. Thus, if we take the difference between transform 1 and transform 2, we will get:

transistor differential-transition 1-transition 2-2 x Δ V_GS+ (noise 1-noise 2)

Thus, by making two transitions in this manner and subtracting one from the other, any correlation errors and noise (e.g., mismatch/offset and delays in the circuit) between the two transitions can be significantly reduced or eliminated to one order. Further, Δ V_GSThe component is increased by 2 times, and the low frequency components of noise 1 and noise 2 should largely cancel each other. Thus, the accuracy of the transistor difference value, which is a measure of the difference between the gate-source voltages of the matched transistor pair 210, is improved. The PUF output may be determined based at least in part on the transistor difference (as previously described with reference to fig. 2 and 3), which may be a more reliable random number due to the increased accuracy of the transistor difference.

It will be appreciated that in this example, the first and second voltage signals applied to the matched transistor pair 210 are both ramp signals, which may improve the Common Mode Rejection Ratio (CMRR) of the circuit and make the measurement process cleaner. However, in alternative embodiments, only one of the first voltage signal and the second voltage signal may be a ramp voltage (increased or decreased), and the other voltage signal is a static reference voltage set to any suitable value between the upper and lower limits of the ramp signal.

In another alternative implementation, for example, an ADC including DAC 410, comparator 430, and PUF output unit 310 may be configured as a SAR ADC, e.g., with PUF output unit 310, DAC 410 is controlled differently by applying digital values to DAC 410 according to the operation of the SAR ADC rather than according to the operation of the slope ADC. In this alternative, the PUF output unit 310 may not include a counter, but may set a digital value in any other suitable manner depending on the operation of the SAR ADC. The use of SAR ADCs may help to increase conversion speed, but since the DAC input of SAR ADC cannot be shared between all cells in a row, a separate DAC needs to be assigned to each PUF cell 105 in succession_x,y。

Figure 6 shows a PUF cell 105_x,yEach PUF cell 105_x,yConfigured in the same manner as the PUF cell 105 shown in fig. 4. As can be seen, the selector circuit 420 has Y pairs of voltage signals 422_y. As previously described, by coupling the voltage signals 422_yIs set to a selection potential (in this example two ramp signals 411 and 412), selects all PUF cells 105 in that row_x,y. Another pair of voltage signals 422 output from the selector circuit 420_yIs held at a non-select potential that is lower than the matched transistor pair 210_x,ySuch that the PUF cell 105_x,yThe transistors in the other rows are turned off and thus not selected. For PUF cell 105_x,yProvides a first current source 232_xA second current source 234_x Chopper circuit 236_xAnother chopper circuit 240_xAnd comparator 430_x. PUF (physical unclonable function) outputThe output unit 310 is configured to receive each comparator 430_xSo that for each column it can be at a respective comparator 430_xThe counter value is stored at the time of output switching. As described above, the PUF output unit 430 or any other suitable unit may control the DAC 410, the selector circuit 420, and the chopper circuit 236_xAnd operation of another chopper circuit 240 x.

In operation, the selector circuit 420 may select a row of PUF cells 105_x,yFor example, PUF cells 105 of the first row_x,1. A transistor difference may be determined in parallel for each selected PUF cell. The selector circuit 420 may then select the PUF cell 105_x,yE.g. PUF cell 105_x,2The second row of (2). A transistor difference may then be determined in parallel for each selected PUF cell. In this way, all PUF cells 105 may be addressed_x,yThe transistor difference is determined, and then the PUF output may be determined by the PUF output unit 310 based on the transistor difference, as previously described with respect to fig. 3.

In some implementations, PUF cell 105_x,yCan exceed the number of bits in the PUF output. In this case, all PUF cells 105 may be enrolled during enrollment of the PUF device 100_x,yThe transistor comparison described above is performed. PUF cell 105 found to have the greatest difference in turn-on threshold voltage between transistors_x,yAnd may then be enrolled for future determination of PUF output. From then on, the remaining PUF cells 105 may effectively be ignored_x,y. By using only the PUF cell 105 with the largest difference in turn-on threshold voltage_x,yThe durability of the PUF output can be improved because a change in the magnitude of the difference in the on-state characteristics of the transistors (e.g., a change caused by component drift, measurement noise, etc.) over time is less likely to cause a change in which of the two transistors has the largest on-threshold voltage.

By parallel selection of X pairs of transistors 210 in a selected row_x,yDetermining the transistor difference may improve the operation speed of the PUF device 100. Furthermore, one column of the PUF array may share each set of first and second current sources 232x and 234x, chopper circuit 236x, whichHis chopper circuit 240x and ADC 250x, thereby reducing the number of required components, and thus reducing the overall size, cost and power consumption of the PUF device 100. Furthermore, the determination unit 170 only needs to include one DAC 410 and one counter (or similar counters) in the PUF output unit 310, thereby maximizing the resource sharing of the entire PUF array and minimizing the number of required components, thereby minimizing the overall size, cost and power consumption of the PUF device 100. Thus, the PUF device 100 may be made relatively small, dense and low power consuming.

It should be appreciated that in another embodiment of the PUF device 100 shown in fig. 4 and 6, the PUF device 100 may be configured to determine one or more PUF cells 105 from different transistor on-state characteristics (e.g., as described above with reference to fig. 15)_x,yThe difference of the transistors.

Fig. 7 illustrates another example configuration of a PUF device 100 in accordance with an aspect of the present disclosure. The PUF device 100 represented in fig. 7 is very similar to the PUF device represented in fig. 4, except that the PUF cell 105 includes a matched pair of transistors 210 configured as a differential pair, and a single current source 720 may be provided for the tail current of the differential pair. Furthermore, the comparator 730 may be implemented differently from the comparator 430 of fig. 4, as explained in more detail later.

Comparator 730 is coupled to the drains of matched transistor pair 210 so that when one of the drain currents becomes larger than the other, the output of comparator 730 should change. Since the gate voltage of each transistor is held at the potential of the pair of voltages 422 and the source voltage of each transistor is held by the current source 720, random manufacturing differences (e.g., differences that cause turn-on threshold voltages, and thus gate-source voltages) between the matched transistor pair 210 can be detected by means of differences in the drain currents of the matched transistor pair 210. To determine the transistor difference, two transitions may be performed as described above with reference to fig. 5, the only difference being that the first input signal comprises only the first voltage signal (first ramp signal 411), the second input signal comprises only the second voltage signal (second ramp signal 412), because there is a single current source 720, andand the output of comparator 730 changes when the drain currents of matched transistor pair 210 cross (rather than when the source voltages cross). Each transition generates a transistor comparison value indicative of the turn-on threshold voltage/V of the matched transistor pair 210_GSThe difference in (a).

As previously described, the M-bit count value for transition 1 may be expressed as:

conversion 1 ═ Δ V_GS+ offset + delay + noise 1

The first transistor of transition 1 compares the values and the offset is the offset of comparator 730.

The M-bit count value for transition 2 may be expressed as:

conversion 2 ═ Δ V_GS+ offset + delay + noise 2

Transition 2 is the second transistor comparison value.

As has been described in the foregoing, the present invention,

transistor differential-transition 1-transition 2-2 x Δ V_GS+ (noise 1-noise 2)

Thus, the indication Δ V may be more accurately determined by mitigating offset and delay inaccuracies_GSAnd thus a transistor difference value indicative of random manufacturing differences. However, as previously mentioned, in some implementations where the offset and delay are considered to be small enough to be negligible, the transistor difference can be found from a single transition, such as transition 1 or transition 2, and is the transistor difference.

Further, although in this example the first voltage signal is the first ramp signal 411 and the second voltage signal is the second ramp signal 412, in an alternative only one of the voltage signals may be a ramp signal (rising or falling) and the second voltage signal may be a fixed reference voltage fixed to any suitable value (as previously described). In another alternative, as previously described, PUF output cell 310 may be configured to drive DAC 410 instead of functioning as a slope ADC, such that the ADC functions as a SAR ADC.

The inventors have recognized that by implementing the matched transistor pair 210 as a differential pair, the matched transistor pair 210 may form an input transistor of the comparator 730. This can be more fully understood from fig. 8.

Fig. 8 shows a schematic diagram showing matched transistor pair 210 and partial comparator block 830, which together form a complete comparator. As will be understood by those skilled in the art, the matched transistor pair 210 forms a differential pair at the input of the full comparator, with the differential input of the full comparator being applied to the gates of the differential pair. Those skilled in the art will also recognize that the transistors in the partial comparator block 830 form the remaining preamplifiers of the complete comparator and that the latch circuit completes the complete comparator. Thus, the determination unit 170 in this example, in which the matched transistor pair 210 forms a differential pair, may be configured with both the full comparator 730 and the matched transistor pair 210, or it may be configured with the partial comparator module 830 and the matched transistor pair 210.

Figure 9 illustrates a PUF cell 105 in accordance with this aspect of the disclosure_x,yIn which a partial comparator block 830 is used_x. The determination of the transistor difference and the PUF output can be understood from the previous description with respect to fig. 4, 6 and 7. However, as can be appreciated from FIG. 10, by utilizing a portion of the comparator module 830_xTwo fewer transistors are required for each column because the input differential pair for the complete comparator for column x is selected by the matched transistor pair 210 in column x_x,yAnd (4) forming. This further reduces the overall size and power consumption of the PUF device 100, thereby increasing density and reducing cost. Furthermore, this means that any comparator offset caused by the input differential pair 210 of the full comparator is actually caused by Δ V_GSAnd therefore, does not result in the "offset" component of "transition 1" and "transition 2" described above. Since now fewer components result in an undesired "offset" component (only some of the components in the comparator block 830 have a relatively small effect on the input reference offset), the "offset" can be reduced to a negligible level, so that only one transition is needed to determine the transistor difference, in which case the further chopper circuit 240 can be omitted_x. However, in some cases, the offset of the partial comparator block 830 may be sufficient to require additional chopper circuit 240_xAnd upper part ofAnd (4) performing the two conversions.

Transistor matched pair layout

The matched transistor pair 210 will now be described_x,yExemplary transistor layouts of (a).

The inventors have recognized that the thickness/doping concentration/gradient in impurities of one or more semiconductor layers across a PUF cell may adversely affect the compositionally matched transistor pair 210_x,yThe randomness of the difference between the two transistors. For example, if the thickness of the gate oxide layer gradually increases across the die from one end to the other, the gate oxide thickness on one of the transistors may always be slightly greater than the other transistor. For example, referring to fig. 3, 6 and 9, if at each PUF cell 105_x,yHas a left-to-right increasing gradient of gate oxide thickness across the array of PUF cells, and is associated with each PUF cell 105_x,yEach PUF cell 105, as compared to the transistors on the right_x,yThe transistor on the left side is more likely to have a slightly thinner gate oxide. This may shift the likelihood of transistor comparison by 50:50, thereby causing one transistor to have a greater transistor on-state characteristic (e.g., V) than the other transistor_THOr V_GSOr I_D) The chance of (2) is no longer 50: 50.

it has been determined that the transistor pair 210 can be matched by_x,yDesigned to be as small and as close together as possible to minimize this effect. Furthermore, it has also been determined that a so-called "common centroid" arrangement can further improve gradient rejection, thereby increasing the likelihood that the transistor comparison is substantially 50: 50.

Fig. 10 shows a schematic diagram of an example transistor whose location helps to illustrate the placement of the "common centroid". In FIG. 10A, matched transistor pairs 210 are formed together_x,yFirst transistor T of_AAnd a second transistor T_BAre separated from each other by a long distance. In this case, matched transistor pair 210_x,yAre susceptible to gradient effects, particularly in the up/down direction of the figure. FIG. 10B shows a similar arrangement, but with a first transistor T_AAnd a second crystalBody tube T_BAre placed close to each other. This may help to reduce the effect of the fade, especially in the up/down direction of the graphics.

FIG. 10C shows an example "common centroid" arrangement. In this example, a first transistor T_ABy a first sub-transistor T_A1And a second sub-transistor T_A2And (4) forming. Second transistor T_BBy a third sub-transistor T_B1And a fourth sub-transistor T_B2And (4) forming. The first transistor T due to the positioning of the sub-transistors_AIs located at or in the centroid of the second transistor T_BOr substantially the same location of the centroid. Thus, for matched transistor pair 210_x,y PUF cell 105_x,yThe overall effect of any linear or first order gradient above should be equalized to achieve gradient suppression.

FIG. 10D shows another example "common centroid" arrangement. Third, the first transistor T is positioned due to the sub-transistors_AIs located at or in the centroid of the second transistor T_BOr substantially the same location of the centroid. Thus, for matched transistor pair 210_x,y PUF cell 105_x,yThe overall effect of any gradient above should be equalized to achieve gradient suppression.

Details of an example "common centroid" arrangement will now be described with reference to fig. 11-13.

FIG. 11A shows a matched transistor pair 210_x,yIs shown in the example of (a). This is a simplified representation of a part of the PUF device described above with reference to fig. 7. Matched transistor pair 210_x,yIs marked as T_AAnd the second transistor of the pair is marked T_B. A first transistor T_AIs marked as V_DaAnd a second transistor T is connected to_BIs marked as V_Db。

FIG. 11B shows how matched transistor pair 210 is implemented by sub-transistors_x,yIs shown in the example of (a). A first transistor T_AIncluding a first sub-transistor ST_A1And a second sub-transistor ST_A2. Second transistor T_BComprises thatThird sub-transistor ST_B1And a fourth sub-transistor ST_B2。

FIG. 12 shows the matched transistor pair 210 shown in FIG. 11B_x,yAn exemplary semiconductor layout of (1). Matched transistor pair 210_x,yAre arranged to have a common centroid configuration corresponding to that shown in fig. 10C. A doped well or back gate region (e.g., an n-type substrate for a p-type FET) is indicated by reference numeral 1110. First sub-transistor ST_A1Comprising a source contact S₁And drain contact D₁Each well region may be a highly doped well region within the semiconductor substrate (e.g., a p + well for a p-type FET). First sub-transistor ST_A1Further comprises a gate G_A1. Third sub-transistor ST_B1Comprising a source contact S₂And drain contact D₁Each of which may be a highly doped well region within the semiconductor substrate (e.g., a p + well for a p-type FET). Thus, it can be seen that the first and third sub-transistors share a drain contact D₁. Third sub-transistor ST_B1Further comprises a gate G_B1. Fourth sub-transistor ST_B2Comprising a source contact S₂And drain contact D₂Each well region may be a highly doped well region within the semiconductor substrate (e.g., a p + well for a p-type FET). Thus, it can be seen that the third and fourth sub-transistors share a source contact S₂. Fourth sub-transistor ST_B2Further comprises a gate G_B2. Second sub-transistor ST_A1Comprising a source contact S₃And drain contact D₂Each of which may be a highly doped well region within the semiconductor substrate (e.g., a p + well for a p-type FET). Thus, it can be seen that the second and fourth sub-transistors share a drain contact D₂. Second sub-transistor ST_A2Further comprises a gate G_A2。

By sharing the source and drain contacts in this manner, matched transistor pair 210 may be made_x,ySmaller while still achieving a common centroid layout. This not only helps to reduce/eliminate gradient effects, but also means that pairs of transistors 210 can be used_x,yThe PUF array is packed more densely, thereby reducing the size of the PUF device 100. For exampleThe semiconductor design shown in fig. 12 can be manufactured to the following dimensions:

x spacing is 1.66um

Y spacing is 3.6um

Area of 5.976um 2

Technological size 0.18um

Area of picture element (standardized as minimum size of process) 33.2F ^2

Since each PUF cell 105_x,yMay include only matched transistor pairs 210_x,yAnd thus each PUF cell 105_x,yIt is possible to achieve the dimensions determined above while also achieving a common centroid layout. This means that very small high density PUF arrays can be realized.

It should be noted that if a non-common centroid arrangement is used instead, the Y pitch may be halved and the PUF cell 105 obtained_x,yHalf the area. While such an arrangement would not have the benefits of a common centroid arrangement, it may result in a smaller, higher density array of PUFs.

Figure 13 shows how the transistor layout of figure 12 may be used to create a PUF cell 105_x,yAn exemplary representation of an array of (a). The PUF array shown in fig. 13 corresponds to the PUF array shown in fig. 9. It can be seen that adjacent pairs of transistors 210 in a column_x,yAre arranged to share a source contact. For example, transistor pair 210_x,ySecond sub-transistor ST in_A2Source contact and transistor pair 210_x,y+1First sub-transistor ST in_A1Is shared. This not only adds to the PUF cell 105_x,yAnd also reduces the current source 720 associated with each column_xThe number of interconnects required thereby simplifying manufacture and reducing wiring/via complexity. It should be understood that although in this example adjacent PUF cells 105_x,yShare the source contact, but in an alternative configuration (e.g., corresponding to the arrangement shown in fig. 3), they may instead share the drain contact. Thus, adjacent transistor pairs 210 in a column_x,yMay be arranged to share the channel contact of the source or drain.

In the figure12 and 13, the sub-transistors are arranged such that when the first transistor T is present_AWhen conducting current, the first sub-transistor ST_A1From the drain D in a first direction in the semiconductor₁To the source S₁. In the illustration shown in fig. 12, the first direction is shown as "up". Second sub-transistor ST_A2From the drain D in a second direction in the semiconductor₂To the source S₃The second direction is substantially opposite to the first direction. This second direction is shown as "downward" in the state shown in fig. 12. When the second transistor T is turned on_BWhen conducting current, the third sub-transistor ST_B1From D in a second direction₁To the source S₂And a fourth sub-transistor ST_B2From the drain D in a first direction₂To the source S₂Although it is understood that, in the alternative, the third sub-transistor ST_B1And a fourth sub-transistor ST_B2Can be switched so that the third sub-transistor ST_B1The channel current in the first direction, and the fourth sub-transistor ST_B2The channel current in (b) flows in the second direction.

By arranging the sub-transistors such that the channel currents in each of the sub-transistors constituting the transistor flow in substantially opposite directions, the effect of the gradient can be further eliminated, thereby improving the suppression of the gradient and thus the randomness of the transistor difference.

Fig. 12 and 13 show an example of how the sub-transistors may be arranged to achieve a common centroid, channel contact sharing and substantially opposite channel current directions, the sub-transistors may be arranged in different ways and still achieve some or all of these effects. For example, the arrangement may be different for different types of transistors (e.g., n-type or p-type, etc.), and/or they may be arranged in different concentric arrangements (e.g., the arrangement of fig. 10D).

Figure 17 shows a graphical representation of a method for determining a PUF output using a plurality of PUF cells. May be determined by the determination unit 170 and the PUF cell 105 disclosed above_x,yIs used to perform the method.

In S1710, e.g. by applying a voltage to one or more PUF cells 105_x,yApplies a selection potential to select one or more PUF cells 105_x,y. In some cases, one PUF cell 105105 may be selected at a time_x,yWhile in other cases, multiple PUF cells 105 may be selected at once_x,y(e.g., some or all of the PUF cells in a particular row of the array of PUF cells).

In S1720, for each selected PUF cell 105_x,yBased at least in part on the selected PUF cell 105_x,yMatched transistor pair 210 in (1)_x,yTo determine a transistor difference value indicative of the one or more PUF cells 105 selected_x,yMatched transistor pair 210 in (1)_x,yRandom manufacturing differences between.

Optionally, if there is another PUF cell 105_x,yStill to be selected and having a certain transistor difference, the method may return to S1710 to select that PUF cell 105_x,yThe corresponding transistor difference is then determined. For example, after determining the transistor difference for the previous row, it may move to the next row of the PUF array. Once all PUF cells 105 have been selected_x,yAnd their transistor differences are determined, the method may then proceed to S1730. Alternatively, for example, at all PUF cells 105_x,yWhere they can be selected and their transistor differences determined in a single iteration of S1710 and S1720, the method may always proceed directly from S1720 to S1730.

In S1730, a PUF output is determined based at least in part on the at least one determined transistor difference, as previously described.

The skilled person will readily appreciate that various changes or modifications may be made to the above described aspects of the present disclosure without departing from the scope of the present disclosure.

For example, although in all of the above disclosed aspects, each PUF cell 105_x,yComprising only matched transistor pairs210_x,yWhich simultaneously serve as a selection mechanism and a transistor to be compared to determine a transistor difference, in an alternative embodiment, the PUF cell 105_x,yMore than two transistors may be included. For example, they may include matched transistor pairs 210_x,yAnd one or more transistors configured as a selection mechanism.

FIG. 14 shows a selection transistor 1410 included_x,y Example PUF cell 105_x,yAs a selection mechanism. In this example, the transistor 1410 is selected_x,yTwo p-type FETs are included. The PUF cell 105 may be selected by applying a selection potential_x,yTo select PUF cell 105_x,yWherein the selection potential is sufficient to turn on the selection transistor 1410_x,yThe potential of (2). Any PUF cell 105 that is not selected at a particular time_x,yMay have a voltage applied to the select transistor 1410_x,ySo that the transistor 1410 is selected_x,yIs cut off. Thus, to determine the presence of a particular PUF cell 105_x,yApplies a selection potential to "select" (e.g., via selector circuit 420), and applies first and second signals, respectively, to the matched transistor pair 210_x,y(e.g., by a current source and/or selector circuit 420, or some other suitable circuit/unit). In the alternative, each PUF cell 105_x,yThere may be only a single select transistor, for example, coupled between the sources of matched transistor pair 210 and current source 720 in the arrangement shown in fig. 8. In addition, a selection transistor 1410 is provided_x,yMatched transistor pair 210 configured as a differential pair_x,yTaken together, it should be understood that select transistor 1410 is shown_x,yCan be matched with the matched transistor pair 210_x,yAny of the configurations of (e.g., in conjunction with fig. 2 or 4).

Selection transistor 1410_x,yTransistor pair with match 210_x,yThe same transistor type, so that the PUF cell 105_x,yAll having the same transistor type. This does not mean that they are all of the same design, but are all n-type or all p-type. Tong (Chinese character of 'tong')By doing so, the PUF cell 105_x,yMay be more densely packed, thereby reducing the overall size of the PUF device and also reducing the gradient problem described above.

The term "coupled" as used throughout this disclosure includes both direct and indirect connections between components, where one or more intermediate components may be present in the coupling.

The array of PUF cells disclosed herein may be of any size and shape, for example having only one row and a number of columns, and vice versa. Furthermore, although the present disclosure is generally in the context of an array of PUF cells, it should be understood that a plurality of PUF cells may be arranged in any suitable manner rather than in an array.