阅读说明：本技术 用于检测对集成电路的损伤的装置和方法 (Apparatus and method for detecting damage to an integrated circuit ) 是由 V·翰纳瑟卡兰 Q·周 L·K-A·马特 于 2018-12-07 设计创作，主要内容包括：各种特征涉及包括集成电路的试环。该试环位于该集成电路的周边周围。该试环包括第一端子、第二端子和第一电路元件,其中第一端子耦合到第一电路元件,并且第一电路元件耦合到第二端子,其中第一端子、第一电路元件和第二端子串联耦合在一起。(Various features relate to a test loop that includes an integrated circuit. The test ring is located around a periphery of the integrated circuit. The test ring includes a first terminal, a second terminal, and a first circuit element, wherein the first terminal is coupled to the first circuit element and the first circuit element is coupled to the second terminal, wherein the first terminal, the first circuit element, and the second terminal are coupled together in series.)

1. An apparatus, comprising:

a test ring around a perimeter of an Integrated Circuit (IC), the test ring further comprising:

a first terminal;

a second terminal; and

a first circuit element, wherein the first terminal is coupled to the first circuit element and the first circuit element is coupled to the second terminal, wherein the first terminal, the first circuit element, and the second terminal are coupled together in series.

2. The apparatus of claim 1, the first circuit element comprising a first resistor.

3. The apparatus of claim 2, wherein the first resistor is selected from the group consisting of: well resistors, polysilicon resistors, and metal resistors.

4. The apparatus of claim 2, further comprising:

a second resistor coupled in series with the first resistor, the first terminal, and the second terminal.

5. The apparatus of claim 4, further comprising:

the first resistor includes first and second metal pieces located on a first side and coupled to a first isolation region, the first and second metal pieces located over a substrate; and

the second resistor includes third and fourth metal pieces located at the first side and coupled to a second isolation region, the third and fourth metal pieces located over a substrate.

6. The apparatus of claim 5, wherein the first metal feature and the second metal feature are located above a doped region in a first well, and the third metal feature and the fourth metal feature are located above a doped region in a second well.

7. The apparatus of claim 1, the first circuit element comprising a first capacitor.

8. The apparatus of claim 7, wherein the first capacitor is selected from the group consisting of: junction capacitors, MOS capacitors, and metal capacitors.

9. The apparatus of claim 7, further comprising:

a second capacitor coupled in series with the first capacitor, the first terminal, and the second terminal.

10. The apparatus of claim 9, further comprising:

the first capacitor includes a first metal piece coupled to a first counter-doped region and a second metal piece coupled to a first isolation region, the first counter-doped region being located in the first isolation region; and

the second capacitor includes a third metal coupled to a second counter-doped region and a fourth metal coupled to a second isolation region, the second counter-doped region being located in the second isolation region, the first, second, third, and fourth metals being over a substrate of the IC.

11. The apparatus of claim 1, wherein the first circuit element is a passive device.

12. The apparatus of claim 1, the first circuit element comprising a first flip-flop.

13. The apparatus of claim 12, wherein the first trigger is selected from the group consisting of: S-R flip-flops, D flip-flops, T flip-flops, and JK flip-flops.

14. The apparatus of claim 1, wherein the first circuit element is integrated into the IC.

15. The apparatus of claim 1, wherein the apparatus is configured to couple to a tester integrated into the IC.

16. The apparatus of claim 15, wherein the tester comprises a signal generator, a measurement device, a comparator, logic, or memory, or a combination thereof.

17. The apparatus of claim 1, further comprising:

wherein the test ring comprises a measurable value;

wherein the trial loop comprises a reference value;

wherein the IC includes a crack if the measurable value is not substantially equal to the reference value.

18. The apparatus of claim 1, wherein the test ring is located in a seal ring located around a periphery of the IC.

19. The apparatus of claim 1, wherein the apparatus is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile phones, smart phones, personal digital assistants, fixed location terminals or servers, tablet computers, wearable computing devices, and laptop computers.

20. A method for detecting damage to an integrated circuit, comprising:

enabling a tester coupled to a test ring located at a periphery of an Integrated Circuit (IC), wherein the test ring includes a first circuit element coupled in series to a first terminal and a second terminal;

measuring a value with the tester;

comparing the measured value with a reference value; and

determining that there is damage to the IC if the measured value is not substantially equal to the reference value or determining that there is no damage to the IC if the measured value is substantially equal to the reference value.

21. The method of claim 20, further comprising:

wherein the first circuit element comprises a first resistor;

wherein the reference value is equal to an equivalent resistance of the first resistor;

wherein measuring the value comprises measuring a resistance between the first terminal and the second terminal, the resistance being the measured resistance; and

determining that damage to the IC is present if the measured resistance is not substantially equal to the equivalent resistance, or determining that damage to the IC is not present if the measured resistance is substantially equal to the equivalent resistance.

22. The method of claim 20, further comprising:

wherein the first circuit element comprises a first resistor;

wherein enabling the tester comprises applying a sinusoidal signal to the first terminal, the sinusoidal signal comprising a reference value amplitude;

wherein measuring the value comprises measuring a signal at the second terminal, the signal comprising the measured amplitude; and

determining that damage to the IC is present if the measured amplitude is not substantially equal to the reference value amplitude or determining that damage to the IC is not present if the measured amplitude is substantially equal to the reference value amplitude.

23. The method of claim 20, further comprising:

wherein the first circuit element comprises a first resistor;

wherein enabling the tester comprises coupling the first terminal to a ground signal and applying a reference current, the reference current flowing through the first resistor;

wherein the reference value is a reference value voltage equal to an equivalent resistance of the first resistor multiplied by the reference current;

wherein measuring the value comprises measuring a voltage at the second terminal, the voltage being the measured voltage; and

determining that there is damage to the IC if the measured voltage is not substantially equal to the reference value voltage, or determining that there is no damage to the IC if the measured voltage is substantially equal to the reference value voltage.

24. The method of claim 20, further comprising:

wherein the first circuit element comprises a first capacitor;

wherein the reference value is equal to an equivalent capacitance of the first capacitor; and is

Wherein measuring the value comprises measuring a capacitance between the first terminal and the second terminal, the capacitance being the measured capacitance; and

determining that damage to the IC is present if the measured capacitance is not substantially equal to the equivalent capacitance, or determining that damage to the IC is not present if the measured capacitance is substantially equal to the equivalent capacitance.

25. The method of claim 20, further comprising:

wherein the first circuit element is a first flip-flop;

wherein enabling the tester comprises setting the first flip-flop to a first reference value and applying a clock to the first flip-flop; and is

Wherein measuring the value comprises measuring a signal at the second terminal, the signal being the measured signal;

determining that damage to the IC is present if the measured signal is not substantially equal to the first reference value or determining that damage to the IC is not present if the measured signal is substantially equal to the first reference value.

26. The method of claim 25, further comprising:

a second flip-flop, wherein an input of the first flip-flop is coupled to the first terminal and an output of the first flip-flop is coupled to the second flip-flop, and wherein an output of the second flip-flop is coupled to the second terminal;

wherein enabling the tester comprises setting the second flip-flop to a second reference value and applying the clock to the second flip-flop; and is

Wherein the measured signal comprises a first bit and a second bit.

27. The method of claim 26, wherein the measured signal comprises an invalid bit value in the presence of damage to the IC, wherein the invalid bit value is an output of one of the first flip-flop or the second flip-flop that corresponds to a damaged location on the IC.

28. The method of claim 25, further comprising:

a rise-fall counter coupled to the second terminal;

wherein the second reference value is equal to a calculated value of the up-down counter;

wherein the measured signal comprises an output of the up-down counter; and

determining that damage to the IC is present if the output of the up-down counter is not substantially equal to the second reference value, or determining that damage to the IC is not present if the output of the up-down counter is substantially equal to the second reference value.

29. The method of claim 20, further comprising:

wherein the first circuit element is a first inverter;

wherein enabling the tester comprises applying a first bit to the first inverter;

wherein the reference value is an expected output of the second terminal;

wherein measuring the value comprises measuring a signal at the second terminal, the signal being the measured signal; and

determining that damage to the IC is present if the measured signal is not substantially equal to the reference value or determining that damage to the IC is not present if the measured signal is substantially equal to the reference value.

30. An apparatus, comprising:

a test ring around a perimeter of an Integrated Circuit (IC), the test ring further comprising:

a first terminal;

a second terminal;

a first means for detecting damage to the IC coupled in series with the first terminal and the second terminal.

31. The apparatus of claim 30, wherein the first means for detecting damage to the IC comprises a first resistor.

32. The apparatus of claim 30, wherein the first means for detecting damage to the IC comprises a first capacitor.

33. The apparatus of claim 30, wherein the first means for detecting damage to the IC comprises a first trigger.

34. The apparatus of claim 33, wherein the first means for detecting damage to the IC comprises means for determining a first damaged location of the IC.

35. The apparatus of claim 30, wherein the first means for detecting cracks in the IC comprises a first inverter.

Background

Integrated Circuits (ICs) are susceptible to mechanical damage during fabrication, such as during peeling of the carrier wafer, and during sawing or dicing. Mechanical damage can also occur during handling, shipping, roll-to-roll packaging, picking and placing surface mount devices on or near ICs, and during board bending. Wafer level packaging of ICs is also susceptible to mechanical damage due to lack of protection around the IC. Mechanical damage that occurs during pick-and-place of surface mount devices may not be detectable prior to phone level testing. Mechanical damage found during phone-level testing requires disassembly and reassembly of the phone components, which can be expensive.

Fig. 1 illustrates a top view of a conventional seal ring. Seal ring 102 is located around the periphery of IC100 and surrounds the circuitry (not shown) of IC 100. Seal ring 102 is integrated into IC100 and includes metal pieces (such as contacts and vias) (not shown) that are part of IC 100. The seal ring 102 prevents damage, such as cracking, to the IC100 that may be caused by mechanical or environmental stress (such as moisture).

Although seal ring 102 prevents damage to IC100, it does not detect whether IC100 is damaged (e.g., cracked) or not, nor does it provide information about where damage is located on IC 100. There is a need for a means of detecting whether the IC100 is damaged.

Disclosure of Invention

Various features relate to trial loops. In a first example, an apparatus comprises: a test ring around a periphery of an Integrated Circuit (IC). The test ring further includes a first terminal, a second terminal, and a first circuit element, wherein the first terminal is coupled to the first circuit element and the first circuit element is coupled to the second terminal, wherein the first terminal, the first circuit element, and the second terminal are coupled together in series.

In a second example, a method for detecting damage to an IC, comprising: enabling a tester coupled to a test ring located at a periphery of an Integrated Circuit (IC), the test ring including a first circuit element coupled in series to a first terminal and a second terminal; measuring a value with the tester; comparing the measured value with a reference value; and determining that damage to the IC is present if the measured value is not substantially equal to the reference value or determining that damage to the IC is not present if the measured value is substantially equal to the reference value.

In a third example, an apparatus comprises: a test ring around a perimeter of an Integrated Circuit (IC), the test ring further comprising a first terminal, a second terminal, a first means for detecting damage to the IC coupled in series with the first terminal and the second terminal.

Drawings

The various features, nature, and advantages of the detailed description set forth below will become apparent from the description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

Fig. 1 illustrates a top view of a conventional seal ring.

Fig. 2A illustrates a top view of an exemplary trial ring in an integrated circuit.

Fig. 2B illustrates a cross-section of the exemplary trial ring of fig. 2A.

Fig. 3A illustrates a top view of an exemplary trial ring in an integrated circuit.

Fig. 3B illustrates a cross-section of the trial ring of fig. 3A.

Fig. 4 illustrates a top view of an exemplary trial ring in an integrated circuit.

Fig. 5 illustrates a top view of an exemplary trial ring in an integrated circuit.

Fig. 6A illustrates an exemplary method for detecting damage to an integrated circuit.

Fig. 6B illustrates a tester for detecting damage to an IC.

Fig. 6C illustrates a structure for use with an exemplary method of detecting damage to an IC.

Fig. 7 illustrates various electronic devices that may include the various substrates, integrated devices, integrated device packages, semiconductor devices, dies, integrated circuits, packages, or inductors described herein.

Detailed Description

In the following description, specific details are given to provide a thorough understanding of various aspects of the disclosure. However, it will be understood by those of ordinary skill in the art that these aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the aspects in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the aspects of the disclosure.

Overview

Some features relate to a test ring formed around a periphery of an Integrated Circuit (IC). The test ring is integrated into the IC. The test ring may be positioned in a sealing ring located around the perimeter of the IC and may be used to detect damage to the IC (e.g., detect cracks). In one aspect, a test loop may be used to detect a first damaged location of an IC. The trial loop allows detection of damage to the IC even after the IC has been assembled into a final product (e.g., mobile device/phone, laptop, wearable). This results in cost savings as disassembly of the final product is avoided.

The test loop includes a circuit element (or more than one circuit element), where the circuit element may be a resistor, a capacitor, a flip-flop, or an inverter. A first terminal of the test ring is coupled to a first circuit element, and the first circuit element is coupled to a second terminal of the test ring. That is, the first and second terminals and the first circuit element are coupled together in series.

A method for detecting damage to an IC, comprising: enabling a tester coupled to a test ring located at a periphery of the IC; measuring a value with the tester; comparing the measured value with a reference value; and determining that the IC is damaged if the measured value is not substantially equal to the reference value or determining that the IC is not damaged if the measured value is substantially equal to the reference value.

The tester may be integrated into the IC (i.e., an integrated tester) or external to the IC (i.e., an external tester), and may include a signal generator, a measurement device, a comparator, logic, and memory for generating the reference value.

Exemplary test ring including passive circuit elements in an integrated circuit

Fig. 2A illustrates a top view of an exemplary trial ring in an IC. Specifically, fig. 2A illustrates a test ring 290 around the periphery of the IC 200, the test ring 290 being used to detect damage (such as cracks) to the IC 200. The test ring includes a plurality of circuit elements 222 coupled together in series with a first terminal 251 and a second terminal 252. The plurality of circuit elements 222 may be passive devices (a passive device is a device that does not require power to operate). In one aspect, the plurality of circuit elements 222 is a plurality of resistors 222a-p (e.g., a first means for detecting damage to an IC). The plurality of resistors 222a-p may be integrated into the IC 200 (see discussion regarding fig. 2B).

The test ring 290 is located in the seal ring 210 around the periphery of the IC 200. The seal ring 210 has a first side 210a, a second side 210b, a third side 210c, and a fourth side 210 d. Fig. 2A illustrates a first resistor 222A, a second resistor 222b, a third resistor 222c, and a fourth resistor 222d on the first side 210a of the seal ring 210, a fifth resistor 222e, a sixth resistor 222f, a seventh resistor 222g, and an eighth resistor 222h on the second side 210b of the seal ring 210, a ninth resistor 222i, a tenth resistor 222j, an eleventh resistor 222k, and a twelfth resistor 222l on the third side 210c of the seal ring 210, and a thirteenth resistor 222m, a fourteenth resistor 222n, a fifteenth resistor 222o, and a sixteenth resistor 222p on the fourth side 210d of the seal ring 210.

The plurality of resistors222a-p are coupled in series, with a first end of the first resistor 222a coupled to the first terminal 251, a second end of the first resistor 222a coupled to a first end of the second resistor 222b, a second end of the second resistor 222c coupled to a first end of the third resistor 222c, and so on, through a second end of a sixteenth resistor 222p coupled to the second terminal 252. The plurality of resistors 222a-p together form an equivalent resistance. The equivalent resistance of the series resistor may be obtained by adding the resistance values of each of the plurality of resistors 222 a-p. Accordingly, R_{Equivalence of}＝R_222a+R_222b+R_222c+R_222d+R_222e+R_222f+R_222g+R_222h+R_222i+R_222j+R_222k+R_222l+R_222m+R_222n+R_222o+R_222p. The equivalent resistance R will be discussed later with respect to FIG. 6A_{Equivalence of}The use of (1).

A total of sixteen resistors (of the plurality of resistors 222a-p), four on each side of the seal ring 210 (first side 210a, second side 210b, third side 210c, and fourth side 210d) are shown, although the disclosure is not so limited. More or fewer resistors may be used, and they may be distributed or spread across seal ring 210 in a different configuration than that shown in fig. 2A.

In one aspect, there may be a single resistor, such as first resistor 222 a. The first resistor 222a (and in this regard the only resistor) may be located on any of the first, second, third, or fourth sides 210a, 210b, 210c, 210d of the seal ring 210. On the other hand, the seal ring 210 may have only the first resistor 222a (i.e., the first circuit element) and the second resistor 222b (i.e., the second circuit element). In this regard, each or both of the first resistor 222a or the second resistor 222b may be located on the first side 210a, or the second side 210b, or the third side 210c, or the fourth side 210d of the seal ring 210. In another aspect, the plurality of resistors 222a-p can include sixteen resistors 222a-p, with two resistors (e.g., 222a, 222b) on the first side 210a of the seal ring 210, eight resistors (e.g., 222c-j) on the second side 210b of the seal ring 210, and six resistors (e.g., 222i-p) on the third side 210c of the seal ring 210. In this regard, there is no resistor on the fourth side 210d of the seal ring 210.

Fig. 2B illustrates a cross-section of trial ring 290 of fig. 2A, which includes a portion of IC 200. For clarity, only a portion of the IC 200 is shown. The IC 200 may have other layers not shown.

Specifically, fig. 2B illustrates the substrate 204. Substrate 204 is a p-type substrate. The substrate 204 includes the plurality of circuit elements 222, which include the plurality of resistors 222 a-p. For clarity, only the first resistor 222a and the second resistor 222b are shown. The first resistor 222a is formed by: a first metal 230a and a second metal 230b located on a first side of the substrate 204 and above the first isolation region 232 a. First isolation region 232a separates first metal piece 230a and second metal piece 230b, thereby creating first resistor 222a integrated into IC 200. It should be understood that the resistor 222a in fig. 2B is merely illustrative, i.e., the drawn resistor does not actually exist, but represents the resistance resulting from the structure shown in fig. 2B.

Similarly, the second resistor 222b is formed by: third and fourth metal pieces 230c and 230d located on the sides of the substrate 204 and above the second isolation region 232 b. Second isolation region 232b separates third metal piece 230c from second metal piece 230d, thereby creating second resistor 222b integrated into IC 200. It should be understood that the resistor 222B in fig. 2B is merely illustrative, i.e., the drawn resistor does not actually exist, but represents the resistance resulting from the structure shown in fig. 2B.

As previously mentioned, the first resistor 222a and the second resistor 222b are coupled in series. This is accomplished by coupling a second metal piece 230b (e.g., the second end of the first resistor 222 a) to a third metal piece 230c (e.g., the first end of the second resistor 222 b).

Although fig. 2B illustrates the substrate 204 as a p-type substrate and the first and second isolation regions 232a and 232B as n-well type isolation regions, the present disclosure is not limited thereto. Substrate 204 may be any type of substrate, such as an n-type substrate or a deep n-well substrate. Furthermore, the first and second isolation regions 232a, 232b may be any type of isolation region (such as a p-well or some other hybrid isolation region) such that an integrated resistor is formed. Further, the plurality of resistors 222a-p may be formed as well resistors, polysilicon resistors, or metal resistors.

Fig. 3A illustrates a top view of an exemplary trial ring in an IC. Specifically, fig. 3A illustrates a test ring 390 around the perimeter of the IC 300, the test ring 390 being used to detect damage (such as cracks) to the IC 300. The test loop 390 includes a plurality of circuit elements 322 coupled together in series with a first terminal 351 and a second terminal 352. The plurality of circuit elements 322 may be passive devices. In one aspect, the plurality of circuit elements 322 is a plurality of capacitors 322a-p (e.g., a first means for detecting damage to an IC). The plurality of capacitors 322a-p may be integrated into the IC 300, as will be explained later with respect to fig. 3B.

The test ring 390 is located in the seal ring 310 around the perimeter of the IC 300. The seal ring 310 has a first side 310a, a second side 310b, a third side 310c, and a fourth side 310 d. Fig. 3A illustrates a first capacitor 322a, a second capacitor 322b, a third capacitor 322c, and a fourth capacitor 322d on a first side 310a of the seal ring 310, a fifth capacitor 322e, a sixth capacitor 322f, a seventh capacitor 322g, and an eighth capacitor 322h on a second side 310b of the seal ring 310, a ninth capacitor 322i, a tenth capacitor 322j, an eleventh capacitor 322k, and a twelfth capacitor 322l on a third side 310c of the seal ring 310, and a thirteenth capacitor 322m, a fourteenth capacitor 322n, a fifteenth capacitor 322o, and a sixteenth capacitor 322p on a fourth side 310d of the seal ring 310.

The plurality of capacitors 322a-p are coupled in series, with a first end of the first capacitor 322a coupled to the first terminal 351, a second end of the first capacitor 322a coupled to a first end of the second capacitor 322b, a second end of the second capacitor 322c coupled to a first end of the third capacitor 322c, and so on, through a second end of the sixteenth capacitor 322p coupled to the second terminal 352. The plurality of capacitors 322a-p together form an array, etcAn effective capacitance. The equivalent capacitances of the capacitors are as follows: the reciprocal value of the equivalent capacitance is equal to the sum of the reciprocal capacitance values of each of the plurality of capacitors 322 a-p. Accordingly, 1/C_{Equivalence of}＝1/C_322a+1/C_322b+1/C_322c+1/C_322d+1/C_322e+1/C_322f+1/C_322g+1/C_322h+1/C_322i+1/C_322j+1/C_322k+1/C_322l+1/C_322m+1/C_322n+1/C_322o+1/C_322p. The equivalent capacitance C will be discussed later with respect to FIG. 6A_{Equivalence of}。

A total of sixteen capacitors (of the plurality of capacitors 322a-p) are shown, four capacitors on each side (first side 310a, second side 310b, third side 310c, and fourth side 310d) of the seal ring 310, although the disclosure is not so limited. More or fewer capacitors may be used and they may be distributed or spread across the seal ring 310 in a different configuration than that shown in fig. 3A.

In one aspect, there may be a single capacitor, such as the first capacitor 322 a. The first capacitor 322a (and the only capacitor in this regard) may be located on any of the first, second, third, or fourth sides 310a, 310b, 310c, 310d of the seal ring 310. On the other hand, the seal ring 310 may have only the first capacitor 322a (i.e., the first circuit element) and the second capacitor 322b (i.e., the second circuit element). In this regard, each or both of the first capacitor 322a or the second capacitor 322b may be located on the first side 310a, or the second side 310b, or the third side 310c, or the fourth side 310d of the seal ring 310. In another aspect, the plurality of capacitors 322a-p can include sixteen capacitors 322a-p, with two capacitors (e.g., 322a, 322b) on the first side 310a of the seal ring 310, eight capacitors (e.g., 322c-j) on the second side 310b of the seal ring 310, and six capacitors (e.g., 322i-p) on the third side 310c of the seal ring 310. In this regard, there is no capacitor on the fourth side 310d of the seal ring 310.

Fig. 3B illustrates a cross-section of the test ring 390 of fig. 3A, which includes a portion of the IC 200. For clarity, only a portion of the IC 300 is shown. The IC 300 may have other layers not shown.

Specifically, fig. 3B illustrates the substrate 304. Substrate 304 is a p-type substrate. The substrate 304 includes the plurality of circuit elements 322, which include the plurality of capacitors 322 a-p. For clarity, only the first and second capacitors 322a and 322b are shown. The substrate 304 includes a plurality of isolation regions 332, including a first isolation region 332a and a second isolation region 332 b. The plurality of isolation regions 332 may include a plurality of counter-doped regions including a first counter-doped region 334a and a second counter-doped region 334 b. In one aspect, the first and second isolation regions 332a and 332b are n-wells, while the first and second counter-doped regions 334a and 334b are P-type. The substrate 304 may have an isolation layer 336 over the top of the substrate 304.

The first capacitor 332a is formed by: a first metal piece 330a coupled to the first counter-doped region 334a through an isolation layer 336, and a second metal piece 330b coupled to the first isolation region 332a through the isolation layer 336. The first metal piece 330a is configured to operate as a first electrode of the capacitor 322a, while the second metal piece 330b is configured to operate as a second electrode of the first capacitor 322 a.

Similarly, the second capacitor 332a is formed by: a third metal piece 330c coupled to the second counter-doped region 334b through an isolation layer 336, and a fifth metal piece 330d coupled to the second isolation region 332b through an isolation layer 336. The third metal piece 330c is configured to operate as a first electrode of the second capacitor 322b, while the fourth metal piece 330d is configured to operate as a second electrode of the second capacitor 322 b.

As previously mentioned, the first capacitor 322a and the second capacitor 322b are coupled in series. This is accomplished by coupling a second metal piece 330b (e.g., the second end of the first capacitor 322 a) to a third metal piece 330c (e.g., the first end of the second capacitor 322 b). Although fig. 3B illustrates the first and second capacitors 322a and 322B as being formed in the substrate 304 as a p-type substrate, the first and second isolation regions 332a and 332B as n-well type isolation regions, and the first and second counter-doped regions 334a and 334B as being of a p-type, the disclosure is not limited thereto. The plurality of capacitors 322a-p may be formed as junction capacitors, MOS capacitors, or metal capacitors, as non-limiting examples. Furthermore, the first and second isolation regions 332a, 332b may be any type of isolation region (such as a p-well or some other hybrid isolation region) such that an integrated capacitor is formed.

Exemplary test ring including active circuit elements in an integrated circuit

Fig. 4 illustrates a top view of an exemplary trial ring in an IC. Specifically, fig. 4 illustrates a test ring 490 around the perimeter of the IC400, the test ring 490 being used to detect damage (such as cracks) to the IC 400. In addition, the test loop 490 is used to determine a first damage location (e.g., a first crack location) of the IC 400.

The test loop 490 includes a plurality of circuit elements 422 coupled together in series with a first terminal 451 and a second terminal 452. In one aspect, the plurality of circuit elements 422 are active devices (where the active devices require a power source to operate). In one aspect, the plurality of circuit elements 422 are a plurality of flip-flops 422a-h (e.g., a first means for detecting damage to the IC, e.g., a means for determining a first damaged location of the IC). The plurality of flip-flops 422a-h are integrated into the IC 400.

Test ring 490 is located in seal ring 410 around the perimeter of IC 400. The seal ring 410 has a first side 410a, a second side 410b, a third side 410c, and a fourth side 410 d. Fig. 4 illustrates a first flip-flop 422a and a second flip-flop 422b on the first side 410a of the seal ring 410, a third flip-flop 422c and a fourth flip-flop 422d on the second side 410b of the seal ring 410, a fifth flip-flop 422e and a sixth flip-flop 422f on the third side 410c of the seal ring 410, and a seventh flip-flop 422g and an eighth flip-flop 422h on the fourth side 410d of the seal ring 410.

The plurality of flip-flops 422a-h are coupled in series, with a first terminal (e.g., input D) of the first flip-flop 422a coupled to the first terminal 451, a second terminal (e.g., output Q) of the first flip-flop 422a coupled to a first terminal (e.g., input D) of the second flip-flop 422b, a second terminal (e.g., output Q) of the second flip-flop 422c coupled to a first terminal (e.g., input D) of the third flip-flop 422c, and so on through to a second terminal (e.g., output Q) of the eighth flip-flop 222h coupled to the second terminal 452. In addition, each of the plurality of flip-flops 422a-h receives a clock as an input.

A total of eight flip-flops (of the plurality of flip-flops 422a-h) are shown, two on each side (first side 410a, second side 410b, third side 410c, and fourth side 410d) of seal ring 410, although the disclosure is not so limited. More or fewer triggers may be used and they may be distributed or spread across the seal ring 410 in a different configuration than that shown in fig. 4.

In one aspect, there may be a single flip-flop, such as first flip-flop 422 a. The first trigger 422a (and in this regard the only trigger) may be located on any of the first, second, third, or fourth sides 410a, 410b, 410c, 410d of the seal ring 410. In another aspect, seal ring 410 may have only a first flip-flop 422a (i.e., a first circuit element) and a second flip-flop 422b (i.e., a second circuit element). In this aspect, each or both of the first trigger 422a or the second trigger 422b may be located on the first side 410a, or the second side 410b, or the third side 410c, or the fourth side 410d of the seal ring 410. In another aspect, the plurality of flip-flops 422 can include sixteen flip-flops 422a-p (not all shown), with two flip-flops (e.g., 422a, 422b) on the first side 410a of the seal ring 410, eight flip-flops (e.g., 422c-j) on the second side 410b of the seal ring 410, and six flip-flops (e.g., 422i-p) on the third side 410c of the seal ring 210. In this aspect, there is no trigger on the fourth side 410d of the seal ring 410.

The number of triggers (such as 422a-h) and their location on seal ring 410 may affect the accuracy in determining the location in seal ring 410. The shorter the distance between two adjacent flip-flops (e.g., 422a and 422b, or 422b and 422c, or 422g and 422h, etc.) in the plurality of flip-flops 422a-h, the more accurate the first damage location (e.g., first fracture location) of the IC400 may be determined.

In one aspect, where there is only a single trigger 422a in seal ring 410, damage (e.g., a crack) to IC400 may be determined, however the location of the damage may be anywhere on IC 400. On the other hand, seal ring 410 has only two triggers 422a and 422b equally spaced apart in seal ring 410. First flip-flop 422a corresponds to a first portion (i.e., a three-dimensional portion) of IC400, and second flip-flop 422b corresponds to a second portion (i.e., a three-dimensional portion) of IC 400. A first damaged location (e.g., crack) of the IC400 may be determined to be present in either the first portion or the second portion of the IC 400. On the other hand, in a case (not shown) where there are fifty flip-flops in the IC400, the first damaged location of the IC400 may be determined to occur between one of the fifty flip-flops (i.e., in one of the fifty regions of the IC corresponding to the fifty flip-flops), thereby increasing the higher accuracy in determining the crack location. A method of detecting a first damaged location of an IC (e.g., 400) will be described later with respect to fig. 6A.

Fig. 4 illustrates the plurality of flip-flops 422a-h as S-R type flip-flops. However, any type of flip-flop may be utilized. For example, T flip-flops, J-K flip-flops, or D flip-flops may be used instead. The plurality of circuit elements 422, such as the plurality of flip-flops 422a-h, may be integrated into the IC400 by methods such as integrated logic gates, such as AND, NOR, or NAND logic gates, or combinations (not shown). These integrated logic gates are connected in series as explained previously. Such integrated logic gates may be implemented in the substrate of IC400 using metal layers and isolation regions (not shown) including doped regions. The substrate (not shown) may be any type of substrate, such as an n-type or p-type substrate, and the isolation region (not shown) and the doped region may be any type (e.g., n-or p-type) so that a flip-flop may be formed.

Fig. 5 illustrates a top view of an exemplary trial ring. In particular, fig. 5 illustrates a test ring 590 around the perimeter of the IC 500, the test ring 590 being used to detect damage (such as cracks) to the IC 500. The test ring 590 includes a plurality of circuit elements 522 coupled together in series with a first terminal 551 and a second terminal 552. The plurality of circuit elements 522 may be active devices. In one aspect, the plurality of circuit elements 522 are a plurality of inverters 522a-h (e.g., a first means for detecting damage to the IC) integrated into the IC 500.

The test ring 590 is located in the seal ring 510 around the perimeter of the IC 500. Fig. 5 illustrates first and second inverters 522a, 522b on a first side 510a of the seal ring 510, third and fourth inverters 522c, 522d on a second side 510b of the seal ring 510, fifth and sixth inverters 522e, 522f on a third side 510c of the seal ring 510, and seventh and eighth inverters 522g, 522h on a fourth side 510d of the seal ring 510.

The plurality of inverters 522a-h are coupled in series, with a first terminal of the first inverter 522a coupled to the first terminal 551, a second terminal of the first inverter 522a (e.g., the output of the first inverter 522 a) coupled to a first terminal of the second inverter 522b (e.g., the input of the first inverter 522 a), a second terminal of the second inverter 522c coupled to a first terminal of the third inverter 522c, and so on through a second terminal of the eighth inverter 222h coupled to the second terminal 552. More capacitors or fewer capacitors may be used than illustrated in fig. 5, and they may be distributed or spread across the seal ring 510 in a different configuration than that shown in fig. 5. In one aspect, the seal ring 510 may have only the first inverter 522 a. On the other hand, the seal ring 510 may have only the first inverter 522a and the second inverter 522 b.

The plurality of circuit elements 522, such as the plurality of inverters 522a-h, may be integrated into the IC 500, including the substrate, metal layers, and isolation regions (not shown) including doped regions of the IC 500. The substrate (not shown) may be any type of substrate, such as an n-type or p-type substrate, and the isolation region (not shown) and the doped region may be any type (e.g., n-or p-type) so that an inverter may be formed.

Exemplary method for detecting damage in an integrated circuit with an exemplary test loop

Fig. 6A illustrates an exemplary method for detecting damage (e.g., cracks) in an IC. It should be noted that for clarity and simplicity, in some instances, several steps have been combined into a single step. Fig. 6B illustrates a tester 610 for detecting damage (e.g., cracks) to an IC (e.g., 200, 300, 400, or 500).

In one aspect, tester 610 is an external tester, i.e., a tester that is not integrated into the IC (e.g., IC 200, 300, 400, or 500). In this regard, a first terminal (e.g., 251, 351, 451, or 551) and a second terminal (e.g., 252, 352, 452, or 552) may be coupled to an interconnect (e.g., a solder ball, a post) of the IC (e.g., 200, 300, 400, or 500). In another aspect, tester 610 is an integrated tester, i.e., integrated into or onto the IC. Regardless of whether tester 610 is an external tester or an integrated tester, tester 610 is coupled to a test ring (e.g., 290, 390, 490, or 590) located at the periphery of the integrated circuit (e.g., 200, 300, 400, or 500). Tester 610 in fig. 6B may include components such as a signal generator 612, a measurement device 614, a comparator 616, logic 618, and memory 619. Although these components are shown separately in FIG. 6B, the components may be combined or omitted (e.g., if the functions of the components are performed manually, the components may be omitted from the tester 610).

In some aspects, the signal generator 612 may be a clock, a sinusoidal signal generator, or a digital signal generator. The measurement device 614 is configured to measure a value (i.e., a measured value), such as a resistance, a voltage, or a pattern. The memory 619 is configured to store a reference value, which may be a resistance, a voltage, or a pattern. The comparator 616 is configured to compare the measured value with a reference value. Logic 618 is configured to determine whether there is damage (e.g., a crack) to the IC. In one aspect, if the measured value is not substantially equal to the reference value, logic 618 may determine that a crack is present. On the other hand, if the measured value is substantially equal to the reference value, logic 618 may determine that no crack is present. Logic 618 may be a circuit or an algorithm.

Devices such as tester 610, measurement device 614, and other devices for measurement (e.g., voltmeters, multimeters, etc.) have a tolerance range, i.e., a permissible error range. For example, such devices may have a tolerance range of approximately ± 1%. It should be understood that the term "substantially" as used in the context of substantially equal or non-substantially equal includes the permissible range of error.

Returning to the method 600 of FIG. 6A, at step 602, the method includes enabling a tester 610. Enabling tester 610 may include: the reference value is stored in the memory 619. At step 604, the method includes measuring a value (i.e., measured value), such as a resistance, voltage, or pattern, with the tester 610. At step 606, the method includes comparing the measured value to a reference value. At step 608, the method includes: determining that damage to the IC is present if the measured value is not substantially equal to the reference value, or determining that damage to the IC is not present if the measured value is substantially equal to the reference value. In the following discussion, the method 600 is discussed in further detail with respect to the illustrations in fig. 2, 3, 4, and 5.

For the test loop 290 illustrated in fig. 2A, enabling the tester 610 (step 602) includes: the measurement device 614 is coupled to the first terminal 251 and the second terminal 252 of the trial ring 290, and one of the first terminal 251 or the second terminal 252 is coupled to ground. In one aspect, the enablement tester 610 may also include: the reference value is stored in the memory 619. However, it is not necessary to store the reference values in memory 619, such as in the case where tester 610 is an external tester and the test is performed manually. For trial loop 290 (of FIG. 2A), the reference value is the equivalent resistance (R) of the plurality of resistors (such as 222A-p)_{Equivalence of}). Measuring values (i.e., measured values) with tester 610 (step 604) includes: the resistance across the first terminal 251 and the second terminal 252 is measured. The measurements may be made using the measurement device 614 or alternatively using other known methods or devices. Comparing the measured value with a reference value (e.g., R)_{Equivalence of}) The comparison (step 606) may be performed using comparator 616.

For step 608, logic 618 or other known method or device may be used to determine when the measured value is not substantially equal to the reference value (e.g., R)_{Equivalence of}) Determine that there is damage to the IC 210, or where the measured value is approximately equal to a reference value (e.g., aSuch as R_{Equivalence of}) Determines that there is no damage to the IC 210. In one aspect of the IC 210 being damaged (e.g., the IC 210 breaking), the measured values will be infinite, as a crack in the IC 210 will constitute an electrical open circuit in the plurality of resistors 222a-p coupled in series. Accordingly, the measured value will not be substantially equal to the reference value (e.g., R)_{Equivalence of}) And logic 618 will determine that IC 210 is damaged. In another aspect where the IC 210 is not damaged, the measured value will be approximately equal to the reference value (e.g., R)_{Equivalence of}) And logic 618 will determine that IC 210 is not damaged.

In another aspect related to test loop 290, tester 610 is an external tester (i.e., located external to the IC). As part of enabling the tester 610 (step 602), a sinusoidal signal is generated and applied to the first terminal 251 using the signal generator 612. The sinusoidal signal includes a reference value amplitude (i.e., a reference value). Measuring (step 604) with the tester 610 includes: the signal at the second terminal 252, which includes the measured amplitude (i.e., the measured value), is measured using the measurement device 614. Comparing (step 606) the measured value with a reference value comprises: a comparator 616 is used to compare a reference value (i.e., a reference value amplitude) with a measured value (i.e., a measured amplitude).

If the measured amplitude is not substantially equal to the reference amplitude, then it will be determined that damage to the IC 210 is present (step 608). Alternatively, if the measured amplitude is approximately equal to the reference amplitude, it will be determined that there is no damage to the IC 210 (step 608).

In another aspect (with respect to test ring 290), tester 610 is an integrated tester (i.e., integrated into the IC). Fig. 6C illustrates a structure for use with an exemplary method 600 of detecting damage to an IC. The enable tester 610 includes: coupling the first terminal 251 to a ground signal 650 and the second terminal 252 to a known voltage source (V)_dd)670, and applying a reference current (I)_ref)672，I_ref672 flow through the plurality of resistors, such as 222 a-p. The reference value being equal to the equivalent resistance R_{Equivalence of}Multiplied by the reference value voltage of the reference current. The value is measured (i.e., measured) with the tester (step 60)4) The method comprises the following steps: the voltage at the second terminal 252 (measured voltage) is measured.

Comparing (step 606) the measured value with a reference value comprises: the voltage measured at the second terminal 252 is compared to a reference value voltage. Step 606 may be performed by comparator 616. If the voltage measured at the second terminal 252 is not substantially equal to the reference value voltage (step 608), then there is damage to the IC 210. If the voltage measured at the second terminal 252 is substantially equal to the reference value voltage (step 608), then there is no damage to the IC 210. Step 608 may be performed by logic 618.

For the test loop 390 illustrated in fig. 3A, enabling the tester 610 (step 602) includes: the measurement device 614 is coupled to a first terminal 351 and a second terminal 352 of the test ring 390. In one aspect, the enablement tester 610 may also include: the reference value is stored in the memory 619. However, it is not necessary to store the reference value in the memory 619. The reference value for the test loop 390 (of FIG. 3A) is the equivalent capacitance C of the plurality of capacitors (such as 322a-p)_{Equivalence of}. Measuring values (i.e., measured values) with tester 610 (step 604) includes: the capacitance (i.e., the measured capacitance) across the first terminal 351 and the second terminal 352 is measured. The measurements may be made using the measurement device 614 or other known methods or devices. Comparing the measured value with a reference value (e.g., C)_{Equivalence of}) The comparison (step 606) may be performed using comparator 616 or other known methods or devices.

For step 608, logic 618 or other known method or device may be used to determine when the measured capacitance is not substantially equal to a reference value (e.g., C)_{Equivalence of}) Determine the presence of damage (e.g., a crack) to the IC 310 or that the measured capacitance is approximately equal to a reference value (e.g., C)_{Equivalence of}) Determines that there is no damage to the IC 310. In one aspect of the IC 310 being damaged (e.g., cracked), the measured value will reflect an electrical open in the plurality of capacitors 322a-p coupled in series. Accordingly, the measured value will not be approximately equal to the reference value (e.g., C)_{Equivalence of}) And logic 618 will determine that IC 310 is damaged. In another aspect where the IC 310 is not damaged, the measured value will be approximately equal to the reference value (e.g., theE.g. C_{Equivalence of}) And logic 618 will determine that IC 310 is not damaged.

For the test loop 490 illustrated in fig. 4, enabling the tester 610 (step 602) includes: a first terminal 451 is coupled to the signal generator 612 and a second terminal 452 is coupled to the measurement device 614. The signal generator 612 may generate a clock signal that is received as input by each of the plurality of flip-flops 422 a-h. In addition, the enablement tester 610 further includes: each of the plurality of flip-flops 422a-h is initialized to a reference value. The reference value may be chosen to be any value desired. In one aspect, the reference value may have 8 bits, one for each of the eight flip-flops of the plurality of flip-flops 422 a-h. For purposes of this discussion, the following reference values will be used: 10101010 (i.e., 8 bits).

Initializing each of the plurality of flip-flops 422a-h to a reference value is performed by setting the S or R input of each of the plurality of flip-flops 422 a-h. According to the known operation of an S-R type flip-flop, if the S input is set to 1, the output of the flip-flop will be 1, and if the R input is set to 1, the output of the flip-flop (which is reset) will be 0. Accordingly (as part of enabling tester 610): the first flip-flop 422a may have its S input set to 1, the second flip-flop 422b may have its R input set to 1, the third flip-flop 422c may have its S input set to 1, the fourth flip-flop 422d may have its R input set to 1, the fifth flip-flop 422e may have its S input set to 1, the sixth flip-flop 422f may have its R input set to 1, the seventh flip-flop 422g may have its S input set to 1, and the eighth flip-flop 422h may have its R input set to 1. In this manner, the plurality of flip-flops 422a-h are each initialized to 10101010 (i.e., the opposite value mode).

The reference value 10101010 may be stored in the memory 619 or, if the tester 610 is an external tester and the test is performed manually, the reference value need not be stored in the memory.

Measuring values ("measured values") with tester 610 (step 604) includes: the signal received at the second terminal 452 (measured signal) is measured. The measured signal may include at least one bit for each of the plurality of flip-flops 422 a-h. The measured signal includes an invalid bit value if there is damage to the IC. The measurements may be made using the measurement device 614 or other known methods or devices. Comparing (step 606) the measured value to a reference value (e.g., 10101010) may be accomplished with comparator 616.

Determining that damage (e.g., a crack) to the IC400 is present if the measured value is not substantially equal to the reference value (e.g., 10101010), or determining that damage to the IC400 is not present if the measured value is substantially equal to the reference value (e.g., 10101010) may be performed by the logic 618 or other method or device. In one aspect where IC 410 is intact, the measured value will be approximately equal to the reference value (e.g., 10101010), and logic 618 will determine that IC400 is intact. On the other hand, if the IC400 were damaged, the damage or crack in the IC400 would constitute an electrical open in the plurality of flip-flops 422a-h, and the measured value would not be approximately equal to the reference value.

It should be appreciated that since each of the flip-flops 422a-h is initialized, even if the IC400 is damaged, the measured value up to the point of damage will be approximately equal to the reference value. For example, if the IC400 is cracked between the fifth flip-flop 422e and the sixth flip-flop 422f (as shown in fig. 4), the measured value will be "xxxxxx 010," where these xs are invalid bit values. Thus, even though in this example, the sixth flip-flop 422f would not be able to successfully receive the signal from the fifth flip-flop 422e, the sixth flip-flop 422f would output its original initialization value of "0" (i.e., the first 0 of the measured values of "xxxxxx 010"). Likewise, the seventh flip-flop 422g will output its original initialization value of "1" (i.e., the first 1 of the measured values "xxxxxx 010") and the eighth flip-flop 422f will output its original initialization value of "0" (i.e., the last bit of the measured values "xxxxxx 010"). The first invalid bit value is the output of one of the plurality of flip-flops 422a-h that corresponds to the first damaged location of the IC.

Test loop 490 may be used to determine a first damaged location of IC 400. As previously discussed, each of the plurality of flip-flops 422a-h corresponds to each of the eight bits of the reference value (e.g., 10101010), respectively. Accordingly, the first corrupted location of the IC400 corresponds to a region near the output of the flip-flop that outputs the first invalid bit value (i.e., one of the plurality of flip-flops 422 a-h). Continuing with the previous example, if the reference value is "10101010" and the measured value is "xxxxxx 010," then the first corrupted location of the IC400 occurs after the fifth flip-flop 422f because it is the fifth flip-flop that outputs the first invalid bit value.

In another aspect where tester 610 is an integrated tester, a method for detecting damage 600 may include the following steps. A up-down counter (not shown) may be coupled to the second terminal 452. The up-down counter may be part of the measurement device 614 of the tester 610. At step 602, the tester is enabled by: initializing the up-down counter to zero, applying a number of clock cycles to the trial loop 490, where the number of clock cycles is equal to the number of flip-flops (e.g., eight clock cycles would apply if there were eight flip-flops 422a-h), and initializing each of the flip-flops 422a-h such that all S inputs are 1 and all R inputs are 1 (as previously discussed). Measuring (step 604) with the tester 610 includes: the up-down counter is used to count up 1 if the tester 610 receives a 1 from the second terminal 452 and to count down 1 (i.e., subtract 1) if the tester receives a 0 from the second terminal 452. In other words, the measured value is the output of the up-down counter.

At step 606, the measured value is compared to a reference value. In one aspect where the plurality of flip-flops are initialized to 10101010, the reference value may be equal to 0 (i.e., 1-1+1-1+1-1 ═ 0). In other words, the reference value is a value of the up-down counter that is calculated based on the number of flip-flops (e.g., the plurality of flip-flops 422a-h has 8 flip-flops). At step 608, it is determined that there is no damage to the IC if the value measured at the up-down counter is substantially equal to a reference value (e.g., 0). At step 608, it is determined that there is damage to the IC if the value measured at the up-down counter is not substantially equal to the reference value of 0. Returning to the previous example where there was damage to the IC400 after the fifth flip-flop 422e, the measured value would equal "-1" (i.e., -1+ 1-1). Thus, the method 600 will determine that there is damage to the IC because the measured value "-1" is not equal to the reference value "0".

For the test loop 590 illustrated in fig. 5, enabling the tester 610 (step 602) includes: a first terminal 551 is coupled to the signal generator 612 and a second terminal 552 is coupled to the measurement apparatus 614. As part of enabling the tester 610, a "0" may be applied by the signal generator 612 at the first terminal 551. By applying a "0", the desired output of the second terminal is obtained. By way of example, by applying a "0" to the first inverter 510a, the expected output (i.e., the reference value) of the second terminal is 10101010 (one bit per inverter). The reference value may optionally be stored in memory 619.

Measuring values ("measured values") with tester 610 (step 604) includes: the signal at the second terminal 552 is measured. The measurements may be made using the measurement device 614 or other known methods or devices. Comparing (step 606) the measured value to a reference value (e.g., 10101010) may be accomplished with comparator 616.

Logic 618 or other known methods or devices may be used to determine that damage is present to IC 500 if the measured value is not substantially equal to the reference value (e.g., 10101010), or that damage is not present to IC 500 if the measured value is substantially equal to the reference value (e.g., 10101010). If the IC 500 is damaged, the damage or crack will constitute an electrical open in the plurality of inverters 522a-h coupled in series. Accordingly, the measured value will not be substantially equal to the reference value (e.g., 10101010), and the logic 618 will determine that the IC 500 is compromised.

Exemplary electronic device

Fig. 7 illustrates various electronic devices that may be integrated with any of the aforementioned substrates, integrated devices, semiconductor devices, integrated circuits, dies, interposers, or packages. For example, mobile phone device 702, laptop computer device 704, fixed location terminal device 706, wearable device 708 may include an integrated apparatus 700 as described herein. The integrated device 700 may be, for example, any of a substrate, an integrated circuit, a die, an integrated device package, an integrated circuit device, a device package, an Integrated Circuit (IC) package, a package-on-package device described herein. The devices 702, 704, 706, 708 illustrated in fig. 7 are merely exemplary. Other electronic devices may also feature integrated device 700, such electronic devices including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, hand-held Personal Communication Systems (PCS) units, portable data units such as personal digital assistants, Global Positioning System (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smart phones, tablet computers, wearable devices (e.g., watches, glasses), internet of things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the various components, processes, features, and/or functions illustrated in fig. 2A-6B may be rearranged and/or combined into a single component, process, feature, or function or implemented in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from this disclosure. It should also be noted that fig. 2A-6B and their corresponding description in the present disclosure are not limited to substrates. In some implementations, fig. 2A-6B and their corresponding descriptions may be used to fabricate, create, provide, and/or produce integrated devices. In some implementations, a device may include a die, an integrated device, a die package, an Integrated Circuit (IC), a device package, an Integrated Circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, and/or an interposer.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object a physically contacts object B, and object B contacts object C, objects a and C may still be considered to be coupled to each other even though they are not in direct physical contact with each other. The term "pass through" as used herein means to pass through, and includes passing through an object in whole or in part.

It is also noted that the various disclosures contained herein may be described as a process which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed. Various features of the present disclosure described herein may be implemented in different systems without departing from the disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the disclosure is intended to be illustrative, and not to limit the scope of the claims appended hereto. As such, the teachings of the present invention are readily applicable to other types of apparatuses and many alternatives, modifications, and variations will be apparent to those skilled in the art.