阅读说明：本技术 延迟电路和相位插值器 (Delay circuit and phase interpolator ) 是由 朴智焕 文峻一 尹炳国 朴明宰 于 2020-10-09 设计创作，主要内容包括：本公开涉及一种延迟电路和相位差值器。该延迟电路包括第一延迟线路,该第一延迟线路适用于以基于延迟控制代码而被调节的延迟值,来延迟第一时钟；延迟控制电路,该延迟控制电路适用于将通过该第一延迟线路而被延迟的第一时钟的相位与第二时钟的相位进行比较,以生成该延迟控制代码；以及第二延迟线路,该第二延迟线路基于延迟控制代码而具有对应于第一延迟线路的延迟值的一半的延迟值。(The present disclosure relates to a delay circuit and a phase difference device. The delay circuit includes a first delay line adapted to delay a first clock by a delay value adjusted based on a delay control code; a delay control circuit adapted to compare a phase of a first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having a delay value corresponding to half of the delay value of the first delay line based on the delay control code.)

1. A delay circuit, comprising:

a first delay line adapted to delay the first clock by a delay value adjusted based on the delay control code;

a delay control circuit adapted to compare a phase of the first clock delayed by the first delay line with a phase of a second clock to generate the delay control code; and

a second delay line having a delay value corresponding to half of a delay value of the first delay line based on a delay control code.

2. The delay circuit of claim 1, wherein the delay control circuit is adapted to increase or decrease a code value of the delay control code according to a result of the phase comparison.

3. The delay circuit of claim 1, wherein the first delay line comprises:

a first variable delay having a delay value that is adjusted based on the delay control code; and

a second variable delay coupled in series to the first variable delay and having the same configuration of elements as the first variable delay,

wherein the second delay line includes a third variable delay having the same configuration of elements as the first variable delay.

4. The delay circuit of claim 1, wherein the first delay line includes a first variable delay having a delay value that is adjusted based on the delay control code,

wherein the second delay line comprises:

a code value converter adapted to halve a code value of the delay control code to generate a half-delay control code; and

a second variable delay having a delay value adjusted based on the half-delay control code and having the same element configuration as the first variable delay.

5. The delay circuit of claim 1, wherein the delay control code comprises N delay control signals,

wherein the first variable delay comprises N delay paths and one of the N delay paths is selected by the N delay control signals,

wherein the second variable delay comprises N/2 delay paths, and one of the N/2 delay paths is selected by half of the N delay control signals.

6. The delay circuit of claim 5, wherein the other half of the delay control signal that is not used when the second variable delay selects the delay path is used to adjust loading of variable delays.

7. A phase interpolator, comprising:

a first delay line adapted to delay the first clock by a delay value adjusted based on the delay control code;

a delay control circuit adapted to compare a phase of the first clock delayed by the first delay line with a phase of a second clock to generate the delay control code; and

a second delay line adapted to delay the first clock by a delay value corresponding to half of a delay value of the first delay line based on the delay control code to generate a phase interpolation clock.

8. The phase interpolator of claim 7, wherein the delay control circuit is adapted to increase or decrease a code value of the delay control code based on a result of the phase comparison.

9. The phase interpolator of claim 7, wherein the first delay line comprises:

a first variable delay having a delay value that is adjusted based on the delay control code; and

a second variable delay coupled in series to the first variable delay and having the same configuration of elements as the first variable delay,

wherein the second delay line includes a third variable delay having the same configuration of elements as the first variable delay.

10. The phase interpolator of claim 7, wherein the first delay line includes a first variable delay having a delay value that is adjusted based on the delay control code,

wherein the second delay line comprises:

a code value converter adapted to halve a code value of the delay control code to generate a half-delay control code; and

a second variable delay having a delay value adjusted by the half-delay control code and having the same element configuration as the first variable delay.

11. The phase interpolator of claim 7, wherein the delay control code comprises N delay control signals,

wherein the first variable delay comprises N delay paths and one of the N delay paths is selected by the N delay control signals,

wherein the second variable delay comprises N/2 delay paths, and one of the N/2 delay paths is selected by half of the N delay control signals.

12. The phase interpolator of claim 7, wherein the other half of the delay control signal that is not used when the second variable delay selects the delay path is used to adjust loading of variable delays.

13. A phase interpolator, comprising:

a first delay line adapted to delay the first input clock by a delay value adjusted based on the delay control code;

a delay control circuit adapted to compare a phase of the first input clock delayed by the first delay line with a phase of a second input clock to generate the delay control code;

a first driver adapted to output the first input clock delayed by the first delay line as a first output clock;

a first synthesizer adapted to synthesize the first input clock delayed by the first delay line and the second input clock to drive a first node with the synthesized clock;

a second delay line adapted to delay the synthesized clock of the first node by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to output the delayed clock as a second output clock;

a second driver adapted to transmit the second input clock to a second node; and

a third delay line adapted to delay the clock of the second node by a delay value that is adjusted based on the delay control code and that is equal to the delay value of the first delay line to output the delayed clock as a third output clock.

14. The phase interpolator of claim 13, further comprising:

a fourth delay line adapted to delay the second input clock by a delay value that is adjusted based on the delay control code and is equal to the delay value of the first delay line;

a second synthesizer adapted to synthesize the second input clock and a third input clock delayed through the fourth delay line to drive a third node with the synthesized clock;

a fifth delay line adapted to delay the synthesized clock of the third node by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to output the delayed clock as a fourth output clock;

a third driver adapted to transmit the third input clock to a fourth node; and

a sixth delay line adapted to delay the clock of the fourth node by a delay value that is adjusted based on the delay control code and that is equal to the delay value of the first delay line to output the delayed clock as a fifth output clock.

15. The phase interpolator of claim 14, further comprising:

a seventh delay line adapted to delay the third input clock by a delay value that is adjusted based on the delay control code and that is equal to the delay value of the first delay line;

a third synthesizer adapted to synthesize the third input clock and the fourth input clock delayed by the seventh delay line to drive a fifth node with the synthesized clock;

an eighth delay line adapted to delay the synthesized clock of the fifth node by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to output the delayed clock as a sixth output clock;

a fourth driver adapted to transmit the fourth input clock to a sixth node; and

a ninth delay line adapted to delay the clock of the sixth node by a delay value that is adjusted based on the delay control code and is equal to the delay value of the first delay line to output the delayed clock as a seventh output clock.

16. The phase interpolator of claim 15, further comprising:

a tenth delay line adapted to delay the fourth input clock by a delay value that is adjusted based on the delay control code and is equal to the delay value of the first delay line;

a fourth synthesizer adapted to synthesize the fourth input clock delayed by the tenth delay line and the first input clock to drive a seventh node with the synthesized clock;

an eleventh delay line adapted to delay the synthesized clock of the seventh node by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to output the delayed clock as an eighth output clock.

17. The phase interpolator of claim 13, wherein the delay control circuit is adapted to increase or decrease a code value of the delay control code based on a result of the phase comparison.

18. A method of phase interpolation, comprising:

delaying the first input clock by a delay value adjusted based on the delay control code;

comparing the delayed phase of the first input clock with the phase of a second input clock to generate the delay control code, the delay control code configured to bring the first and second input clocks in phase;

synthesizing the delayed first input clock and the second input clock to output a synthesized clock;

delaying the synthesized clock by a delay value corresponding to half of a delay value of the first input clock based on the delay control code to output a delayed synthesized clock;

delaying the second output clock by a delay value equal to a delay value of the first input clock based on the delay control code.

Technical Field

Various embodiments relate to a delay circuit and a phase interpolator.

Background

In general, phase interpolators are used to generate clocks having various phases in various integrated circuits. The phase interpolator receives a plurality of clocks having different phases and synthesizes the received clocks, thereby generating an output clock having an intermediate phase between phases of the received clocks.

Fig. 1 is a diagram illustrating a conventional phase interpolator 100 and its operation.

Referring to fig. 1, the phase interpolator 100 may include inverters 101 and 102 for transmitting a first input clock CLKA _ IN, inverters 106 and 107 for transmitting a second input clock CLKB _ IN, and inverters 103 to 105 for synthesizing the first and second input clocks CLKA _ IN and CLKB _ IN.

Fig. 1 shows that the first input clock CLKA _ IN and the second input clock CLKB _ IN have a phase difference "dT" therebetween, and the interpolated output clock CLKAB _ OUT output from the phase interpolator 100 has an intermediate phase between the first output clock CLKA _ OUT and the second output clock CLKB _ OUT. This is because the interpolated output clock CLKAB _ OUT is generated by fusing analog components of the periods IN which the first input clock CLKA _ IN and the second input clock CLKB _ IN transition.

When the phase difference "dT" between the first input clock CLKA _ IN and the second input clock CLKB _ IN is large, the period of the first input clock CLKA _ IN transition and the period of the second input clock CLKB _ IN transition do not overlap with each other. IN this case, it is important to synthesize analog components of the two clocks CLKA _ IN and CLKB _ IN. Therefore, when the two clocks CLKA _ IN and CLKB _ IN to be synthesized are low frequency clocks, it is impossible to perform phase interpolation using the conventional phase interpolator 100 of fig. 1.

Disclosure of Invention

Various embodiments are directed to a phase interpolator capable of generating an intermediate phase clock between a plurality of clocks having a phase difference therebetween.

In one embodiment, a delay circuit may include: a first delay line adapted to delay the first clock by a delay value adjusted based on the delay control code; a delay control circuit adapted to compare a phase of a first clock delayed by a first delay line with a phase of a second clock to generate a delay control code; and a second delay line having a delay value corresponding to half of the delay value of the first delay line based on the delay control code.

In one embodiment, a phase interpolator may include: a first delay line adapted to delay the first clock by a delay value adjusted based on the delay control code; a delay control circuit adapted to compare a phase of a first clock delayed by a first delay line with a phase of a second clock to generate a delay control code; and a second delay line adapted to delay the first clock by a delay value corresponding to half of a delay value of the first delay line based on a delay control code to generate a phase interpolation clock.

In one embodiment, a phase interpolator may include: a first delay line adapted to delay the first input clock by a delay value adjusted based on the delay control code; a delay control circuit adapted to compare a phase of a first input clock delayed through a first delay line with a phase of a second input clock to generate a delay control code; a first driver adapted to output a first input clock delayed by a first delay line as a first output clock; a first synthesizer adapted to synthesize the first input clock delayed through the first delay line and the second input clock to drive the first node with the synthesized clock; a second delay line adapted to delay the synthesized clock of the first node by a delay value corresponding to half of the delay value of the first delay line based on the delay control code to output the delayed clock as a second output clock; a second driver adapted to transmit a second input clock to a second node; and a third delay line adapted to delay the clock of the second node by a delay value that is adjusted based on the delay control code and is equal to the delay value of the first delay line, to output the delayed clock as a third output clock.

In one embodiment, a method of phase interpolation may include: delaying the first clock by a delay value that is adjusted based on the delay control code; comparing the phase of the delayed first clock with the phase of the second clock to generate a delay control code configured to bring the first and second input clocks in phase; synthesizing the delayed first input clock and the second input clock to output a synthesized clock; delaying the synthesized clock by a delay value corresponding to half of a delay value of the first input clock based on a delay control code to output the delayed synthesized clock; the second output clock is delayed by a delay value equal to the delay value of the first input clock based on the delay control code.

This embodiment may be able to generate intermediate phase clocks between clocks having a large phase difference therebetween.

Drawings

Fig. 1 is a diagram illustrating a conventional phase interpolator and its operation.

Fig. 2 is a diagram illustrating a delay circuit 200 according to an embodiment of the present invention.

Fig. 3 is a detailed diagram illustrating a first embodiment of the first and second delay lines of fig. 2.

Fig. 4 is a detailed diagram illustrating a second embodiment of the first and second delay lines of fig. 2.

Fig. 5 is a detailed diagram illustrating a third embodiment of the first and second delay lines of fig. 2.

Fig. 6 is a diagram illustrating a phase interpolator according to an embodiment of the present invention.

Fig. 7 is a diagram illustrating a phase interpolator according to another embodiment of the present invention.

Detailed Description

Various embodiments will be described later in order to describe the present disclosure in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the technical spirit of the present disclosure. In the description of the present embodiment, components irrelevant to the subject matter of the present embodiment may be omitted. When reference numerals are given to components in the drawings, the same components may be denoted by the same reference numerals even though the components are illustrated in different drawings.

It is noted that references to "an embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily to the same embodiment(s).

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below could also be termed a second or third element without departing from the spirit and scope of the present invention.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the singular forms may also include the plural forms and vice versa, unless the context clearly dictates otherwise. The articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

Fig. 2 is a diagram illustrating a delay circuit 200 according to an embodiment of the present invention.

Referring to fig. 2, the delay circuit 200 may include a first delay line 210, a delay control circuit 220, and a second delay line 230.

The first delay line 210 may generate a delayed first clock CLK1D by delaying the first clock CLK 1. The first delay line 210 may have a delay value adjusted by a delay control code DLY _ CONT < N:1 >.

The delay control circuit 220 may generate the delay control code DLY _ CONT < N:1> by comparing the delayed first clock CLK1D and the second clock CLK 2. The delay control circuit 220 may increase or decrease the code value of the delay control code DLY _ CONT < N:1> according to the result of phase comparison between the delayed first clock CLK1D and the second clock CLK 2. Accordingly, the delay control circuit 220 may generate the delay control code DLY _ CONT < N:1> such that the delayed first clock CLK1D and the second clock CLK2 are in phase, that is, the delay value of the first delay line 210 becomes equal to the phase difference between the first clock CLK1 and the second clock CLK 2.

The second delay line 230 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and the delay value corresponds to half of the delay value of the first delay line 210. Since the second delay line 230 receives the same delay control code DLY _ CONT < N:1> as the first delay line 210, the second delay line 230 may be designed to have a delay value corresponding to half of the delay value of the first delay line 210. The second delay line 230 may be used to delay the random signal IN that needs to be delayed.

Referring to fig. 2, the first delay line 210 may have a delay value corresponding to a phase difference between the first clock CLK1 and the second clock CLK2, and the second delay line 230 may have a delay value corresponding to half of the phase difference between the first clock CLK1 and the second clock CLK 2. Based on this characteristic, a phase interpolator to be described below can be designed.

Fig. 3 is a detailed diagram illustrating a first embodiment of the first delay line 210 and the second delay line 230 of fig. 2.

Referring to fig. 3, the first delay line 210 may include two variable delays 311 and 312, and the second delay line 230 may include one variable delay 321.

The first delay line 210 may include a first variable delay 311 and a second variable delay 312 coupled in series. Each of the first variable delay 311 and the second variable delay 312 may have a delay value adjusted by the delay control code DLY _ CONT < N:1>, and the first variable delay 311 and the second variable delay 312 may be designed in the same manner (i.e., may have the same element configuration) and have the same delay value.

The second delay line 230 may include a third variable delay 321. The third variable delay 321 may have a delay value that is adjusted by the delay control code DLY _ CONT < N:1 >. The third variable delay 321 may be designed in the same manner as the first variable delay 311 (i.e., may have the same element configuration) and have the same delay value as the first variable delay 311.

Since the first to third variable delays 311, 312 and 321 are designed in the same manner and receive the same delay control code DLY _ CONT < N:1>, the first to third variable delays 311, 312 and 321 may be equal to each other. Since the first delay line 210 includes two variable delays 311 and 312 coupled in series and the second delay line 230 includes one variable delay 321, the delay value of the first delay line 210 may be twice as large as the delay value of the second delay line 230.

Fig. 4 is a detailed diagram illustrating a second embodiment of the first delay line 210 and the second delay line 230 of fig. 2.

Referring to fig. 4, the first delay line 210 may include a first variable delay 411. The first variable delay 411 may have a delay value adjusted by the delay control code DLY _ CONT < N:1 >.

The second delay line 230 may include a code value transformer 431 and a second variable delay 432.

The code value converter 431 may generate the HALF delay control code DLY _ CONT _ HALF < N:1> by halving the code value of the delay control code DLY _ CONT < N:1 >. The HALF delay control code DLY _ CONT _ HALF < N:1> may be a code that: for controlling the delay value to be half of the code value of the delay control code DLY _ CONT < N:1 >. The delay control code DLY _ CONT < N:1> may have a binary code format or a thermometer code format. In any case, the code value converter 431 may generate the HALF delay control code DLY _ CONT _ HALF < N:1> such that the delay value corresponding to the HALF delay control code DLY _ CONT _ HALF < N:1> becomes HALF of the code value corresponding to the delay control code DLY _ CONT < N:1 >.

The second variable delay 432 may be designed in the same manner as the first variable delay 411 (i.e., may have the same configuration of elements) and may have a delay value adjusted by the HALF-delay control code DLY _ CONT _ HALF < N:1 >. Thus, the second variable delay 432 may have a delay value that corresponds to half the delay value of the first variable delay 411.

Fig. 5 is a detailed diagram illustrating a third embodiment of the first delay line 210 and the second delay line 230 of fig. 2. In fig. 5, <1> to < N > may represent N bits of the delay control code DLY _ CONT < N:1 >. Further, <1> B to < N > B may represent bits obtained by inverting N bits of the delay control code DLY _ CONT < N:1 >.

Referring to fig. 5, the first delay line 210 may include NAND gates 511 to 521 and inverters 522 to 527. The first delay line 210 may have a delay value adjusted by a delay control code DLY _ CONT < N:1 >. When the delay control code has a value of 000 … 11, the first clock CLK1 may be delayed by the NAND gates 511, 513, 515, 516, 520, 519, and 518. Further, when the delay control code has a value of 000 … 01, the first clock CLK1 may be delayed by the NAND gates 511, 513, 514, 519, and 518. Inverters 522 through 527 may act as latches that are used to form the load. The path traversed by the first clock CLK1 in the first delay line 210 may be adjusted in the first delay line 210 according to the value of the delay control code DLY _ CONT < N:1 >. That is, one of the N paths may be selected according to the value of the delay control code DLY _ CONT < N:1>, and the first clock CLK1 may be delayed by the selected path. For example, the NAND gates 512, 514, and 516 may select the path in the first delay line 210 through which the first clock CLK1 passes.

The second delay line 230 may include NAND gates 531 to 541 and inverters 542 to 547. The second delay line 230 has N/2 paths, and one of the N/2 paths may be selected by delaying the even code values DLY _ CONT <2>, <4>, > and < N > of the control code DLY _ CONT < N:1>, and is used to delay the input signal IN. The odd code values DLY _ CONT <1>, <3>,. and < N-1> of the delay control code DLY _ CONT < N:1>, the latch composed of the inverters 542 to 547 may be enabled or disabled, thereby adjusting the loading. When the delay control code has a value of 000 … 11, the input signal may be delayed by the NAND gates 531, 533, 534, 539, and 538. In this case, the inverter 543 may be disabled. Thus, the latch formed by inverters 544 and 545 may be disabled. When the delay control code has a value of 000 … 01, the input signal IN may be delayed by the NAND gates 531, 532, and 538. In this case, the inverter 543 may be enabled. Thus, the latch formed by inverters 542 and 543 may be enabled to increase loading. For reference, the NAND gates 542, 544, and 546 may select a path through which the input signal IN passes IN the second delay line 230.

Since the delay values of the first delay line 210 and the second delay line 230 are adjusted by the same delay control code DLY _ CONT < N:1> and a path having a length corresponding to half the length of the first delay line 210 is selected in the second delay line 230, the second delay line 230 may have a delay value corresponding to half the delay value of the first delay line 210.

Fig. 6 is a diagram illustrating a phase interpolator 600 according to an embodiment of the present invention.

Referring to fig. 6, the phase interpolator 600 may include a first delay line 610, a delay control circuit 620, and a second delay line 630.

The first delay line 610 may generate a delayed first clock CLK1D by delaying the first clock CLK 1. The first delay line 610 may have a delay value adjusted by a delay control code DLY _ CONT < N:1 >. The first delay line 610 may be designed in the same manner as the first delay line 210 (i.e., may have the same configuration of elements).

The delay control circuit 620 may generate a delay control code by comparing the phases of the delayed first clock CLK1D and the second clock CLK 2. The delay control circuit 620 may increase or decrease the code value of the delay control code DLY _ CONT < N:1> according to the result of phase comparison between the delayed first clock CLK1D and the second clock CLK 2. Accordingly, the delay control circuit 620 may generate the delay control code DLY _ CONT < N:1> such that the delayed first clock CLK1D and the second clock CLK2 are in phase, that is, the delay value of the first delay line 610 becomes equal to the phase difference between the first clock CLK1 and the second clock CLK 2.

The second delay line 630 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and the delay value corresponds to half of the delay value of the first delay line 610. Since the second delay line 630 receives the same delay control code DLY _ CONT < N:1> as the first delay line 610, the second delay line 630 may be designed to have a delay value corresponding to half of the delay value of the first delay line 610. The second delay line 630 may be designed in the same manner as the second delay line 230 (i.e., may have the same configuration of elements).

The second delay line 630 may generate a phase interpolated clock CLK12 by delaying the first clock CLK 1. Since the second delay line 630 has a delay value corresponding to half of the phase difference between the first clock CLK1 and the second clock CLK2, and the phase-interpolated clock CLK12 is obtained by delaying the first clock CLK1 via the second delay line 630, the phase-interpolated clock CLK12 may have an intermediate phase between the first clock CLK1 and the second clock CLK 2.

Fig. 7 is a diagram illustrating a phase interpolator 700 according to another embodiment of the present invention. The phase interpolator 700 of fig. 7 may generate 8 output clocks CLK0_ OUT, CLK45_ OUT, CLK90_ OUT, CLK135_ OUT, CLK180_ OUT, CLK225_ OUT, CLK270_ OUT, and CLK315_ OUT, which have a phase difference of 45 degrees therebetween, using four input clocks CLK0_ IN, CLK90_ IN, CLK180_ IN, and CLK270_ IN, which have a phase difference of 90 degrees therebetween.

Referring to fig. 7, the phase interpolator 700 may include first to eleventh delay lines 711 to 721, a delay control circuit 730, first to fourth drivers 741 to 744, and first to fourth synthesizers 751 to 754.

The first delay line 711 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and delay the first input clock CLK0_ IN.

The delay control circuit 730 may generate the delay control code DLY _ CONT < N:1> by comparing the phases of the output clock of the first delay line 711 and the second input clock CLK90_ IN. Accordingly, the delay control circuit 730 may generate the delay control code DLY _ CONT < N:1> such that the output clock of the first delay line 711 and the second input clock CLK90_ IN are IN phase, that is, the delay value of the first delay line 711 becomes equal to the phase difference between the first input clock CLK0_ IN and the second input clock CLK90_ IN.

The first driver 741 may output the output clock of the first delay line 711 as a first output clock CLK0_ OUT. The first driver 741 may include two inverters coupled in series.

The first synthesizer 751 may synthesize the output clock of the first delay line 711 and the second input clock CLK90_ IN and transmit the synthesized clock to the second delay line 712. Since the output clock of the first delay line 711 and the second input clock CLK90_ IN are IN phase, the first synthesizer 751 can be said to have transmitted two clocks to the second delay line 712. The first synthesizer 751 may include three inverters.

The second delay line 712 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and the delay value corresponds to half of the delay value of the first delay line 711. That is, the second delay line 712 may have a delay value corresponding to a phase difference of 45 degrees between clocks. The second delay line 712 may delay the output clock of the first synthesizer 751 and output the delayed clock as the second output clock CLK45_ OUT.

The second driver 742 may transmit the second input clock CLK90_ IN to the third delay line 713. The second driver 742 may include two inverters coupled in series.

The third delay line 713 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and equal to the delay value of the first delay line 711. That is, the third delay line 713 may have a delay value corresponding to a 90-degree phase difference between clocks. The third delay line 713 may delay the output clock of the second driver and output the delayed clock as a third output clock CLK90_ OUT.

The fourth delay line 714 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and equal to the delay value of the first delay line 711. The fourth delay line 714 may delay the second input clock CLK90_ IN.

The second synthesizer 752 may transmit the output clock of the fourth delay line 714 and the third input clock CLK180_ IN to the fifth delay line 715. The second synthesizer 752 may include three inverters.

The fifth delay line 715 may have a delay value that is adjusted by the delay control code DLY _ CONT < N:1> and that corresponds to half the delay value of the first delay line 711. The fifth delay line 715 may delay the output clock of the second synthesizer 752 and output the delayed clock as the fourth output clock CLK135_ OUT.

The third driver 743 may transmit the third input clock CLK180_ IN to the sixth delay line 716. The third driver 743 may include two inverters coupled in series.

The sixth delay line 716 has a delay value adjusted by the delay control code DLY _ CONT < N:1> and is equal to the delay value of the first delay line 711. The sixth delay line may delay the output clock of the third driver 743 and output the delayed clock as the fifth output clock CLK180_ OUT.

The seventh delay line 717 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and equal to the delay value of the first delay line 711. The seventh delay line 717 may delay the third driving input clock CLK180_ IN.

The third synthesizer 753 may transmit the output clock of the seventh delay line 717 and the fourth input clock CLK270_ IN to the eighth delay line 718. The third synthesizer 753 may include three inverters.

The eighth delay line 718 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and the adjusted value corresponds to half of the delay value of the first delay line 711. The eighth delay line 718 may delay the output clock of the third synthesizer 753 and output the delayed clock as the sixth output clock CLK225_ OUT.

The fourth driver 744 may transmit the fourth input clock CLK270_ IN to the ninth delay line 719. The fourth driver 744 may include two inverters coupled in series.

The ninth delay line 719 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and equal to the delay value of the first delay line 711. The ninth delay line 719 may delay the output clock of the fourth driver 744 and output the delayed clock as the seventh output clock CLK270_ OUT.

The tenth delay line 720 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and equal to the delay value of the first delay line 711. The tenth delay line 720 may delay the fourth driving input clock CLK270_ IN.

The fourth synthesizer 754 may transmit the output clock of the tenth delay line 720 and the first input clock CLK0_ IN to the eleventh delay line 721.

The eleventh delay line 721 may have a delay value adjusted by the delay control code DLY _ CONT < N:1> and the delay value corresponds to half of the delay value of the first delay line 711. The eleventh delay line 721 may delay the output clock of the fourth synthesizer 754 and output the delayed clock as the eighth output clock CLK315_ OUT.

According to the embodiment of fig. 7, the delay lines 711, 713, 714, 716, 717, 719, and 720 having delay values corresponding to a 90-degree phase difference between clocks and the delay lines 712, 715, 718, and 721 having delay values corresponding to a 45-degree phase difference between clocks may be combined, so that the phase interpolator may be able to generate clocks CLK0_ OUT, CLK45_ OUT, CLK90_ OUT, CLK135_ OUT, CLK180_ OUT, CLK225_ OUT, CLK270_ OUT, and CLK315_ OUT having desired phases.

According to the embodiment of the present invention, even in the case where two clocks to be synthesized are low-frequency clocks, the two clocks can be synthesized after being brought into phase.

Although various embodiments have been described for purposes of illustration, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope as defined in the following claims.