阅读说明：本技术 碳化硅半导体装置
(Silicon carbide semiconductor device
) 是由 富永贵亮
福井裕 于 2018-02-19 设计创作，主要内容包括：漂移层(10)以及源极区域(8)具有第1导电类型。基极区域(7)具有第2导电类型。第1沟槽(12)贯通源极区域(8)以及基极区域(7)。栅极电极(1)隔着栅极绝缘膜(2)设置于第1沟槽(12)内。第1缓和区域(3)配置于第1沟槽(12)的下方,具有第2导电类型。源极焊盘电极(4)与第1缓和区域(3)电连接。栅极焊盘电极(14)配置于非元件区域(RN)。杂质区域(108)配置于非元件区域(RN),设置于漂移层(10)上,具有第1导电类型。第2沟槽(112)贯通杂质区域(108)。第2缓和区域(103)配置于第2沟槽(112)的下方,具有第2导电类型。(The drift layer (10) and the source region (8) have a 1 st conductivity type. The base region (7) has a 2 nd conductivity type. The 1 st trench (12) penetrates the source region (8) and the base region (7). A gate electrode (1) is provided in the 1 st trench (12) with a gate insulating film (2) therebetween. The 1 st alleviation region (3) is arranged below the 1 st trench (12) and has the 2 nd conductivity type. The source pad electrode (4) is electrically connected to the 1 st buffer region (3). The gate pad electrode (14) is disposed in the non-element Region (RN). The impurity region (108) is disposed in the non-element Region (RN), is provided on the drift layer (10), and has the 1 st conductivity type. The 2 nd trench (112) penetrates the impurity region (108). The 2 nd relaxation region (103) is disposed below the 2 nd trench (112), and has the 2 nd conductivity type.)
1. A silicon carbide semiconductor device (701-714, 701V) having an element Region (RE) and a non-element Region (RN) provided outside the element Region (RE) in a plan view, the silicon carbide semiconductor device comprising:
a silicon carbide semiconductor substrate (11) that spans the element Region (RE) and the non-element Region (RN);
a drift layer (10) which is provided on the silicon carbide semiconductor substrate (11), comprises silicon carbide, and has the 1 st conductivity type;
a base region (7) which is disposed in the element Region (RE), is provided on the drift layer (10), and has a 2 nd conductivity type different from the 1 st conductivity type;
a source region (8) disposed on the element Region (RE), disposed on the base region (7), and having the 1 st conductivity type;
a 1 st trench (12) having side surfaces and a bottom surface penetrating the source region (8) and the base region (7);
a gate insulating film (2) provided on the side surface and the bottom surface of the 1 st trench (12);
a gate electrode (1) provided in the 1 st trench (12) with the gate insulating film (2) therebetween;
a 1 st relaxation region (3) which is disposed below the 1 st trench (12), is in contact with the drift layer (10), and has the 2 nd conductivity type;
a source pad electrode (4) electrically connected to the source region (8) and the 1 st buffer region (3);
a gate pad electrode (14) disposed in the non-element Region (RN) and electrically connected to the gate electrode (1);
at least 1 impurity region (108) disposed at least in the non-element Region (RN), provided on the drift layer (10), and having the 1 st conductivity type;
at least 12 nd trench (112) having a side surface and a bottom surface penetrating the impurity region (108); and
and at least 12 nd relaxation region (103) disposed below the 2 nd trench (112), in contact with the drift layer (10), and having the 2 nd conductivity type.
2. The silicon carbide semiconductor device (702, 704, 706, 709, 710) according to claim 1,
the silicon carbide semiconductor device (702, 704, 706, 709, 710) has a contact Region (RC) provided with a 3 rd trench (212) between the element Region (RE) and the non-element Region (RN) in a plan view,
the silicon carbide semiconductor device (702, 704, 706, 709, 710) further includes a 3 rd buffer region (203), and the 3 rd buffer region (203) is disposed below the 3 rd trench (212), electrically connected to the source pad electrode (4) and the 2 nd buffer region (103), and has the 2 nd conductivity type.
3. The silicon carbide semiconductor device (703, 704, 707, 709, 710, 714) according to claim 1, wherein,
the silicon carbide semiconductor device (703, 704, 707, 709, 710, 714) has a contact Region (RC) in which a part of the impurity region (108) is arranged between the element Region (RE) and the non-element Region (RN) in a plan view, and the impurity region (108) and the source pad electrode (4) are directly connected in the contact Region (RC).
4. The silicon carbide semiconductor device (704, 709, 710) according to claim 1,
the silicon carbide semiconductor device (704, 709, 710) has a contact Region (RC) in which a part of the impurity region (108) is arranged and a 3 rd trench (212) is provided between the element Region (RE) and the non-element Region (RN) in a plan view, wherein the impurity region (108) and the source pad electrode (4) are electrically connected in the contact Region (RC),
the silicon carbide semiconductor device (704, 709, 710) further includes a 3 rd buffer region (203), the 3 rd buffer region (203) being disposed below the 3 rd trench (212), electrically connected to the source pad electrode (4) and the 2 nd buffer region (103), respectively, and having the 2 nd conductivity type.
5. The silicon carbide semiconductor device (701 to 704, 701V, 708, 710, 713, 714) according to any one of claims 1 to 4,
the 2 nd trench (112) is filled with an insulator.
6. The silicon carbide semiconductor device (705-707, 709) according to any one of claims 1 to 4, further comprising:
an inner surface insulating film (202) provided on the side surface and the bottom surface of the 2 nd trench (112); and
and a low-resistance region (101) which is provided in the 2 nd trench (112) with the inner surface insulating film (202) interposed therebetween, is electrically insulated from the gate pad electrode (14), and is made of a metal or a doped semiconductor.
7. The silicon carbide semiconductor device (708, 713, 714) according to any one of claims 1 to 6,
the semiconductor device further comprises a connection region (109), wherein the connection region (109) is provided on the side surface of the 2 nd trench (112), has the 2 nd conductivity type, and connects the 2 nd buffer region (103) and the impurity region (108) to each other.
8. The silicon carbide semiconductor device (710) according to any one of claims 1 to 7,
a plurality of the 2 nd alleviation areas (103) are provided separately from each other,
a plurality of impurity regions (108) are provided so as to be separated from each other.
9. The silicon carbide semiconductor device (711) according to any one of claims 1 to 7,
a plurality of the 2 nd alleviation areas (103) are provided separately from each other,
the impurity region (108) includes a plurality of extended impurity regions (108X) separated from each other and a connecting impurity region (108Y) connecting adjacent ones of the plurality of extended impurity regions (108X) to each other.
10. The silicon carbide semiconductor device (712) according to any one of claims 1 to 7,
a plurality of impurity regions (108) are provided separately from each other,
the 2 nd relaxation region (103) includes a plurality of extension relaxation regions (103X) separated from each other and a connection relaxation region (103Y) connecting adjacent extension relaxation regions among the plurality of extension relaxation regions (103X) to each other.
11. The silicon carbide semiconductor device (701-714, 701V) according to any one of claims 1 to 10,
the 1 st trench (12) and the 2 nd trench (112) have the same depth.
12. The silicon carbide semiconductor device (710) according to any one of claims 1 to 11,
the 2 nd groove (112) is provided in plurality in the non-element Region (RN).
Technical Field
The present invention relates to a silicon carbide semiconductor device.
Background
As a switching element used in an inverter circuit or the like, a vertical power Semiconductor device is widely used, and particularly, an example having a Metal Oxide Semiconductor (MOS) structure is widely used. Typically, Insulated Gate Bipolar Transistors (IGBTs) and Metal-Oxide-Semiconductor Field effect transistors (MOSFETs) are used. For example, a MOSFET is disclosed in international publication No. 2010/098294 (patent document 1), and an IGBT is disclosed in japanese patent laid-open No. 2004-273647 (patent document 2). In particular, the former discloses a vertical n-channel MOSFET using silicon carbide (SiC) as a semiconductor material. In addition, for the purpose of further reducing the on-voltage of a vertical n-channel MOSFET using silicon carbide, a trench gate type MOSFET is disclosed in international publication No. 2012/077617 (patent document 3).
An n-channel MOSFET has an n-type drift layer and a p-type well disposed thereon. When the MOSFET is switched from an on state to an off state, the drain voltage of the MOSFET, i.e., the voltage of the drain electrode, sharply rises from approximately 0V to several hundred V. At this time, a displacement current is generated via a parasitic capacitance existing between the p-type well and the n-type drift layer. The displacement current generated on the drain electrode side flows to the drain electrode, and the displacement current generated on the source electrode side flows to the source electrode via the p-type well.
Here, in a vertical n-channel MOSFET, typically, in addition to a p-type well constituting a MOSFET cell that actually functions as a MOSFET, another p-type well is provided in the outer peripheral region of the chip. Examples of such other p-type wells include those located directly below the gate pad. These p-wells of the peripheral region typically have a very large cross-sectional area (area in planar layout) compared to the p-wells of the MOSFET cells. Therefore, the displacement current needs to flow through a long path in the p-type well in the peripheral region before reaching the source electrode. Therefore, the p-type well serves as a current path for the displacement current and has a high resistance. As a result, a potential drop of an extent that cannot be ignored may occur in the p-type well. Therefore, a relatively large potential difference occurs in the p-type well with respect to the source potential at a portion separated in the in-plane direction from the portion connected to the source electrode. Therefore, there is a fear that dielectric breakdown occurs due to the potential difference.
Recently, semiconductor devices using silicon carbide having a band gap about 3 times as large as that of silicon, which is the most general semiconductor material, have begun to be used as switching elements of inverter circuits, and in particular, n-channel MOSFETs have been applied. By using a semiconductor having a wide band gap, the loss of the inverter circuit can be reduced. In order to further reduce the loss, it is required to drive the switching element at a higher speed. In other words, in order to reduce the loss, it is required to further increase dV/dt, which is the variation of the drain voltage V with respect to the time t. In this case, the displacement current flowing into the p-type well via the parasitic capacitance also increases. Further, since it is difficult to lower the resistance of silicon carbide by doping as compared with silicon, the parasitic resistance of a p-type well tends to increase when silicon carbide is used. This large parasitic resistance tends to cause a large potential drop in the p-well. Due to the above, in the case of using silicon carbide, the above-described concern of dielectric breakdown is greater.
In the technique of international publication No. 2010/098294, a low-resistance p-type semiconductor layer is provided entirely or partially on the upper surface of a p-type well located below a gate pad in an outer peripheral region. Thus, the voltage distribution in the p-type well caused by the potential drop when the displacement current flows in the p-type well located below the gate pad is suppressed. Therefore, the potential difference between the p-type well and the gate electrode is suppressed. Thus, the gate insulating film is prevented from being broken.
On the other hand, in the technique of international publication No. 2011/007387 (patent document 4), a low-resistance n-type semiconductor layer is provided entirely or partially on the upper surface of a p-type well located below a gate pad in an outer peripheral region. This makes it possible to further suppress a voltage distribution in the p-type well due to a potential drop when a displacement current flows in the p-type well located below the gate pad, as compared with a case where a low-resistance p-type semiconductor layer is provided. Thereby, the potential difference between the p-type well and the gate electrode is suppressed. Thus, the gate insulating film is prevented from being broken.
Disclosure of Invention
In a planar MOSFET and a trench MOSFET, a structure of an outer peripheral region (more generally, a non-device region) is generally different. The technologies of international publication No. 2010/098294 and international publication No. 2011/007387 relate to planar MOSFETs, and are not necessarily suitable for trench MOSFETs.
The present invention has been made to solve the above-described problems, and an object thereof is to provide a trench-type silicon carbide semiconductor device capable of preventing element destruction during switching by suppressing a potential drop when a displacement current flows.
The silicon carbide semiconductor device of the present invention includes an element region and a non-element region provided outside the element region in a plan view. The silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a drift layer, a base region, a source region, a 1 st trench, a gate insulating film, a gate electrode, a 1 st buffer region, a source pad electrode, a gate pad electrode, at least 1 impurity region, at least 12 nd trench, and at least 12 nd buffer region. The silicon carbide semiconductor substrate spans the element region and the non-element region. The drift layer is disposed on the silicon carbide semiconductor substrate, includes silicon carbide, and has a 1 st conductivity type. The base region is disposed in the element region, disposed on the drift layer, and has a 2 nd conductivity type different from the 1 st conductivity type. The source region is disposed in the device region, disposed on the base region, and has a 1 st conductivity type. The 1 st trench has side surfaces and a bottom surface penetrating the source region and the base region. The gate insulating film is disposed on the side surface and the bottom surface of the 1 st trench. The gate electrode is disposed in the 1 st trench with a gate insulating film interposed therebetween. The 1 st relaxation region is disposed below the 1 st trench, is in contact with the drift layer, and has a 2 nd conductivity type. The source pad electrode is electrically connected to the source region and the 1 st buffer region. The grid pad electrode is configured in the non-element area and is electrically connected with the grid electrode. The impurity region is at least arranged in the non-element region, is arranged on the drift layer and has the 1 st conductive type. The 2 nd trench has a side surface and a bottom surface penetrating the impurity region. The 2 nd relaxation region is disposed below the 2 nd trench, is in contact with the drift layer, and has a 2 nd conductivity type.
According to the present invention, in the non-element region, the impurity region on the drift layer is included as a part of the path of the displacement current passing through the 2 nd relaxation region in the high-speed switching of the silicon carbide semiconductor device. Thereby, the effective sheet resistance to the displacement current is reduced. Therefore, the magnitude of the potential drop due to the displacement current is suppressed. Therefore, the magnitude of the voltage between the potential of the 2 nd relaxation region and the gate potential due to the potential drop is suppressed. Therefore, dielectric breakdown between the 2 nd relaxation region and the region having the gate potential is prevented.
The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.
Drawings
Fig. 1 is a plan view schematically showing the structure of a silicon carbide device according to embodiment 1 of the present invention.
Fig. 2 is a diagrammatic partial sectional view along the line II-II in fig. 1.
Fig. 3 is a diagrammatic partial sectional view along the line III-III in fig. 1.
Fig. 4 is a diagrammatic partial sectional view along the line IV-IV in fig. 1.
Fig. 5 is a partial cross-sectional view taken along line V-V in fig. 6 schematically showing the structure of a silicon carbide device according to a modification of embodiment 1 of the present invention.
Fig. 6 is a partially sectional perspective view schematically showing the structure of a silicon carbide device in a modification of embodiment 1 of the present invention, with a part of the structure on the upper surface side omitted.
Fig. 7 is a plan view schematically showing the structure of a silicon carbide device according to embodiment 2 of the present invention.
Fig. 8 is a schematic partial sectional view taken along line VIII-VIII of fig. 7.
Fig. 9 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 3 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
Fig. 10 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 4 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
Fig. 11 is a partial cross-sectional view showing a structure in a non-element region of a silicon carbide device in embodiment 5 of the present invention.
Fig. 12 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 6 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
Fig. 13 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 7 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
Fig. 14 is a partial cross-sectional view showing a structure in a non-element region of a silicon carbide device in embodiment 8 of the present invention.
Fig. 15 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 9 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
Fig. 16 is a partial plan view showing the structure of the silicon carbide semiconductor layer in the non-device region of the silicon carbide device according to embodiment 10 of the present invention.
Fig. 17 is a partial cross-sectional view taken along line XVII-XVII of fig. 16.
Fig. 18 is a partial cross-sectional view taken along line XVIII-XVIII of fig. 16.
Fig. 19 is a partial plan view showing the structure of the silicon carbide semiconductor layer in the non-device region of the silicon carbide device according to embodiment 11 of the present invention, in the same view as fig. 16.
Fig. 20 is a partial plan view showing the structure of the silicon carbide semiconductor layer in the non-device region of the silicon carbide device according to embodiment 12 of the present invention, in the same view as fig. 16.
Fig. 21 is a partial cross-sectional view showing a structure in a non-element region of a silicon carbide device in embodiment 13 of the present invention.
Fig. 22 is a partial cross-sectional view showing the structure of a silicon carbide device according to embodiment 14 of the present invention in a cross section similar to line VIII-VIII in fig. 7.
(symbol description)
RC: a contact region; RE: an element region; RN: a non-element region; 1: a gate electrode; 2: a gate insulating film; 3: a 1 st alleviation region; 4: a source pad electrode; 5: an interlayer insulating film; 6. 106: a high concentration region; 7: a base region; 8: a source region; 109: a connection region; 10: a drift layer; 11: a substrate (silicon carbide semiconductor substrate); 12: a 1 st groove; 14: a gate pad electrode; 30: an epitaxial layer; 101: a low resistance region; 102: an insulator region; 103: a 2 nd relaxation area; 104: a drain electrode; 107: an impurity region; 112: a 2 nd groove; 202: an inner surface insulating film; 203: a 3 rd relief region; 212: a 3 rd groove; 701-714 and 701V: MOSFET (silicon carbide semiconductor device).
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated.
< embodiment 1>
(Structure)
Fig. 1 is a plan view schematically showing the structure of a MOSFET701 (silicon carbide semiconductor device) in embodiment 1. The MOSFET701 has an element region RE and a non-element region RN in a plan view. The element region RE includes a region where a channel controlled by a gate electrode is arranged, and typically, a region where MOSFET cells actually functioning as a MOSFET are arranged. The non-element region RN is provided outside the element region RE and includes a region where the gate pad electrode 14 for supplying a desired voltage to the gate electrode from the outside is arranged. A wire made of metal such as aluminum is connected to the gate pad electrode 14 by ultrasonic bonding or the like. The non-element region RN may also include a termination region of the MOSFET 701.
In each of fig. 2 and 3, different partial cross sections in the element region RE are schematically shown along the line II-II and the line III-III in fig. 1. In fig. 4, a partial cross section in the non-element region RN is schematically shown along the line IV-IV of fig. 1. In these cross-sectional views and other cross-sectional views described later, a dot pattern is added to a region having a p-type conductivity (2 nd conductivity type).
The MOSFET701 includes a substrate 11 (silicon carbide semiconductor substrate), an epitaxial layer 30 (silicon carbide semiconductor layer), a gate insulating film 2, a gate electrode 1, a gate pad electrode 14, a source pad electrode 4, a drain electrode 104, an interlayer insulating film 5, and an insulator region 102. Epitaxial layer 30 includes drift layer 10, base region 7, source region 8, impurity region 108, high concentration region 6, 1 st buffer region 3, 2 nd buffer region 103, and connection region 9. The epitaxial layer 30 is provided with a 1 st trench 12 (fig. 2 and 3) and a 2 nd trench 112 (fig. 4).
The substrate 11 spans the element region RE and the non-element region RN. The substrate 11 has an n-type (1 st conductivity type). The epitaxial layer 30 is provided by epitaxial growth on the substrate 11, and spans the element region RE and the non-element region RN.
A drift layer 10 is provided on the substrate 11 across the element region RE and the non-element region RN, the drift layer 10 includes silicon carbide, the drift layer 10 is n-type, and has a value of 1 × 1014cm-3～1×1017cm-3Donor concentration of (2). The donor concentration of the drift layer 10 is preferably lower than that of the substrate 11.
A base region 7 disposed on the drift layer 10 and the element region RE, wherein the base region 7 has a p-type (a 2 nd conductive type different from the 1 st conductive type), preferably 1 × 1014cm-3～1×1018cm-3The acceptor concentration of the base region 7 may be uneven, the source region 8 is disposed on the element region RE and is provided on the base region 7, the source region 8 is n-type and has a donor concentration higher than that of the drift layer 10, specifically, 1 × 1018cm-3～1×1020cm-3Donor concentration of (2). The high concentration region 6 is disposed in the element region RE, penetrates the source region 8, and reaches the base region 7. The high concentration region 6 has a p-type and has an acceptor concentration higher than that of the base region 7Degree, in particular 1 × 1019cm-3～1×1021cm-3Acceptor concentration of (a).
In the present embodiment, as shown in fig. 2, a plurality of 1 st trenches 12 are arranged in an element region RE. with an interval, and as shown in fig. 2, a plurality of 1 st trenches 12 appearing in a certain cross section may be connected to each other in a planar layout, the 1 st trenches 12 have side surfaces and bottom surfaces, the side surfaces of the 1 st trenches 12 penetrate through a source region 8 and a base region 7, the side surfaces of the 1 st trenches 12 reach a drift layer 10 in the cross section of fig. 2, whereby, in the cross section of fig. 2, a channel constituting a MOSFET, a 1 st relaxation region 3 is arranged below the 1 st trenches 12 and in contact with the drift layer 10, typically, the 1 st relaxation region 3 is in contact with the bottom surfaces of the 1 st trenches 12, the 1 st relaxation region 3 has a p-type, and preferably, 1 × 1014cm-3～1×1018cm-3Acceptor concentration of (a). The acceptor concentration and the thickness of the 1 st relaxed region 3 may not be uniform. The gate insulating film 2 is provided on the side surface and the bottom surface of the 1 st trench 12. At least a part of the gate electrode 1 is provided in the 1 st trench 12 with the gate insulating film 2 interposed therebetween.
The source pad electrode 4 is electrically connected to the source region 8 and the high concentration region 6 by ohmic bonding or schottky bonding. In order to obtain this electrical connection, the source pad electrode 4 is in contact with the source region 8 and the high concentration region 6. In addition, a portion of the source pad electrode 4 in contact with the source region 8 and the high concentration region 6 may be silicided. In other words, the source electrode 4 may include a silicide layer in contact with the source region 8 and the high concentration region 6. The source pad electrode 4 is separated from the gate electrode 1 by an interlayer insulating film 5.
Source pad electrode 4 is electrically connected to first buffer region 3. In the present embodiment, source pad electrode 4 is connected to 1 st relaxation region 3 having a p-type only via a semiconductor region having a p-type. Specifically, as shown in fig. 3, source pad electrode 4 is connected to relaxation 1 st region 3 via high-concentration region 6, base region 7, and connection region 9. To obtain such an electrical connection, the connection region 9 adjoins the side faces of the 1 st trench 12 between the base region 7 and the bottom face of the 1 st trench 12.The connection region 9 is of p-type as described above, preferably of 1 × 1014cm-3～1×1018cm-3Acceptor concentration of (a). In addition, the acceptor concentration and the thickness of the connection region 9 may also be uneven. It is also possible to provide a plurality of connection regions 9 spaced apart from one another in a planar arrangement. In fig. 3, the connection regions 9 are provided on both sides of the 1 st groove 12, but may be provided only on one side. Further, the arrangement of the connection region 9 provided on one side of the 1 st groove 12 and the arrangement of the connection region 9 provided on the other side of the 1 st groove 12 may be different in the longitudinal direction of the 1 st groove 12.
The gate pad electrode 14 is disposed in the non-element region RN, and is electrically connected to the gate electrode 1 by ohmic bonding or schottky bonding. To obtain this electrical connection, for example, the gate electrode 1 includes a portion extending from the element region RE to the non-element region RN, and the extended portion is in contact with the gate pad electrode 14 in the non-element region RN. Thereby, ohmic connection or schottky connection is provided between the gate pad electrode 14 and the gate electrode 1.
The impurity region 108 is disposed at least in the non-element region RN and is provided on the drift layer 10, the impurity region 108 is of an n-type and has a donor concentration higher than that of the drift layer 10, specifically, the donor concentration of the impurity region 108 is 1 × 1018cm-3～1×1020cm-3The donor concentration may be the same as or different from that of the source region 8. The impurity region 108 is separated from the gate pad electrode 14 by the interlayer insulating film 5. In this embodiment, the impurity region 108 is preferably electrically connected to the source pad electrode 4, but may be insulated. Impurity region 108 is preferably electrically connected to first buffer region 3, but may be insulated. In the case where impurity region 108 is insulated from source pad electrode 4, the displacement current flowing from 2 nd relaxation region 103 to impurity region 108 via drift layer 10 may flow to any of the above-described electrodes via some capacitance, or may flow again to 2 nd relaxation region 103 via pn junction capacitance.
The No. 2 trench 112 (fig. 4) is disposed in the non-device region RN. The 2 nd trench 112 has side surfaces and a bottom surface. The side surface of the 2 nd trench 112 penetrates the impurity region 108 and reaches the drift layer 10. The 2 nd trench 112 may have the same depth as the 1 st trench 12. In the present embodiment, as shown in fig. 4, a plurality of the 2 nd grooves 112 are arranged at intervals. In addition, a plurality of 2 nd trenches 112 appearing in a certain cross section as shown in fig. 4 may also be connected to each other in a planar layout.
The 2 nd relaxation region 103 is disposed below the 2 nd trench 112 and contacts the drift layer 10, typically, the 2 nd relaxation region 103 contacts the bottom surface of the 2 nd trench 112, and the 2 nd relaxation region 103 is p-type, preferably 1 × 1014cm-3～1×1018cm-3Acceptor concentration of (a). The acceptor concentration and the thickness of the 2 nd relaxation region 103 may not be uniform. The 2 nd buffer region 103 may have the same acceptor concentration as that of the 1 st buffer region 3. In this embodiment, although the 2 nd relaxation region 103 is preferably electrically connected to the source pad electrode 4, it may be insulated. In addition, although the 2 nd alleviation region 103 is preferably electrically connected to the 1 st alleviation region 3, it may be insulated. The 2 nd relief region 103 may be directly connected to the 1 st relief region 3.
Insulator region 102 is disposed within trench 2 112 filling trench 2 112. In this embodiment, the 2 nd trench 112 is filled with only an insulator. The material of the insulator region 102 may not be uniform. For example, the portion of the insulator region 102 facing the side surface and the bottom surface of the 2 nd trench 112 is made of the same material as the gate insulating film 12 (fig. 2), and the portion filled in the 2 nd trench 112 via this portion is made of the same material as the interlayer insulating film 5.
The drain electrode 104 is provided on the surface (lower surface in fig. 2 to 4) of the substrate 11 opposite to the surface on which the drift layer 10 is provided. Thus, the drain electrode 104 is electrically connected to the drift layer 10 having an n-type via the substrate 11 having an n-type. Specifically, at least 1 (2 in the present embodiment) of interfaces forming an ohmic junction or interfaces forming a schottky junction are provided between the drain electrode 104 and the drift layer 10. Further, the drain electrode 104 may contain silicide at a junction with the drift layer 10.
In this embodiment, the 1 st conductivity type is an n-type and the 2 nd conductivity type is a p-type, but these conductivity types may be reversed as a modification. In this case, the words of "donor concentration" and "acceptor concentration" in the above description regarding the impurity concentration are mutually replaced. The planar layout shown in fig. 1 is an example, and the arrangement of the non-element regions RN in the planar layout is arbitrary.
(Effect)
According to this embodiment, in the non-element region RN (fig. 4), the impurity region 108 on the drift layer 10 is included as a path of a displacement current passing through the 2 nd relaxation region 103 at the time of high-speed switching of the MOSFET 701. Thereby, the effective sheet resistance to the displacement current is reduced. Therefore, the magnitude of the potential drop due to the displacement current is suppressed. Therefore, the magnitude of the voltage between the potential of the 2 nd relaxation region 103 and the gate potential due to the potential drop is suppressed. Therefore, dielectric breakdown between the 2 nd relaxation region 103 and the region having the gate potential, specifically, the gate pad electrode 14 is prevented.
Specifically, when the switch is turned off, a displacement current flows mainly in a direction from the 2 nd buffer region 103 toward the impurity region 108, and through a forward current in the pn junction between the 2 nd buffer region 103 and the drift layer 10. When the switch is turned on, a displacement current flows from impurity region 108 toward 2 nd buffer region 103 mainly through the pn junction capacitance between 2 nd buffer region 103 and drift layer 10. As for these displacement currents, the impurity regions 108 have a high impurity concentration and a low sheet resistance, and thus can flow in the impurity regions 108 with a low potential drop.
(modification example)
Fig. 5 is a partial cross-sectional view along the line V-V in fig. 6 schematically showing the structure of a MOSFET701V (silicon carbide device) in a modification of embodiment 1. Fig. 6 is a partially sectional perspective view schematically showing the structure of the MOSFET701V with a part of the structure on the upper surface side omitted.
In order to obtain electrical connection between the source pad electrode 4 and the 1 st relaxation region 3, in the MOSFET701 (fig. 3), the source pad electrode 4 and the 1 st relaxation region 3 are connected to each other through a p-type semiconductor region such as a connection region 9, but in the present modification (fig. 5), the source pad electrode 4 is in contact with the 1 st relaxation region 3. By this contact, ohmic junction or schottky junction is provided between the source pad electrode 4 and the 1 st relaxation region 3. This contact is obtained by providing a contact portion 15 extending in the interlayer insulating film 5 so as to reach the 1 st relaxation region 3 in the source pad electrode 4. The contact 15 may be disposed in a trench provided in the epitaxial layer 30. The trench may be disposed in the element region RE, and may be integrated with the 1 st trench 12 as shown in the figure.
Further, in the cross section shown in fig. 5, a plurality of 1 st moderation regions 3 separated from each other appear, but they are connected to each other in a planar layout.
< embodiment 2>
Fig. 7 is a plan view schematically showing the structure of a MOSFET702 (silicon carbide semiconductor device) in embodiment 2. The MOSFET702 has a contact region RC between the element region RE and the non-element region RN in a plan view.
Fig. 8 is a schematic partial sectional view taken along line VIII-VIII of fig. 7. In this embodiment, the 3 rd trench 212 is provided in the epitaxial layer 30 in at least a part of the contact region RC. The 3 rd trench 212 has side surfaces and a bottom surface. The 3 rd trench 212 may have the same depth as the 1 st trench 12.
The MOSFET702 has a 3 rd relaxation region 203 disposed in the contact region RC. Specifically, the 3 rd relaxation region 203 is disposed below the 3 rd trench 212 and contacts the drift layer 10. Typically, the 3 rd relief region 203 contacts the bottom surface of the 3 rd trench 212. The 3 rd relaxation region 203 has a p-type. The 3 rd buffer region 203 may have the same acceptor concentration as that of the 1 st buffer region 3. The 3 rd relief region 203 is electrically connected to the 2 nd relief region 103. Specifically, the 3 rd relief region 203 appears apart from the 2 nd relief region 103 in the cross section of fig. 8, but is connected to the 2 nd relief region 103 in the planar layout. The 3 rd relief region 203 is preferably connected to the 1 st relief region 3 in the planar layout, but may not be connected.
The 3 rd relief region 203 is electrically connected to the source pad electrode 4. To obtain this electrical connection, typically, in 3 rd trench 212, source pad electrode 4 includes contact portion 215 extending to 3 rd relief region 203 in interlayer insulating film 5. Contact portion 215 is in contact with buffer region 3, and source pad electrode 4 and buffer region 3 are ohmically bonded or schottky bonded to each other. Further, the source pad electrode 4 may include silicide at a junction with the 3 rd alleviation region 203.
With the above configuration, the 2 nd relaxation region 103 is electrically connected to the source pad electrode 4. Specifically, the 2 nd relaxation region 103 having the p type is connected to the source pad electrode 4 only through the 3 rd relaxation region 203 having the p type.
In addition, a part of the gate electrode 1 and a part of the gate pad electrode 14 may be disposed in contact with each other in the 3 rd trench 212. Thereby, the electrical connection between the gate electrode 1 and the gate pad electrode 14 is obtained.
Since the configuration other than the above is substantially the same as that of embodiment 1, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated.
According to the present embodiment, the 2 nd buffer region 103 is connected to the source pad electrode 4 via the 3 rd buffer region 203. This enables the displacement current flowing through the 2 nd relaxation region 103 during high-speed switching to sufficiently flow to the source pad electrode 4 or from the source pad electrode 4. Therefore, the magnitude of the potential drop due to the displacement current is further suppressed. Therefore, the magnitude of the voltage between the potential of the 2 nd relaxation region 103 and the gate potential due to the potential drop is further suppressed. Therefore, dielectric breakdown between the 2 nd relaxation region 103 and the region having the gate potential, specifically, the gate pad electrode 14 is more reliably prevented.
The planar layout shown in fig. 7 is an example, and the arrangement of the non-element region RN in the planar layout is arbitrary. The structure for obtaining the electrical connection between source pad electrode 4 and 2 nd relaxation region 103 is not limited to the example shown in fig. 8, and they may be in contact with each other, for example.
< embodiment 3>
Fig. 9 is a partial cross-sectional view showing the structure of a MOSFET703 (silicon carbide semiconductor device) in embodiment 3 in the same cross-section as the line VIII-VIII in fig. 7. The MOSFET703 has a contact region RC in which a part of the impurity region 108 (fig. 9) is arranged between the element region RE and the non-element region RN in a plan view (see fig. 7). In the contact region RC, the impurity region 108 and the source pad electrode 4 are electrically connected. To obtain this electrical connection, typically, the source pad electrode 4 includes a contact portion 115 extending toward the impurity region 108 in the interlayer insulating film 5 in the contact region RC. The contact portion 115 is in contact with the impurity region 108, and an ohmic junction or a schottky junction is provided between the source pad electrode 4 and the impurity region 108. Thereby, the impurity region 108 and the source pad electrode 4 are electrically connected in the contact region RC. In this embodiment, the contact portion 215 is not provided (fig. 8: embodiment 2).
Since the other configurations are substantially the same as those of embodiment 1 or 2, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated.
According to the present embodiment, the impurity region 108 is electrically connected to the source pad electrode 4. This enables a sufficient flow of displacement current flowing through the impurity region 108 to the source pad electrode 4 or from the source pad electrode 4 during high-speed switching. Therefore, the magnitude of the potential drop due to the displacement current is further suppressed. Therefore, the magnitude of the voltage between the potential of the 2 nd relaxation region 103 and the gate potential due to the potential drop is further suppressed. Therefore, dielectric breakdown between the 2 nd relaxation region 103 and the region having the gate potential, specifically, the gate pad electrode 14 is more reliably prevented.
< embodiment 4>
Fig. 10 is a partial cross-sectional view showing the structure of a MOSFET704 (silicon carbide semiconductor device) in embodiment 4 in a cross-section similar to the line VIII-VIII in fig. 7. The MOSFET704 is provided with both the contact portion 215 described in embodiment 2 and the contact portion 115 described in embodiment 3. Thereby, the effects of both embodiments 2 and 3 are obtained.
< embodiment 5>
Fig. 11 is a partial cross-sectional view showing the structure in the non-element region RN of the MOSFET705 (silicon carbide semiconductor device) in embodiment 5. MOSFET705 includes an interlayer insulating film 202 and a low-resistance region 101 instead of insulator region 102 (fig. 4: embodiment 1).
The inner surface insulating film 202 is provided on the side surface and the bottom surface of the 2 nd trench 112. The material of the inner surface insulating film 202 may be the same as that of the gate insulating film 2 (fig. 2: embodiment 1).
The low-resistance region 101 is provided in the 2 nd trench 112 with the inter-surface insulating film 202 interposed therebetween. The low-resistance region 101 is electrically insulated from the gate pad electrode 14 by the interlayer insulating film 5. The low-resistance region 101 is made of metal or doped semiconductor. Thus, the low-resistance region 101 has low resistivity. The material of the low-resistance region 101 may be the same as that of the gate electrode 1 (fig. 2: embodiment 1).
Since the other configurations are substantially the same as those of embodiments 1 to 4, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. The present embodiment also provides substantially the same effects as those of embodiments 1 to 4.
< embodiment 6>
Fig. 12 is a partial cross-sectional view showing the structure of a MOSFET706 (silicon carbide device) in embodiment 6 in the same cross-section as the line VIII-VIII in fig. 7. The MOSFET706 has the same contact portion 215 as in embodiment 2 (fig. 8), and has the same inner surface insulating film 202 and low-resistance region 101 as in embodiment 5 (fig. 11).
Since the configuration other than the above is substantially the same as that of embodiment 1, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. According to the present embodiment, substantially the same effects as those of embodiments 2 and 5 described above are obtained.
< embodiment 7>
Fig. 13 is a partial cross-sectional view showing the structure of a MOSFET707 (silicon carbide device) in embodiment 7 in a cross-section similar to the line VIII-VIII in fig. 7. The MOSFET707 has the same contact portion 115 as in embodiment 3 (fig. 9), and has the same inner surface insulating film 202 and low-resistance region 101 as in embodiment 5 (fig. 11).
Since the configuration other than the above is substantially the same as that of embodiment 1, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. According to the present embodiment, substantially the same effects as those of embodiments 3 and 5 described above are obtained.
< embodiment 8>
Fig. 14 is a partial cross-sectional view showing the structure of a MOSFET708 (silicon carbide semiconductor device) in non-element region RN in embodiment 8, MOSFET708 has a connection region 109, connection region 109 is adjacent to the side surface of the 2 nd trench 112, and is connected to the 2 nd buffer region 103 and impurity region 108, connection region 109 has a p-type, and preferably has a value of 1 × 1014cm-3～1×1018cm-3Acceptor concentration of (a). Further, in the MOSFET708, as shown in fig. 11, there may be a cross section where the connection region 109 is not provided. In fig. 14, the connection regions 109 are provided on both sides of the 2 nd trench 112, but may be provided only on one side. The arrangement of the connection region 109 provided on one side of the 2 nd trench 112 and the arrangement of the connection region 109 provided on the other side of the 2 nd trench 112 may be different in the longitudinal direction of the 2 nd trench 112. The acceptor concentration and the thickness of the connection region 109 may also be non-uniform.
Since the other configurations are substantially the same as those of embodiments 1 to 4, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. As a modification, the connection region 109 (fig. 14) may be applied to embodiments 5 to 7 (fig. 11 to 13) having the inner surface insulating film 202 and the low resistance region 101.
According to this embodiment, connection region 109 is provided between second buffer region 103 and impurity region 108. This allows a displacement current during high-speed switching of MOSFET708 to efficiently flow between second relaxation region 103 and impurity region 108. When the switch is turned off, a displacement current flows from the 2 nd relaxation region 103 to the impurity region 108 through the connection region 109 mainly by a forward current at a pn junction between the connection region 109 and the impurity region 108. When the switch is turned on, a displacement current flows from impurity region 108 to second relaxation region 103 through connection region 109 and mainly through the pn junction capacitance between connection region 109 and impurity region 108. Since the connection region 109 is provided, these displacement currents can flow with a low potential drop.
< embodiment 9>
Fig. 15 is a partial cross-sectional view showing the structure of a MOSFET709 (silicon carbide device) in embodiment 9 in the same cross-section as the line VIII-VIII in fig. 7. The MOSFET709 has the same contact 115 and the same contact 215 as those in embodiment 4 (fig. 10), and has the same inner surface insulating film 202 and the low-resistance region 101 as those in embodiment 5 (fig. 11).
Since the configuration other than the above is substantially the same as that of embodiment 1, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. According to the present embodiment, substantially the same effects as those of embodiments 4 and 5 described above are obtained.
< embodiment 10>
Fig. 16 is a partial plan view showing the structure of the epitaxial layer 30 in the non-element region RN of the MOSFET710 (silicon carbide device) in embodiment 10. Each of fig. 17 and 18 is a partial cross-sectional view taken along lines XVII-XVII and XVIII-XVIII of fig. 16.
In the present embodiment, a plurality of 2 nd grooves 112 are arranged at intervals. Specifically, in the drawings, they extend in the longitudinal direction, respectively, and they are separated from each other in the lateral direction. In the present embodiment, these plural portions are connected to the 3 rd groove 212 as shown in fig. 18. Accordingly, the 2 nd relaxation area 103 is connected to the 3 rd relaxation area 203.
In the non-element region RN, the impurity regions 108 (fig. 16) are disposed between the 2 nd trenches 112. The plurality of impurity regions 108 are separated from each other. Each of which is electrically connected to the source pad electrode 4, for example, via a contact portion 115 (fig. 17). The contact portions 115 may either extend continuously in the lateral direction of fig. 16 in a manner spanning them, or may have a plurality of portions that are split.
The 2 nd alleviation regions 103 are each disposed below the 2 nd trench 112, specifically, on the bottom surface thereof. Thereby, the plurality of 2 nd relaxation regions 103 are separated from each other as shown in fig. 16. In fig. 16, they extend in the longitudinal direction, respectively, and they are separated from each other in the lateral direction just below the impurity region 108 by the drift layer 10 (not shown in fig. 16). Each of the 2 nd relaxation regions 103 is electrically connected to the source pad electrode 4 through the 3 rd relaxation region 203, for example, via a contact portion 215 (fig. 18). The contact portion 215 may extend continuously in the lateral direction of fig. 16, or may have a plurality of portions that are split.
Since the other configurations are substantially the same as those of embodiments 1 to 4, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. As a modification, the structure shown in this embodiment mode can be applied to embodiments 5 to 7 (fig. 11 to 13) having the inner surface insulating film 202 and the low resistance region 101 instead of the insulator region 102.
According to the present embodiment, as shown in fig. 16, a simple planar layout can be used as the planar layout of the non-element region RN. Specifically, a planar layout of lines and spaces arranged in one direction (lateral direction in fig. 16) can be used. This can improve the reliability of the MOSFET.
< embodiment 11>
Fig. 19 is a partial plan view showing the structure of the epitaxial layer 30 in the non-element region RN of the MOSFET711 (silicon carbide device) in embodiment 11, in the same view as fig. 16. In the MOSFET711, the impurity region 108 includes a plurality of extension impurity regions 108X and at least 1 connection impurity region 108Y. The plurality of extended impurity regions 108X are separated from each other, and each extends in one direction (longitudinal direction in the drawing). The connecting impurity region 108Y connects adjacent ones of the plurality of extended impurity regions 108X to each other. The connecting impurity region 108Y may be provided in at least a part of a pair of mutually adjacent extended impurity regions 108X.
The other configurations are substantially the same as those of embodiment 10 or its modified example, and therefore the same or corresponding elements are denoted by the same reference numerals and description thereof will not be repeated.
According to the present embodiment, impurity region 108 constituting a path of displacement current together with 2 nd relaxation region 103 is provided with connection impurity region 108Y. Thereby, the nonuniformity of the distribution of the displacement current flowing through the 2 nd relaxation region 103 in the non-element region RN at the time of high-speed switching is suppressed. Therefore, the nonuniformity of the distribution of the magnitude of the potential drop along the 2 nd relaxation region 103 is suppressed. Therefore, the voltage between the 2 nd relaxation region 103 and the gate pad electrode 14 due to the potential drop is suppressed from locally increasing. Therefore, dielectric breakdown between second buffer region 103 and gate pad electrode 14 is more reliably prevented.
< embodiment 12>
Fig. 20 is a partial plan view showing the structure of the epitaxial layer 30 in the non-element region RN of the MOSFET712 (silicon carbide device) in embodiment 12, in the same view as fig. 16. In the MOSFET712, the 2 nd relaxation region 103 includes a plurality of extension relaxation regions 103X and at least 1 connection relaxation region 103Y. The plurality of extension moderating regions 103X are separated from each other, and each extends in one direction (longitudinal direction in the drawing). The connection moderation region 103Y connects adjacent extension moderation regions among the plurality of extension moderation regions 103X to each other. The connection alleviation region 103Y may be provided in at least a part of the pair of adjacent extension alleviation regions 103X.
The other configurations are substantially the same as those of embodiment 10 or its modified example, and therefore the same or corresponding elements are denoted by the same reference numerals and description thereof will not be repeated.
According to the present embodiment, the connection relaxing region 103Y is provided in the 2 nd relaxing region 103. Thereby, the nonuniformity of the distribution of the displacement current flowing through the 2 nd relaxation region 103 in the non-element region RN at the time of high-speed switching is suppressed. Therefore, the nonuniformity of the distribution of the magnitude of the potential drop along the 2 nd relaxation region 103 is suppressed. Therefore, the voltage between the 2 nd relaxation region 103 and the gate pad electrode 14 due to the potential drop is suppressed from locally increasing. Therefore, dielectric breakdown between second buffer region 103 and gate pad electrode 14 is more reliably prevented.
< embodiment 13>
Fig. 21 is a partial cross-sectional view showing the structure of a MOSFET713 (silicon carbide device) in embodiment 13 in a non-element region RN, the MOSFET713 has a structure in which a p-type impurity region 107 is added to the structure of embodiment 8 (fig. 14), the impurity region 107 is disposed on the drift layer 10 directly below the impurity region 108, in other words, in this embodiment, the impurity region 108 is disposed on the drift layer 10 with the impurity region 107 interposed therebetween, the connection region 109 connects the second relaxation region 103 and the impurity region 107, and the impurity region 107 preferably has a value of 1 × 1014cm-3～1×1018cm-3Acceptor concentration of (a). The acceptor concentration and the thickness of the impurity region 107 may be uneven.
The other configurations are substantially the same as those of embodiments 1 to 4 or 10 to 12, and therefore the same or corresponding elements are denoted by the same reference numerals and description thereof will not be repeated. As a modification, the impurity region 107 can be applied to embodiments 5 to 7 (fig. 11 to 13) having the inner surface insulating film 202 and the low-resistance region 101 instead of the insulator region 102.
According to this embodiment, by providing impurity region 107, a displacement current during high-speed switching of MOSFET713 can be made to flow efficiently between second relaxation region 103 and impurity region 108. When the switch is turned off, a displacement current flows mainly by a forward current in a pn junction between the impurity region 107 and the impurity region 108 from the 2 nd relaxation region 103 to the impurity region 108 via the connection region 109 and the impurity region 107. When the switch is turned on, a displacement current flows from impurity region 108 to No. 2 relaxation region 103, mainly through the pn junction capacitance between impurity region 107 and impurity region 108 via impurity region 107 and connection region 109. Since the impurity region 107 is provided, these displacement currents can flow with a low potential drop.
< embodiment 14>
(Structure)
Fig. 22 is a partial cross-sectional view showing the structure of a MOSFET714 (silicon carbide device) in embodiment 14 in the same cross-section as the line VIII-VIII in fig. 7.
In the MOSFET714, the impurity region 108 includes a partial region 108N disposed in the non-element region RN and a partial region 108C disposed in the contact region RC. The partial region 108N and the partial region 108C appear separately in the cross section of fig. 22, but are connected to each other in a planar layout. The impurity region 107 includes a partial region 107N disposed in the non-element region RN and a partial region 107C disposed in the contact region RC. The partial region 107N and the partial region 107C appear separately in the cross section of fig. 22, but are connected to each other in a planar layout.
In the contact region RC, the epitaxial layer 30 has a high concentration region 106, the high concentration region 106 penetrates the partial region 108C and reaches the partial region 107C, the high concentration region 106 is of p-type and has an acceptor concentration higher than that of the impurity region 107, specifically, 1 × 1019cm-3～1×1021cm-3Acceptor concentration of (a). The acceptor concentration of the high concentration region 106 may be the same as that of the high concentration region 6.
The partial region 108C is electrically connected to the source pad electrode 4. To obtain this electrical connection, typically, in the contact region RC, the source pad electrode 4 includes a contact portion 315 extending to the partial region 108C in the interlayer insulating film 5. By the contact 315 being in contact with the partial region 108C, an ohmic junction or a schottky junction is provided between the source pad electrode 4 and the partial region 108C. With this configuration, the source pad electrode 4 is connected to the partial region 108N via the partial region 108C. Thereby, the entire impurity region 108 is electrically connected to the source pad electrode 4.
The high concentration region 106 is electrically connected to the source pad electrode 4. To obtain this electrical connection, typically, in the contact region RC, the source pad electrode 4 includes a contact portion 315 extending to the high concentration region 106 in the interlayer insulating film 5. The contact portion 315 is in contact with the high concentration region 106, and an ohmic junction or a schottky junction is provided between the source pad electrode 4 and the high concentration region 106. With this structure, the source pad electrode 4 is connected to the 2 nd relaxation region 103 having a p-type via the high concentration region 106, the partial region 107C, and the connection region 109 which have a p-type in common. Thereby, 2 nd relaxation region 103 is electrically connected to source pad electrode 4.
Note that the other configurations are substantially the same as those of embodiment 13 or its modified example, and therefore the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated.
(Effect)
According to the present embodiment, source pad electrode 4 is electrically connected to impurity region 108 and 2 nd buffer region 103. This enables the displacement current flowing through the 2 nd relaxation region 103 during high-speed switching to sufficiently flow to the source pad electrode 4 or from the source pad electrode 4. Therefore, the magnitude of the potential drop due to the displacement current is further suppressed. Therefore, the magnitude of the voltage between the potential of the 2 nd relaxation region 103 and the gate potential due to the potential drop is further suppressed. Therefore, dielectric breakdown between the 2 nd relaxation region 103 and the region having the gate potential, specifically, the gate pad electrode 14 is more reliably prevented.
Specifically, since the impurity region 108 is electrically connected to the source pad electrode 4, a displacement current generated in the impurity region 108 during high-speed switching can be easily caused to flow to the source pad electrode 4 or from the source pad electrode 4. Further, since the 2 nd relaxation region 103 is electrically connected to the source pad electrode 4, a displacement current generated in the 2 nd relaxation region 103 at the time of high-speed switching can be easily caused to flow to the source pad electrode 4 or to flow from the source pad electrode 4.
In addition, the present invention can freely combine the respective embodiments or appropriately modify or omit the respective embodiments within the scope of the present invention. Although the present invention has been described in detail, the above description is illustrative in all aspects, and the present invention is not limited thereto. It is to be understood that numerous modifications, not illustrated, may be devised without departing from the scope of the invention.
