阅读说明：本技术 晶体管及形成晶体管的方法 (Transistor and method of forming a transistor ) 是由 D·V·N·拉马斯瓦米 于 2019-01-03 设计创作，主要内容包括：本发明揭示一种晶体管,其包括一对源极/漏极区域,所述对源极/漏极区域之间具有沟道。晶体管栅极构造是操作地接近所述沟道。所述沟道包括Si<Sub>1-y</Sub>Gey,其中“y”是从0到0.6。所述源极/漏极区域中的每一者的至少一部分包括Si<Sub>1-</Sub><Sub>x</Sub>Ge<Sub>x</Sub>,其中“x”是从0.5到1。本发明还揭示包含方法的其它实施例。(A transistor includes a pair of source/drain regions having a channel therebetween. A transistor gate is configured to be operatively proximate to the channel. The channel comprises Si 1‑y Gey, where "y" is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si 1‑ x Ge x Wherein "x" is from 0.5 to 1. Other embodiments including methods are also disclosed.)

1. A transistor, comprising:

a pair of source/drain regions having a channel therebetween;

a transistor gate construction operatively proximate to the channel;

the channel comprises Si_1-yGe_yWherein "y" is from 0 to 0.6; and

at least a portion of each of the source/drain regions comprises Si_1-xGe_xWherein "x" is from 0.5 to 1.

2. The transistor of claim 1, wherein "x" is greater than "y".

3. The transistor of claim 1, wherein "y" is 0.

4. The transistor of claim 1, wherein "x" equals "y".

5. The transistor of claim 1, wherein each of the portions encompasses an entirety of the respective source/source drain region.

6. The transistor of claim 1, wherein each of the portions encompasses only a portion of the respective source/drain region.

7. The transistor of claim 1 wherein each of the portions and the Si therein_1-xGe_xIs directly against the channel.

8. The transistor of claim 1, wherein the portion and the Si therein_1-xGe_xAre not directly adjacent to the channel.

9. The transistor of claim 8, wherein each of the source/drain regions comprises the Si_1-yGe_yAnd is the Si directly adjacent to the channel_1-yGe_y。

10. The transistor of claim 1, wherein the portion and the Si therein_1-xGe_xIs directly against the channel, and the portion and the Si therein_1-xGe_xThe other of which does not directly abut against the channel.

11. The transistor of claim 1, wherein each of the source/drain regions includes at least a portion thereof including a conductivity enhancing dopant therein having a maximum concentration of the conductivity enhancing dopant within the respective source/drain region, each of the portions being within the portion.

12. The transistor of claim 1 wherein the channel includes a conductivity enhancing dopant therein, the conductivity enhancing dopant having no more than 1 × 10 in the channel¹⁴Atom/cm³The maximum concentration of (c).

13. The transistor of claim 1 wherein an immeasurable amount of conductivity enhancing dopant is included in the channel.

14. The transistor of claim 1, wherein each of the source/drain regions comprises Si_1-yGe_yAnd is the Si directly adjacent to the channel_1-yGe_y。

15. The transistor of claim 14, wherein the channel comprises a direction of current flow through the channel between the pair of source/drain regions, the Si of each of the source/drain regions_1-yGe_yHaving a maximum thickness in the direction of current flow of 2 to 200 angstroms.

16. The transistor of claim 1, wherein the channel comprises a direction of current flow through the channel between the pair of source/drain regions, each of the portions extending completely through the respective source/drain region orthogonal to the current flow direction.

17. The transistor of claim 1, wherein the channel comprises a direction of current flow through the channel between the pair of source/drain regions, the Si_1-yGe_yExtending completely in the current flow direction.

18. The transistor of claim 1, wherein the channel comprises a direction of current flow through the channel between the pair of source/drain regions, the Si_1-yGe_yDoes not extend completely in the current flow direction.

19. The transistor of claim 1, which is vertically extended.

20. The transistor of claim 19, wherein one of the pair of source/drain regions is directly over the other of the pair of source/drain regions.

21. The transistor of claim 19 being vertical or within 10 ° of vertical.

22. The transistor of claim 21, wherein the combination of the pair of source/drain regions and the channel has an aspect ratio of at least 3: 1.

23. The transistor of claim 1, which is a thin film transistor.

24. A transistor, comprising:

a pair of source/drain regions having a channel therebetween;

a transistor gate construction operatively proximate to the channel;

the channel comprises a direction of current flow through the channel between the pair of source/drain regions;

insulator material regions in each of the source/drain regions, the insulator material regions being individually elongated orthogonal to the current flow direction and no thicker than 10 angstroms in the current flow direction.

25. The transistor of claim 24 wherein each of the insulator material regions is at least 2 angstroms thick.

26. The transistor of claim 25 wherein each of the insulator material regions is no more than 5 angstroms thick.

27. The transistor of claim 24 wherein each of the insulator material regions comprises SiO₂。

28. The transistor of claim 24 wherein each of the insulator material regions comprises C.

29. The transistor of claim 28 wherein each of the insulator material regions comprises amorphous carbon and Si_xO_yC_zAt least one of (a).

30. The transistor of claim 24 wherein each of the insulator material regions is directly against the channel.

31. The transistor of claim 24 wherein each of the insulator material regions does not directly abut against the channel.

32. The transistor of claim 24, wherein each of the insulator material regions extends completely through the respective source/drain region orthogonal to the current flow direction.

33. The transistor of claim 24 wherein each of the insulator material regions serves, at least in part, as a limiter for conductivity-modifying dopant diffusion between (a) each of the source/drain regions and (b) the channel.

34. A transistor, comprising:

a pair of source/drain regions having a channel therebetween;

a transistor gate construction operatively proximate to the channel;

the channel includes a direction in which current flows between the pair of source/drain regions through the channel, the channel including Si_1-yGe_yWherein "y" is from 0 to 0.6;

at least a portion of each of the source/drain regions comprises Si_1-xGe_xWherein "x" is greater than y and from 0.5 to 1; and

insulator material regions in each of the source/drain regions, the insulator material regions being individually elongated orthogonal to the current flow direction and no thicker than 10 angstroms in the current flow direction.

35. A transistor, comprising:

a pair of source/drain regions having a channel therebetween;

a transistor gate construction operatively proximate to the channel;

the channel comprises a direction of current flow through the channel between the pair of source/drain regions; and

a pair of insulator material regions located in the channel, the pair of insulator material regions each elongated orthogonal to and each no thicker than 10 angstroms in the current flow direction, the insulator material regions individually directly abutting one of the pair of source/drain regions.

36. The transistor of claim 35, wherein each of the insulator material regions extends into one of the respective source/source drain regions.

37. The transistor of claim 36, wherein each of the insulator material regions extends completely through the respective source/drain region orthogonal to the current flow direction.

38. The transistor of claim 35 wherein each of the insulator material regions extends completely through the channel orthogonal to the current flow direction.

39. A method of forming a transistor, comprising:

forming a pair of source/drain regions having a channel therebetween, the channel comprising Si_1-yGe_yWherein "y" is from 0 to 0.6, at least a portion of each of the source/drain regions comprising Si_1-xGe_xWherein "x" is from 0.5 to 1, including conductivity enhancing dopants within each of the source/drain regions;

activating the conductivity enhancing dopant in each of the source/drain regions at a temperature of no more than 600 ℃; and

a transistor gate construction is formed in operative proximity to the channel.

40. The method of claim 39, wherein the activating is performed at a temperature of no more than 600 ℃.

41. The method of claim 39, wherein the channel is crystalline at the onset of the activating.

42. The method of claim 39, wherein the channel is amorphous at the beginning of the activation, the channel becoming crystalline during the activation.

Technical Field

Embodiments disclosed herein relate to transistors and methods of forming transistors.

Background

Memory is one type of integrated circuit and is used to store data in a computer system. The memory may be fabricated as one or more arrays of individual memory cells. The memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, or sense lines) and access lines (which can also be referred to as word lines). Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of sense and access lines.

The memory cells may be volatile, semi-volatile, or nonvolatile. Non-volatile memory cells can store data for long periods of time in the absence of power. Non-volatile memory is typically particularly intended as memory having a retention time of at least about 10 years. Volatile memory consumes and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, the memory cells are configured to save or store storage into at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store more than two layers or states of information.

A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors include a pair of conductive source/drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to and separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source/drain regions through the channel region to the other. When voltage is removed from the gate, current is substantially prevented from flowing through the channel region. The field effect transistor may also include additional structures, such as a reversibly programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate.

The transistor may be used in circuits other than memory circuits.

Drawings

Fig. 1 is a diagrammatic cross-sectional view of a transistor according to an embodiment of the invention and is taken through line 1-1 in fig. 2-4.

Fig. 2 is a cross-sectional view taken through line 2-2 in fig. 1.

Fig. 3 is a cross-sectional view taken through line 3-3 in fig. 1.

Fig. 4 is a cross-sectional view taken through line 4-4 in fig. 1.

Fig. 5 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 6 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 7 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 8 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 9 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 10 is a diagrammatic cross-sectional view of a transistor in accordance with an embodiment of the invention.

Fig. 11 is a diagrammatic, cross-sectional view of a transistor in accordance with an embodiment of the invention and is taken through line 11-11 in fig. 12.

Fig. 12 is a cross-sectional view taken through line 12-12 in fig. 11.

Detailed Description

Embodiments of the invention encompass transistors, transistor arrays, and devices comprising one or more transistors. A first example embodiment is described with reference to fig. 1 to 4. The substrate fragment, construction or device 10 includes a base substrate 11, which may include one or more of a conductive/conductor (i.e., electrically conductive/conductor herein) material, a semi-conductive/semiconductor material, or an insulating/insulator (i.e., electrically insulating/insulator herein) material. Various materials have been formed vertically above the base substrate 11. The material may be located on both sides of the material depicted in fig. 1-4, vertically within it, and/or vertically outward of it. For example, other partially or completely fabricated components of the integrated circuit may be disposed above the base substrate 11, around the base substrate 11, and/or at some location within the base substrate 11. Control and/or other peripheral circuitry for operating components within the transistor array may also be fabricated and may or may not be located entirely or partially within the transistor array or sub-array. Further, multiple sub-arrays may also be manufactured and operated independently, in tandem, or otherwise with respect to each other. As used in this disclosure, a "sub-array" may also be considered an array.

The substrate construction 10 includes a transistor 12 including a pair of source/ drain regions 16, 18 with a channel 14 between the source/ drain regions 16, 18. The transistor gate construction 30 is operatively proximate the channel 14. The gate construction 30 includes a conductive gate material 34, such as a conductively-doped semiconductor material and/or a metallic material, and a gate insulator 32, such as silicon dioxide, silicon nitride and/or other high-k dielectrics, ferroelectric materials and/or other programmable materials, and the like. Gate material 34 may include portions of access lines 35 (fig. 2) that interconnect the gates of multiple transistors together in a single row or column. Regardless, in one embodiment, in a rectilinear vertical cross-section (such as the vertical cross-section of fig. 1 and whether presented in a straight pendulum, yaw, or paper plane, or any other rotational orientation of the visual representation in which fig. 1 is situated), the gate construction 30 is located over laterally opposite sides (such as sides 61 and 63) of the channel 14. In one embodiment and as shown, the gate construction 30 completely surrounds the channel 14 in all rectilinear vertical cross-sections, as is inherently common when viewing fig. 1 and 2.

The channel 14 includes a direction 20 (i.e., a direction of current flow) in which current flows through the channel between the source/ drain region pairs 16 and 18. In one embodiment and as shown, the current flow direction 20 is straight at each location between the source/ drain regions 16 and 18 and may be considered a plane (e.g., the page of fig. 1 between the two opposing gate insulators 32 depicted). The channel 14 comprises Si_1-yGe_yWhere "y" is from 0 to 0.6, and in one embodiment, the channels 14 all extend in the current flow direction 20. The channel 14 may comprise Si_1-yGe_yConsisting essentially of Si_1-yGe_yIs composed of or consists of Si_1-yGe_yAnd (4) forming. An example maximum channel length in the current flow direction 20 is 200 to 2,000 angstroms.

At least one of each source/drain region 16, 18Part of comprising Si_1-xGe_xWherein "x" is from 0.5 to 1. For example, source/drain region 16 includes such a portion 26 and source/drain region 18 includes such a portion 28. Portions 26 and 28 may comprise Si_1-xGe_xConsisting essentially of Si_1-xGe_xIs composed of or consists of Si_1-xGe_xAnd (4) forming. In one embodiment, each portion 26 and 28 extends completely through the respective source/drain region orthogonal to current flow direction 20, such as along orthogonal direction 25 (which may be planar, for example), as shown in fig. 1-4. Regardless, in one embodiment and ideally, "x" is greater than "y," and in another embodiment, "x" is equal to "y. In one embodiment, "y" is 0. An example maximum dimension of each source/ drain region 16, 18 in the orthogonal direction 25 is 50 to 2,000 angstroms.

Each source/ drain region 16, 18 includes at least a portion thereof that includes a conductivity enhancing dopant therein having a maximum concentration of such conductivity enhancing dopant within the respective source/ drain region 16, 18, for example, to render such portion conductive (e.g., having at least 10 a)²⁰Atom/cm³Maximum dopant concentration). Accordingly, all or only a portion of each source/ drain region 16, 18 may have such a maximum concentration of conductivity enhancing dopant. Regardless, in one embodiment, each portion 26 and 28 is partially or completely within the maximum concentration dopant portion. Source/ drain regions 16 and 18 may include other doped regions (not shown), such as halo regions, LDD regions, and the like.

The channel 14 may be appropriately doped with conductivity enhancing dopants, which may be of opposite conductivity type to the dopants in the source/ drain regions 16, 18, and, for example, have no more than 1 × 10 in the channel¹⁶Atom/cm³In one embodiment, the channel 14 includes a channel having no more than 1 × 10 therein¹⁴Atom/cm³And in one embodiment, includes an immeasurable amount of conductivity enhancing dopant within channel 14.

In one embodiment and as shown, each source/ drain region 16, 18 comprises Si_1-yGe_y(e.g., Si in the source/drain regions 16)_1-yGe_ySi in portions 22 and source/drain regions 18_1-yGe_yPortion 24), and in one embodiment, Si_1-yGe_ySi directly adjacent to the channel 14_1-yGe_y. Example maximum thickness (e.g., T) of each portion 22 and 24 in current flow direction 20₁) Is between 0 and 200 angstroms and, in one embodiment, is from 2 to 200 angstroms. Portions 22 and 24 may have the same or different thicknesses from one another. In fig. 1-4, a dielectric material 45, such as silicon dioxide and/or silicon nitride, is shown over and on both sides of various operating features. Other materials, regions, and portions (materials not particularly important to the invention) described and shown above may have any suitable respective thicknesses. However, in one embodiment, transistor 12 is a thin film transistor.

FIG. 5 shows an alternative example embodiment of a substrate construction 10a having a transistor 12a in which the source/ drain regions 16 and 18, respectively, are devoid of Si_1-yGe_yThe regions 22, 24 (not shown in fig. 5). Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "a". Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In one embodiment, transistor 12 extends vertically, and in one such embodiment shown, is vertical or within 10 ° of vertical. In particular and in this example, source/drain regions 16 are upper source/drain regions and source/drain regions 18 are lower source/drain regions. The channel 14 extends vertically between the source/ drain regions 16 and 18 and includes a top 36 (i.e., uppermost epitaxy) and a bottom 38 (i.e., lowermost epitaxy). Moreover, in this embodiment, the portion 22 of the upper source/drain region 16 is the lowermost portion thereof and includes a top 40 and a bottom 42, with the bottom 42 directly abutting the top 36 of the channel 14. In one embodiment and as shown, the top 36 of the channel 14 and the bottom 42 of the lowermost portion 22 may be planar and vertically coincident along the orthogonal direction 25. Portion 26 is the uppermost portion of upper source/drain region 16 and includes a top 46 and a bottom 44. In one embodiment, the combination of the source/ drain pair 16, 18 and the channel 14 has an aspect ratio of at least 3: 1.

Portion 24 of lower source/drain region 18 includes its uppermost portion and includes a top 48 and a bottom 50, with top 48, in one embodiment, immediately abutting bottom 38 of channel 14. In one embodiment and as shown, the bottom 38 of the channel 14 and the top 48 of the lowermost portion 22 may be planar and vertically coincident along the orthogonal direction 25. Portion 28 is the lowermost portion of lower source/drain region 18 and includes a top 52 and a bottom 54.

The source/ drain regions 16, 18 and channel 14 are shown as being circular in horizontal cross-section, but other shapes of the various regions (e.g., oval, square, rectangular, triangular, pentagonal, etc.) may be used and need not all be the same shape as one another.

As an alternative example, transistor 12 may not extend vertically, e.g., horizontally. In particular and by way of example, any of fig. 1-4 rotated 90 ° to the right or left depicts a horizontally extending transistor, regardless of the position or composition of the example substrate material 11. In any event, any other properties or aspects shown and/or described herein with respect to other embodiments may be used, whether the transistors are vertically, horizontally, or otherwise oriented.

Next, an alternative example embodiment transistor 12b of substrate construction 10b is described with reference to fig. 6. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "b" or with different numerals. Insulator material regions 60 are located in each source/ drain region 16, 18, and the insulator material regions 60 individually extend orthogonal to the current flow direction 20 (e.g., along orthogonal direction 25) and are no thicker than 10 angstroms (e.g., thickness T) in the current flow direction 20 (e.g., thickness T)₂). In one embodiment, each insulator material region 60 is at least 2 angstroms thick, and in one embodiment, no more than 5 angstroms thick. The insulator material regions 60 may have the same or different thicknesses from one another. In one embodiment, each insulator material region 60 comprises SiO₂. In one embodimentEach insulator material region 60 comprises C, e.g., comprising amorphous carbon and/or Si_xO_yC_z(e.g., where "z" is 1% -10% of the sum of "x", "y" and "z"; where "x" is 25% -33% of the sum of "x", "y" and "z"; and where "y" is 50% -66% of the sum of "x", "y" and "z"; each such percentage is an atomic percent)]). In one embodiment, each insulator material region 60 extends completely through the respective source/ drain region 16, 18 orthogonal to the current flow direction 20 (e.g., along direction 25). Each insulator material region 60 may at least partially serve as a diffusion limiter for conductivity-adjusting dopants between (a) each source/ drain region 16, 18 and (b) the channel 14. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Fig. 6 shows an example embodiment transistor 12b in which each insulator material region 60 is not directly against channel 14. Alternatively, each insulator material region 60 may abut directly against channel 14, such as shown in an alternative embodiment transistor 12c with respect to substrate construction 10c in fig. 7. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "c". As another alternative example, an insulator material region 60 may be directly against the channel 14 and another insulator material region 60 is not directly against the channel 14 (not shown). In any event, any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Fig. 8 shows another example alternate embodiment transistor 12d relative to substrate construction 10 d. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "d". The insulator material region 60 in the transistor 12d is individually located in the channel 14 and directly against one of the source/drain region pairs 16, 18. In one embodiment and as shown, each insulator material region 60 extends completely through channel 14 orthogonal to current flow direction 20 (e.g., along direction 25). Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used. Fig. 9 shows an alternative example of such an embodiment transistor 12e relative to a substrate construction 10 e. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "e". Fig. 9 shows an example in which each insulator material region 60 is located within the channel 14 and extends into one of the respective source/ drain regions 16, 18. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Fig. 10 shows an alternative example embodiment substrate construction 10 f. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "f". The gate construction 30f of the transistor 12f does not completely surround the channel 14f, specifically and alternatively, in the rectilinear vertical cross-section, the gate construction 30f is located only over two laterally opposite sides 61, 63 of the channel 14 f. This may be part of the access line construction 35f, and may or may not be directly electrically coupled together. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Fig. 11 and 12 show yet another alternative example embodiment substrate construction 10g, wherein, in rectilinear vertical cross-section, the gate construction 30g of transistor 12g is located only over a lateral side (e.g., side 61) of channel 14 f. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix "g". Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

In one embodiment, each portion 26 and 28 encompasses all of the respective source/drain regions 16, 18 (e.g., fig. 5 and 8). In one embodiment, each portion 26 and 28 encompasses only a portion of the respective source/drain region 16, 18 (e.g., fig. 1, 6, 7, 9 and 11). In one embodiment, each portion 26 and 28 and the Si therein_1-xGe_xDirectly adjacent to the channel 14 (e.g., fig. 5 and 8). In one embodiment, Si in or on both portions 26 and 28_1-xGe_xNot directly against the channel 14 (e.g., fig. 1, 6, 7, 9, and 11). In this embodiment, each source/ drain region 16, 18 comprises Si_1-yGe_yAnd directly against the Si of the channel 14_1-yGe_y(e.g., FIGS. 1, 6 and 11). In one embodiment, one of portions 26 and 28 and the Si therein_1-xGe_xDirectly against the channel and the other of portions 26 and 28 and the Si therein_1-xGe_xNot directly against the channel (not shown). In one embodiment, the Si of channel 14_1-yGe_yNot extending completely in the current flow direction 20 (e.g., fig. 8 and 9). Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention include transistors (e.g., 12b, 12c, 12d, 12e) that include a pair of source/drain regions (e.g., 16, 18, and whether or not there is any Si within them_1-xGe_x) With a channel (e.g. 14) between the source/drain regions, and with or without any Si_1-yGe_y). The channel includes a direction (e.g., 20) in which current flows through the channel between the source/drain region pair. In one embodiment, an insulator material region (such as 60 in fig. 6, 7 and 9) is located in each source/ drain region 16, 18, and such insulator material regions individually extend orthogonal to the current flow direction (e.g., along direction 25) and are not thicker than 10 angstroms in the current flow direction. In one embodiment, a pair of insulator material regions (such as 60 in fig. 8 and 9) are located in the channel and are each elongated orthogonal to the direction of current flow and are each no thicker than 10 angstroms in the direction of current flow, with the insulator material regions individually abutting directly against one of the source/drain region pairs. Any other attributes or aspects shown and/or described herein with respect to other embodiments may be used.

As described above, incorporation of germanium into one or both of the channel and the source/drain regions may enable activation temperature reduction (i.e., in an annealing step performed to activate the dopant within the source/drain regions and/or the channel). In one embodiment, a method of forming a transistor includes forming a pair of source/drain regions having a channel therebetween. The channel comprises Si_1-yGe_yWherein "y" is from 0 to 0.6. Each source/drain regionAt least a part of which comprises Si_1-xGe_xWherein "x" is from 0.5 to 1. Each source/drain region includes conductivity enhancing dopants therein. The conductivity enhancing dopant in each source/drain region is activated at a temperature of no more than 600 ℃ (and in one embodiment, no more than 550 ℃). Operatively forming a transistor gate construction proximate the channel prior to or subsequent to the act of activating the conductivity enhancing dopant in the source/drain regions. In one embodiment, the channel is crystalline at the beginning of the activation action, and in another embodiment, the channel is amorphous at the beginning of the activation action and becomes crystalline during the activation. In the present invention, a "crystalline" material or state is at least 90% crystalline by volume. In the present invention, an "amorphous" material or state is at least 90% amorphous by volume. Any other attributes with respect to the above structural embodiments may be applied to the method embodiments and vice versa.

In the present invention, unless otherwise indicated, "vertical," "upper," "lower," "top," "bottom," "above," "below," "beneath," "upward" and "downward" generally refer to a vertical direction. "horizontal" refers to a general direction along the main substrate surface (i.e., within 10 °) and may be relative to the substrate processed during fabrication, and "vertical" is a direction that is substantially orthogonal to "horizontal". "substantially horizontal" refers to a direction along the main substrate surface (i.e., at an angle of 0 ° to the main substrate surface) and may be relative to the substrate being processed during fabrication. Further, as used herein, "vertical" and "horizontal" are directions that are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. Additionally, "vertically extending" refers to a direction that is offset from "perfectly horizontal" by at least 45 °. Furthermore, "vertically extending" and "horizontally extending" with respect to the field effect transistor are orientations with reference to the channel length of the transistor along which current flows between the source/drain regions in operation. For a bipolar junction transistor, "vertically extending" and "horizontally extending" are orientations with reference to the length of the substrate along which current flows between the emitter and collector in operation.

Further, "directly above" and "directly below" require that two such regions/materials/components at least partially laterally overlap each other (i.e., horizontally). Furthermore, the use of "over" without "directly above" requires only that some portion of another such region/material/component above that region/material/component be vertically outward of that region/material/component (i.e., regardless of whether there is any lateral overlap of two such regions/materials/components). Similarly, the use of "under" without "directly above requires that some portion of another such region/material/component be vertically inward of the region/material/component (i.e., regardless of whether there is any lateral overlap of two such regions/materials/components).

Any materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event may be continuous or discontinuous over any material it overlies. Moreover, unless otherwise specified, each material may be formed using any suitable or yet to be developed technique (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation).

Additionally, "thickness" itself (the foregoing unoriented adjective) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of a directly adjacent material or region of different composition. In addition, the various materials or regions described herein can have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness unless otherwise indicated, and since the thickness is variable, this material or region will have some minimum thickness and some maximum thickness. As used herein, "different compositions" only require that portions of two such materials or regions that can be in direct proximity to each other be chemically and/or physically different, e.g., such materials or regions are non-homogeneous. If two such materials or regions are not in direct proximity to each other, then the "different compositions" need only be such that the portions of the two such materials or regions that are closest to each other are chemically and/or physically different, e.g., such materials or regions are non-homogeneous. In the present invention, a material, region or structure and another material, region or structure are "directly adjacent to" each other when the materials, regions or structures and the other material, regions or structures are in at least partial physical touching contact with each other. In contrast, "directly over," "on," "adjacent," "along," and "abutting" where not preceded by "directly" encompass "directly abutting" and configurations in which intervening materials, regions, or structures result in the materials, regions, or structures not being in physical touching contact with one another.

Herein, region-material-components are "electrically coupled" to each other if, in normal operation, current is able to continuously flow from such region-material-component to another region-material-component, and when sufficient subatomic positive and/or negative charges are generated, such "electrical coupling" is achieved primarily by moving such subatomic positive and/or negative charges. Another electronic component may be between and electrically coupled to the region-material-component. In contrast, when a region-material-component is considered to be "directly electrically coupled," then no intervening electronic components (e.g., no diodes, transistors, resistors, sensors, switches, fuses, etc.) are interposed between the directly electrically coupled region-material-component.

Additionally, a "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any conductive metal compound.

Summary of the invention

In some embodiments, a transistor includes a pair of source/drain regions with a channel therebetween. A transistor gate construction is operatively proximate the channel. The channel comprises Si_1-yGe_yWherein "y" is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si_1-xGe_xWherein "x" is from 0.5 to 1.

In some embodiments, a transistor includes a pair of source/drain regions with a channel therebetween. A transistor gate construction is operatively proximate the channel. The channel includes a direction in which current flows between the pair of source/drain regions through the channel. An insulator material region is located in each of the source/drain regions. The insulator material regions are individually elongated orthogonal to the current flow direction and are no thicker than 10 angstroms in the current flow direction.

In some embodiments, a transistor includes a pair of source/drain regions with a channel therebetween. A transistor gate construction is operatively proximate the channel. The channel includes a direction in which current flows between the pair of source/drain regions through the channel. A pair of insulator material regions are located in the channel and are each elongated orthogonal to the current flow direction and are each no thicker than 10 angstroms in the current flow direction. The insulator material regions individually directly abut one of the pair of source/drain regions.

In some embodiments, a method of forming a transistor includes: a pair of source/drain regions is formed with a channel therebetween. The channel comprises Si_1-yGe_yWherein "y" is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si_1-xGe_xWherein "x" is from 0.5 to 1. Each of the source/drain regions includes conductivity enhancing dopants therein. Activating the conductivity enhancing dopant in each of the source/drain regions at a temperature not exceeding 600 ℃. A transistor gate construction is formed in operative proximity to the channel.