阅读说明：本技术 测试设备 (Test equipment ) 是由 金珍宇 李昌挥 承万镐 于 2019-10-22 设计创作，主要内容包括：公开了一种测试设备。该测试设备包括：输入/输出(I/O)电路,其被配置为允许在输入/输出(I/O)焊盘与内部电路之间流动的静电被放电至电源线、地线或基板线；电容器电路,其被配置为执行从封装设计中提取的寄生电容的建模；以及放电电路,其被配置为允许在电容器电路中储存的电容被放电至基板线。(A test apparatus is disclosed. The test apparatus includes: an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power supply line, a ground line, or a substrate line; a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design; and a discharge circuit configured to allow the capacitance stored in the capacitor circuit to be discharged to the substrate line.)

1. A test apparatus, comprising:

an input/output I/O circuit configured to allow static electricity flowing between the input/output I/O pad and the internal circuit to be discharged to at least one of the power supply line, the ground line, and the substrate line;

a capacitor circuit configured to perform modeling of parasitic capacitance extracted from the parameter signal; and

a discharge circuit coupled with the substrate line and the capacitor circuit, the discharge circuit configured to allow a capacitance stored in the capacitor circuit to discharge to the substrate line.

2. The test apparatus of claim 1, wherein the capacitor circuit performs modeling of the parasitic capacitance to match an equivalent circuit corresponding to the parameter signal.

3. The test apparatus of claim 1, wherein the capacitor circuit comprises:

a first capacitor coupled between a test line and an input/output line IOL coupled to the input/output I/O pad;

a second capacitor coupled between the substrate line and the test line;

a third capacitor coupled between the ground line and the test line; and

a fourth capacitor coupled between the power line and the test line.

4. The test apparatus of claim 1, wherein the discharge circuit comprises:

a resistor coupled between the substrate line and the capacitor circuit.

5. The test apparatus of claim 4, wherein the resistor comprises a variable resistor.

6. The test apparatus of claim 1, further comprising:

a test pad configured to receive a test signal as an input; and

an inductance circuit coupled between the test pad and the capacitor circuit and configured to perform modeling of inductance parameters.

7. The test apparatus of claim 6, further comprising:

a resistor coupled between the inductive circuit and the capacitor circuit.

8. The test apparatus of claim 1, wherein the test pads are coupled to pogo pins of a semiconductor package.

9. The test apparatus of claim 1, further comprising:

a bias generation circuit configured to provide a bias voltage to the capacitor circuit; and

a switch circuit configured to selectively control a connection between the capacitor circuit and the bias generation circuit.

10. The test apparatus of claim 9, wherein the bias voltage has a Direct Current (DC) level.

11. The test apparatus of claim 9, wherein:

the capacitor circuit is charged by the bias voltage when the switch circuit is closed; and

when the switch circuit is turned off, the voltage stored in the capacitor circuit is discharged to the substrate line through the resistor circuit.

12. The test apparatus of claim 1, wherein the input/output I/O circuit comprises:

a power clamp coupled between the power supply line and the ground line and configured to form a discharge path between the power supply line and the ground line;

a local clamp circuit configured to form a discharge path between the power supply line, the ground line, and an input/output I/O line; and

an electrostatic discharge (ESD) protection circuit coupled between the power line and the ground line and configured to form an ESD path.

13. The test apparatus of claim 12, wherein the input/output I/O circuit further comprises:

a power supply voltage pad configured to supply a power supply voltage to the power supply line;

a ground voltage pad configured to supply a ground voltage to the ground line;

the input/output I/O pad configured to supply an input/output I/O signal to the substrate line; and

a substrate voltage pad configured to supply a substrate voltage to the substrate line.

14. The test apparatus of claim 13,

wherein the power supply line includes a resistor;

wherein the input/output I/O line comprises a resistor; and

wherein the ground line comprises a resistor.

15. A test apparatus, comprising:

a parameter extractor configured to design an equivalent circuit by extracting at least one parasitic parameter from a substrate of a package design and each constituent element of the package design; and

a modeling circuit configured to generate a simulation signal of a charged device model CDM by modeling the parasitic parameters to match the equivalent circuit.

16. The test apparatus of claim 15, wherein the package design comprises:

a die contained in the package molding;

a die metal coupled with the die;

a package substrate electrically isolated from the die metal;

package balls electrically coupled to the package substrate; and

a ground line formed on a surface of the package mold facing the package ball.

17. The test apparatus of claim 16, wherein the parameter extractor is configured to extract a parasitic capacitance from each of the constituent elements by supplying a predetermined voltage to the package design.

18. The test apparatus of claim 15, wherein the modeling circuit comprises:

an input/output I/O circuit configured to allow static electricity flowing between the input/output I/O pad and the internal circuit to be discharged to at least one of a power supply line, a ground line, or a substrate line;

a capacitor circuit configured to perform modeling of parasitic capacitance extracted from the package design; and

a discharge circuit coupled with the substrate line and the capacitor circuit, the discharge circuit configured to allow a capacitance stored in the capacitor circuit to discharge to the substrate line.

19. The test apparatus of claim 18, wherein the capacitor circuit comprises:

a first capacitor coupled between a test line and an input/output line IOL coupled to the input/output I/O pad;

a second capacitor coupled between the substrate line and the test line;

a third capacitor coupled between the ground line and the test line; and

a fourth capacitor coupled between the power line and the test line.

20. The test apparatus of claim 18, wherein the discharge circuit comprises:

a resistor coupled between the substrate line and the capacitor circuit.

Technical Field

Embodiments of the present disclosure may generally relate to a test apparatus, and more particularly, to a technique for testing a semiconductor device.

Background

In general, electrostatic discharge (ESD) may represent a specific state in which a current caused by a large voltage difference between at least two electrically insulated objects momentarily flows in the two objects when the two objects are in contact with each other. Therefore, when a current caused by static electricity flows in an internal circuit of a semiconductor Integrated Circuit (IC), there is a high possibility that serious damage (for example, breakage of an insulating film, breakage of a resistance junction, or the like) is caused in the internal circuit. Therefore, there is a need for an electrostatic discharge (ESD) path in which a current caused by static electricity can flow in an internal circuit of a semiconductor IC without damaging the internal circuit of the semiconductor IC.

Disclosure of Invention

According to an embodiment of the present disclosure, a test apparatus may include: an input/output (I/O) circuit configured to allow static electricity flowing between an input/output (I/O) pad and an internal circuit to be discharged to a power supply line, a ground line, or a substrate line; a capacitor circuit configured to perform modeling of parasitic capacitance extracted from a package design; and a discharge circuit configured to allow the capacitance stored in the capacitor circuit to be discharged to the substrate line.

According to an embodiment of the present disclosure, a test apparatus may include: a parameter extractor configured to design an equivalent circuit by extracting at least one parasitic parameter from a substrate of the package design and each element of the package design; and a modeling circuit configured to generate a simulation signal of a Charged Device Model (CDM) by modeling a parasitic parameter to match the equivalent circuit.

Drawings

Fig. 1 is a block diagram illustrating a test apparatus according to an embodiment of the present disclosure.

Fig. 2 is a detailed circuit diagram illustrating the modeling circuit shown in fig. 1.

Fig. 3 is a block diagram illustrating a parameter extractor shown in fig. 1.

Fig. 4 is a circuit diagram showing an equivalent circuit of the package design shown in fig. 3.

Detailed Description

It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are examples and explanatory and are intended to provide further explanation of the disclosure as claimed.

Reference will now be made in detail to embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Throughout the specification of the present disclosure, if it is assumed that a certain component is connected (or coupled) to another component, the term "connected" or "coupled" means that the certain component is directly connected (or coupled) to the other component and/or is electrically connected (or coupled) to the other component through a third party medium. As used herein with respect to some embodiments, the word "coupled" means that two components are directly connected to each other. For example, a first component coupled with a second component means that the first component contacts the second component. For other embodiments, the coupled components have one or more intermediate components. For example, even if a first component is not in direct contact with a second component, the first component is coupled to the second component when both the first and second components are in contact with a common third component. Throughout the specification of the present disclosure, if it is assumed that a certain component includes a certain component, the term "including" or "comprises" means that the corresponding component may also include other components unless a specific meaning to the contrary is written. As used in the specification and the appended claims, the terms "a", "an", "the" and other similar terms include both the singular and the plural, unless the context clearly dictates otherwise. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Unless the context indicates otherwise, singular expressions may include plural expressions.

Various abnormal patterns may occur in the semiconductor device. In particular, there are abnormal patterns caused by electrical phenomena (e.g., Electrical Overstress (EOS), electrostatic discharge (ESD), etc.).

ESD may refer to an abnormal pattern caused by movement of static electricity, and the static electricity based on ESD may be applied to a diode or a transistor of a semiconductor device such that the function of the diode or the transistor of the semiconductor device is destroyed or destroyed. That is, a high current caused by the ESD phenomenon is applied to a PN junction of the diode, junction spike occurs or a gate insulating film of the transistor is broken, so that a gate terminal, a drain terminal, and a source terminal of the transistor are short-circuited, and the ESD phenomenon may greatly affect reliability of a constituent element (e.g., a diode, a transistor, etc.) of the semiconductor device.

The ESD phenomenon may be classified into a Human Body Model (HBM), a Machine Model (MM), and a Charged Device Model (CDM) according to the cause of static electricity.

For example, a Human Body Model (HBM) may refer to a phenomenon in which static electricity generated from a charged human body is discharged through a constituent element of a semiconductor device so that the constituent element is destroyed or destroyed. The Machine Model (MM) may refer to a phenomenon in which static electricity generated from a charged machine is instantaneously discharged through constituent elements of a semiconductor device, so that the constituent elements are destroyed or destroyed. A Charged Device Model (CDM) may refer to a phenomenon in which static electricity stored in a semiconductor device is simultaneously and instantaneously discharged since the semiconductor device is grounded to an external conductor during a manufacturing process of the semiconductor device, so that constituent elements of the semiconductor device are destroyed or destroyed. CDM means that constituent elements of a semiconductor device are destroyed or destroyed by an electrified semiconductor device, so that reliability of a product may be greatly affected by such CDM. Accordingly, many developers and companies of semiconductor devices are intensively studying techniques for measuring CDM characteristics through charge discharge modeling and securing CDM characteristics desired by users.

Various embodiments of the present disclosure may be directed to providing a test apparatus that substantially obviates one or more problems due to limitations and disadvantages of the related art.

Embodiments of the present disclosure may generally relate to a test apparatus for extracting parasitic parameters from a package design, and may reflect the extracted parasitic parameters into a modeling process to predict Charged Device Model (CDM) stress.

Fig. 1 is a block diagram illustrating a test apparatus 10 according to an embodiment of the present disclosure.

Referring to fig. 1, the test apparatus 10 may include a parameter extractor 100 and a modeling circuit 200.

CDM may greatly affect product reliability. Since CDM can occur unexpectedly at any time during product delivery from the manufacturer to the customer, it is likely to result in defective or malfunctioning products. As a result, many defective or malfunctioning products may occur due to the occurrence of unexpected CDM. CDM testing may be used to identify and confirm characteristics of package coupling structures of semiconductor devices.

If the characteristics of at least one chip are substantially simulated by simulation, there is a difference in size between the package level and the chip layer, so that the amount of resources required for simulation may increase and the consumed time becomes longer. Therefore, important for embodiments of the present disclosure are an extraction process for extracting package-level parasitic parameters that have a great influence on charge and discharge and a modeling process for modeling a package design to be very similar to an actual product structure. Package design refers to the actual semiconductor package manufactured in various forms for predicting the stress exerted on the device.

To this end, the parameter extractor 100 may extract one or more parasitic parameters capable of adequately coping with various ESD-based phenomena according to various package designs. The parameter extractor 100 may extract at least one parasitic parameter affecting the CDM waveform at the packaging level, and may thus generate a parameter signal PARA. For example, parameter extractor 100 may extract the capacitance of the substrate of the package design that is used as a source of CDM stress, and may also extract the capacitance of each pin of the package design.

Modeling circuit 200 may generate a CDM simulation signal SIM by matching NETLIST information to parameter signal PARA. In other words, the modeling circuit 200 may generate a simulation signal SIM in which an actual measurement (measurement) of the package design is simulated by modeling the parameter signal PARA. For example, detailed circuits and operations of the modeling circuit 200 will be described below with reference to the drawings.

Accordingly, embodiments of the present disclosure may compare actual measurement information of capacitance extracted from a package design with a simulation result, and thus may confirm simulation consistency according to the comparison result. That is, how much the parasitic capacitance generated in the semiconductor package during the assembly of the semiconductor package affects the semiconductor device can be tested in advance by a system designer or manager.

When a design circuit is simulated and the simulation circuit does not operate as intended by the system designer, the design circuit may also be changed to another circuit design as needed. As described above, the target circuit may be simulated in advance, and the system designer may recognize in advance whether the target circuit is operating normally before actually manufacturing the target circuit.

In terms of engineering, technology shrinkage (technology shrink) to improve the characteristics of semiconductor devices is important. In contrast, technological shrinkage may reduce metal width, oxide thickness, etc., and may also increase the likelihood of hazards in electrostatic discharge (ESD).

In addition, many developers and companies have researched and developed some package-level technologies from among various technologies for improving product characteristics. Various package structures must affect CDM stress. If a system designer can pretest weak points in CDM stress based on individual package structures, the possibility of causing defective products can be predicted, and the occurrence of such defective products can be prevented in advance.

Accordingly, the test apparatus according to an embodiment of the present disclosure may perform chip-level modeling based on NETLIST information, and may extract various parasitic parameters on a package structure at a package level. As a result, the test apparatus according to the embodiment of the present disclosure can identify not only noise caused by CDM stress but also weak points predicted at a wafer level regardless of a package structure.

Fig. 2 is a detailed circuit diagram illustrating the modeling circuit 200 shown in fig. 1.

Referring to fig. 2, the modeling circuit 200 may include a power supply voltage pad P1, a ground voltage pad P2, an input/output (I/O) pad P3, a substrate voltage pad P4, a test pad P5, a plurality of resistors R1 to R9, a power clamping circuit (power clamping circuit)210, a local clamping circuit 220, an ESD protection circuit 230, a capacitor circuit 240, a discharge circuit 250, a capacitor circuit 260, an inductance circuit 270, a switch circuit 280, and a bias generation circuit 290.

The modeling circuit 200 may include specific circuits including the above-described constituent elements (i.e., the power supply voltage pad P1, the ground voltage pad P2, the I/O pad P3, the substrate voltage pad P4, the resistors R1 to R7, the power supply clamp circuit 210, the local clamp circuit 220, the ESD protection circuit 230, and the capacitor circuit 240). For convenience of description, this specific circuit will be referred to as an input/output circuit (IOC) hereinafter. Hereinafter, the signal extracted by the input/output circuit (IOC) is referred to as "NETLIST".

The modeling circuit 200 may extract NETLIST in which elements interconnected in the input/output circuit (IOC) of the above-described design chip are defined and also a connection relationship of these elements, from the IOC of the above-described design chip. For example, modeling circuit 200 may extract NETLIST based on simulation program with integrated circuit emphasis (SPICE).

In Integrated Circuit (IC) design, various circuit simulation tools may be used. One of the circuit simulation tools may be a program called "SPICE". Modeling circuit 200 may use the SPICE program to extract netlet from an input/output circuit (IOC) implemented as an Integrated Circuit (IC). In other words, the modeling circuit 200 can extract NETLIST including ideal connection relationships of elements and parasitic information of the respective elements at the chip level.

The detailed circuit structure of the modeling circuit 200 will be described below.

The power supply voltage pad P1 may receive the power supply voltage VDD from an external component and may transfer the received power supply voltage VDD to the power supply line PL. The resistors R1-R3 may be coupled with the power line PL.

The ground voltage pad P2 may receive the ground voltage VSS from an external component, and may transfer the received ground voltage VSS to the ground line GL. The resistors R5-R7 may be coupled to the ground line GL.

The I/O pad P3 may be coupled to an external I/O pin such that the I/O pad P3 may transmit an input/output (I/O) signal IO to an input/output line (IOL). The resistor R4 may be coupled between the I/O pad P3 and the internal circuitry 201.

Substrate voltage pad P4 may transmit substrate voltage PSUB to substrate line PSUBL. Because the package design includes a silicon substrate (e.g., a P-type silicon substrate), a substrate voltage PSUB may be applied to substrate line PSUBL to simulate parasitic parameters corresponding to the silicon substrate into the modeling process.

The test pad P5 may transmit the test signal TS to the test line TL. For example, the test pad P5 may be a pad coupled with a pogo pin (pogo pin) used in a semiconductor package. In one embodiment, the test pad P5 may be used to exchange electrical signals between a socket board (not shown) and a semiconductor package. Resistor R9 may be coupled to test line TL.

The power clamp 210 may be used to form a discharge path between two power lines. The power clamp circuit 210 may allow the constant power supply voltage VDD and the ground voltage VSS to remain unchanged, and thus the power clamp circuit 210 may prevent or mitigate the charges stored in the internal circuit 201 from being discharged to the outside, so that the internal circuit 201 is not damaged. The power clamp 210 may be coupled between the power line PL and the ground line GL, and thus the power clamp 210 may clamp a power voltage applied to the power line PL and the ground line GL. In one embodiment, the power clamp circuit 210 may be coupled between the power line PL and the ground line GL, and configured to form a discharge path between the power line PL and the ground line GL.

Local clamp 220 may be coupled between power line PL and ground line GL such that local clamp 220 may clamp a power supply voltage applied to an input/output line (IOL). The local clamp 220 may include a first clamp 221 and a second clamp 222. In one embodiment, local clamp 220 may be configured to form a discharge path between power line PL, ground line GL, and input/output (I/O) line IOL.

For example, the first clamping circuit 221 may be coupled between the power line PL and the I/O line (IOL) such that the first clamping circuit 221 may clamp a power voltage applied to the power line and the I/O line (IOL). The second clamping circuit 222 may be coupled between the I/O line (IOL) and the ground line GL such that the second clamping circuit 222 may clamp a power supply voltage applied to the I/O line (IOL) and the ground line GL.

The ESD protection circuit 230 may prevent or reduce electrostatic discharge to the internal circuit 201, or may prevent or reduce electrostatic discharge from the internal circuit 201 to the outside through the I/O pad P3. The ESD protection circuit 230 may be coupled between the power line PL and the ground line GL, resulting in an ESD path. Accordingly, the ESD protection circuit 230 can allow a current caused by static electricity to flow in the internal circuit 201 without damaging the internal circuit 201. The ESD protection circuit 230 may include a first discharge protection circuit 231 and a second discharge protection circuit 232.

For example, the first discharge protection circuit 231 may be coupled between the power line PL and an I/O line (IOL). The first discharge protection circuit 231 may form an ESD path in each of the I/O line (IOL) and the power line PL upon receiving static electricity from the I/O pad P3. The second discharge protection circuit 232 may be coupled between an I/O line (IOL) and the ground line GL. The second discharge protection circuit 232 may form an ESD path in an I/O line (IOL) and a ground line GL when receiving static electricity from the I/O pad P3.

Capacitor circuit 240 may perform modeling of at least one parasitic parameter on substrate line PSUBL. The capacitor circuit 240 may include a plurality of capacitors C1-C3.

For example, capacitor C1 may be coupled between an I/O line (IOL) and substrate line PSUBL. The capacitor C1 may perform modeling of at least one parasitic capacitance of a metal line through which signals are input to and output from the package die.

The capacitor C2 may be coupled between the ground line GL and the substrate line PSUBL. The capacitor C2 may perform modeling regarding parasitic capacitance of a ground voltage among power voltages from the package dies.

The capacitor C3 may be coupled between the power supply line PL and the substrate line PSUBL. The capacitor C3 may perform modeling of a power-supply voltage (power-supply voltage) among power voltages (power voltages) from the packaged die.

Discharge circuit 250 may be coupled between substrate line PSUBL and capacitor circuit 260. Discharge circuit 250 may include a resistor R8, the resistor R8 coupled between capacitor circuit 260 and substrate line PSUBL. For example, the resistor R8 may be a variable resistor having a variable resistance. Since variable resistor R8 has a variable resistance, discharge circuit 250 can form a discharge path in the direction from capacitor circuit 260 to substrate line PSUBL.

In response to the parameter signal PARA extracted from the parameter extractor 100, the capacitor circuit 260 may perform a modeling of at least one parasitic parameter generated at the package level. For example, test line TL may be coupled to capacitor circuit 260.

To perform CDM simulation, the main parameter for such modeling may be set to capacitance. Various parameters having influence on the wavelength of the current and voltage used in each circuit, for example, RLC { resistance (R), inductance (L), and capacitance (C) }, may be used. Since the duration required to extract and verify all parameters is increased, the capacitance can be set as the main parameter required for modeling. Therefore, in order to perform modeling of the same conditions as in CDM noise generated at the package level, a test device according to an embodiment may arbitrarily simulate one or more parasitic parameters into the modeling using the capacitor circuit 260.

Upon receiving the parameter signal PARA, the capacitor circuit 260 may use the capacitance to perform modeling of parasitic components resulting from various elements of the package design. The capacitor circuit 260 may include a plurality of capacitors C4 to C7, each having characteristics similar to those of an actual chip, so the capacitor circuit 260 may perform modeling of a package design.

For example, capacitor C4 may be coupled between an I/O line (IOL) and test line TL. The capacitor C4 may perform modeling of parasitic capacitance of a metal line of the package die through which a signal is input and output.

Capacitor C5 may be coupled between substrate line PSUBL and test line TL. Capacitor C5 may perform modeling of parasitic capacitance with respect to the substrate voltage of the packaged die.

The capacitor C6 may be coupled between the ground line GL and the test line TL. The capacitor C6 may perform modeling regarding parasitic capacitance of a ground voltage among power voltages from the package dies.

The capacitor C7 may be coupled between the power line PL and the test line TL. The capacitor C7 may perform modeling regarding parasitic capacitance of the supply voltage among the power voltages from the package dies.

The inductive circuit 270 may be coupled between the test pad P5 and the resistor R9 such that the inductive circuit 270 may perform modeling of one or more inductance parameters. The inductive circuit 270 may include an inductor (I) for modeling an inductive component of the Test Signal (TS) received from the test pad P5. In response to the Test Signal (TS), the inductor (I) may perform a modeling of one or more inductive components generated in the physical structure of the test device.

The switching circuit 280 may include a Switch (SW) for selectively controlling the connection between the capacitor circuit 260 and the bias generation circuit 290. The switching circuit 280 may selectively transfer the BIAS voltage (BIAS) generated from the BIAS generation circuit 290 to the capacitor circuit 260.

For example, when the switch circuit 280 is closed, the capacitors C4-C7 of the capacitor circuit 260 may be charged by a BIAS voltage (BIAS). For example, when the switching circuit 280 is turned off, the voltage charged through the capacitor circuit 260 may be discharged to the substrate line PSUBL through the resistor R8.

The BIAS generation circuit 290 may be coupled between the switching circuit 280 and the capacitor circuit 260, resulting in a BIAS voltage (BIAS) having a Direct Current (DC) level. The BIAS generation circuit 290 may selectively communicate a BIAS voltage (BIAS) to the capacitor circuit 260.

As described above, the test apparatus according to the embodiment of the present disclosure may analyze wafer-level weak points caused by CDM stress, and may predict CDM stress regardless of the type and structure of a package design.

Fig. 3 is a block diagram illustrating the parameter extractor 100 shown in fig. 1.

To perform the simulation process, an example of a package design of the parameter extractor 100 simulated by the modeling circuit 200 is shown in FIG. 3. Referring to fig. 3, a package design may include a die 520 and a die metal 530 in a package molding 510. For example, the die metal 530 may be electrically coupled with the die 520. Package substrate 550 may be electrically coupled to package balls 540 through one or more vias. For example, the package substrate 550 may be formed of a silicon substrate. The ground line 500 may be formed at a surface facing the package ball 540.

In order to perform the CDM test, the test apparatus according to an embodiment of the present disclosure may allow the package to be charged with a predetermined voltage, so that the test apparatus may extract a capacitance from each element of the package. The package design may be altered in various ways and the parasitic capacitances may be extracted from the various elements using simulation tools for each package design. The parasitic capacitances extracted from the parameter extractor 100 can be simulated by modeling the design of the circuit 200. The word "predetermined" as used herein with respect to a parameter, such as a predetermined voltage, means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the values of the parameters are determined before the process or algorithm begins. In other embodiments, the values of the parameters are determined during the process or algorithm but before the parameters are used in the process or algorithm.

For example, although the die 520 is present in the package molding 510 in the process of extracting parasitic capacitance from the package design as shown in fig. 3, bumps and wires required to interconnect the package substrate 550 and the die metal 530 may be removed as shown in (a) of fig. 3. Thus, the die metal 530 and the package substrate 550 may be electrically isolated from each other.

In the above case, the power supply voltage may be applied to the parameter extractor 100 through the package ball 540, and the ground voltage may be applied to the parameter extractor 100 through the ground line 500. As a result, the respective elements of the package may be floated, so that parasitic capacitance may occur between the respective elements.

Fig. 4 is a circuit diagram showing an equivalent circuit of the package design shown in fig. 3.

The parasitic capacitance matching each element of the package design shown in fig. 3 can be represented by the equivalent circuit shown in fig. 4. In the equivalent circuit of fig. 4, metal lines 600, 610, and 620 may be electrically coupled to package balls 540 of a package design. The equivalent circuit of each parasitic capacitance can be easily changed in various ways according to the layout of the metal lines of the package design.

In the equivalent circuit, the capacitor C44 may refer to a parasitic capacitance occurring between the metal line 600 and the ground line 500. In an equivalent circuit, capacitor C45 may refer to the parasitic capacitance that occurs between metal line 610 and die metal 530. The parasitic capacitance of capacitors C44 and C45 may be modeled as shown by capacitor C4 of fig. 2.

In an equivalent circuit, capacitor C55 may refer to the parasitic capacitance that occurs between die metal 530 and ground 500. The parasitic capacitance of capacitor C55 may be modeled as shown by capacitor C5 of fig. 2.

In an equivalent circuit, the capacitor C66 may refer to the parasitic capacitance that occurs between the metal line 610 and the die metal 530. In the equivalent circuit, the capacitor C67 may refer to a parasitic capacitance occurring between the metal line 620 and the ground line 500. The parasitic capacitance of capacitors C66 and C67 may be modeled as shown by capacitor C6 of fig. 2.

In an equivalent circuit, the capacitor C68 may refer to the parasitic capacitance that occurs between the metal line 610 and the die metal 530. The parasitic capacitance of capacitor C68 may be modeled as shown by capacitor C7 of fig. 2.

As described above, the test apparatus according to the embodiment of the present disclosure may extract parasitic capacitance generated from each element of an actual package design using the parameter extractor 100, and thus may simulate characteristics of the actual package by the modeling circuit 200.

As is apparent from the above description, a test apparatus according to an embodiment of the present disclosure may improve accuracy of a Charged Device Model (CDM) waveform, and may predict Charged Device Model (CDM) stress.

Those skilled in the art will appreciate that the embodiments may be practiced in other specific ways than those set forth herein without departing from the spirit and essential characteristics of the present disclosure. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive. The scope of the present disclosure should be determined by the appended claims and their legal equivalents, rather than by the descriptions above. Furthermore, all changes which come within the meaning and range of equivalency of the appended claims are intended to be embraced therein. In addition, it is obvious to those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be combined to present an embodiment or may be included as a new claim through subsequent amendment after the application is filed.

While a number of illustrative embodiments have been described, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. In particular, many variations and modifications are possible in the component parts and/or arrangements of the subject disclosure within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Reference to each element in the figures

100: parameter extractor

200: modeling circuit