阅读说明：本技术 兼容cmos工艺的体声波谐振器及其制造方法 (Bulk acoustic wave resonator compatible with CMOS (complementary Metal oxide semiconductor) process and manufacturing method thereof ) 是由 吴明 唐兆云 杨清华 赖志国 王家友 于 2020-04-20 设计创作，主要内容包括：一种兼容CMOS工艺的体声波谐振器及其制造方法,该谐振器包括：压电膜阵列,包括在衬底与盖帽层之间的多个压电膜,垂直方向上相邻压电膜之间、压电膜与盖帽层之间以及压电膜与衬底之间具有多个第一空腔,水平第一方向上相邻压电膜之间具有共用的第二空腔,水平第二方向上相邻压电膜之间具有共用的第三空腔；多个电极层,至少覆盖每个压电膜的顶面和底面；多个电极互连层,沿第三空腔侧面连接压电膜底面的电极层；驱动晶体管位于盖帽层中,漏极电连接顶部压电膜的顶部电极层；驱动晶体管的源极和漏极上具有欧姆接触层。本发明采用CMOS兼容工艺,并通过离子深注入形成电连接压电膜顶部电极的驱动电路,减小了封装体积,降低了界面电阻。(A bulk acoustic wave resonator compatible with CMOS process and a method for manufacturing the same, the resonator comprising: the piezoelectric film array comprises a plurality of piezoelectric films between a substrate and a cap layer, wherein a plurality of first cavities are formed between the adjacent piezoelectric films in the vertical direction, between the piezoelectric films and the cap layer and between the piezoelectric films and the substrate, a shared second cavity is formed between the adjacent piezoelectric films in the horizontal first direction, and a shared third cavity is formed between the adjacent piezoelectric films in the horizontal second direction; a plurality of electrode layers covering at least the top and bottom surfaces of each piezoelectric film; a plurality of electrode interconnection layers connected to the electrode layer on the bottom surface of the piezoelectric film along the side surfaces of the third cavity; the driving transistor is positioned in the cap layer, and the drain electrode is electrically connected with the top electrode layer of the top piezoelectric film; the source and drain electrodes of the driving transistor have ohmic contact layers thereon. The invention adopts CMOS compatible technology and forms a driving circuit electrically connected with the top electrode of the piezoelectric film by ion deep injection, thereby reducing the packaging volume and reducing the interface resistance.)

1. A CMOS process compatible Bulk Acoustic Wave (BAW) resonator, comprising:

the piezoelectric film array comprises a plurality of piezoelectric films between a substrate and an upper cover cap layer of the chip, wherein a plurality of first cavities are formed among the adjacent piezoelectric films in the vertical direction, between the piezoelectric films and the cover cap layer and between the piezoelectric films and the substrate, a common second cavity is formed among the adjacent piezoelectric films in the horizontal first direction, and a common third cavity is formed among the adjacent piezoelectric films in the horizontal second direction;

a plurality of electrode layers covering at least the top and bottom surfaces of each piezoelectric film;

a plurality of electrode interconnection layers connected to the electrode layer on the bottom surface of the piezoelectric film along the side surfaces of the third cavity;

the driving transistor is positioned in the cap layer, and the drain electrode of the driving transistor is electrically connected with the top electrode layer of the top piezoelectric film;

wherein the source and drain electrodes of the driving transistor have ohmic contact layers thereon.

2. The CMOS process compatible BAW resonator of claim 1, wherein each first cavity has an electrode layer, a first isolation layer, and an electrode interconnect layer between the common third cavity; optionally, an electrode layer and a second separator layer surround each first cavity; optionally, an interlayer dielectric layer and a contact plug in the interlayer dielectric layer are further arranged above the driving transistor, preferably, an intermetallic dielectric layer and a rewiring layer are arranged above the interlayer dielectric layer, and preferably, the depth of the interlayer dielectric layer extending into the second cavity and the third cavity is less than or equal to 1/3 of the thickness of the cap layer.

3. A CMOS process compatible BAW resonator as claimed in claim 1 or 2, wherein the substrate and/or capping layer material is selected from the group consisting of bulk Si, silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and capping layer materials are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the ohmic contact layer is a metal silicide or a metal germanide; optionally, the interlevel dielectric layer is a low-k material.

4. A method of fabricating a CMOS process compatible Bulk Acoustic Wave (BAW) resonator, comprising the steps of:

forming a plurality of sacrificial layers and a plurality of piezoelectric layers alternately stacked on a substrate;

forming a cap layer on the sacrificial layer at the top, and forming a hard mask on the cap layer;

sequentially etching the layers until the substrate is exposed to form a plurality of first openings extending along a first direction;

forming a first isolation layer in each opening;

etching until the substrate is exposed, and forming a plurality of second openings extending along a second direction;

removing the plurality of sacrificial layers through the second openings, and leaving a plurality of first cavities between the adjacent piezoelectric layers, between the piezoelectric layers and the capping layer, and between the piezoelectric layers and the substrate;

forming a plurality of electrode layers at least on the top surface and the bottom surface of the piezoelectric layer through the second openings;

forming an electrode interconnection layer connecting bottom electrodes of the piezoelectric layers in the first openings;

forming a drive transistor in the cap layer, wherein a drain of the drive transistor is electrically connected to the top electrode layer of the top piezoelectric layer;

an ohmic contact layer is formed on the source/drain electrodes of the driving transistor.

5. The CMOS process compatible BAW resonator manufacturing method of claim 4, wherein an electrode layer, a first isolation layer and an electrode interconnection layer are formed between each first cavity and the common third cavity; optionally, forming an electrode layer and a second separator layer surrounding each first cavity; optionally, an interlayer dielectric layer and a contact plug in the interlayer dielectric layer are further formed on the driving transistor, further preferably, an intermetallic dielectric layer and a rewiring layer are formed on the interlayer dielectric layer, and preferably, the depth of the interlayer dielectric layer extending into the second cavity and the third cavity is less than or equal to 1/3 of the thickness of the cap layer.

6. A method of fabricating a CMOS process compatible BAW resonator as claimed in claim 4 or 5, wherein the substrate and/or capping layer material is selected from the group consisting of bulk Si, silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and capping layer materials are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the ohmic contact layer is a metal silicide or a metal germanide; optionally, the interlevel dielectric layer is a low-k material.

7. The method of fabricating a CMOS process compatible BAW resonator of claim 4, wherein the first anneal is performed to form the shallower source region and the deeper drain region using a mask selective ion implantation process.

8. The CMOS process compatible BAW resonator manufacturing method of claim 7, wherein the process of forming the ohmic contact layer comprises:

a) forming a metal layer on the source region and the drain region, and performing second annealing to enable the metal layer to react with the semiconductor material of the cap layer to form metal silicide or metal germanide, wherein the metal layer is preferably W, Co, Pt, Ti, Ni and Ta; or

b) And performing ion implantation to form a source drain region, and simultaneously forming an ohmic contact layer in situ, wherein the ohmic contact layer is preferably silicide or germanide of W, Co, Pt, Ti, Ni and Ta.

9. The CMOS process compatible BAW resonator manufacturing method of claim 8, wherein the step a) further comprises:

step a1), low-temperature annealing is carried out at a first temperature so that the metal layer reacts with the semiconductor material of the cap layer to form a silicon-rich or germanium-rich compound;

step a2), performing a high temperature anneal at a second temperature to convert the silicon-rich or germanium-rich compound to a low resistivity state, wherein the second temperature is higher than the first temperature.

Preferably, the annealing of step a2) is performed in combination with the aforementioned first annealing;

preferably, the first temperature is below 450 degrees celsius and the second temperature is 450 to 650 degrees celsius.

10. The CMOS process-compatible BAW resonator manufacturing method according to claim 8, wherein the step b) includes that the target material for ion implantation is a compound of the implanted ions and the metal contained in the ohmic contact layer; preferably, the implanted ions are As, P, Sb and B, and the metal is W, Co, Pt, Ti, Ni and Ta; preferably, a first mass analyzer is used for selecting the implanted ions to perform vertical ion implantation, and a second mass analyzer is used for alternately selecting the metal ions to be obliquely guided to the surface of the source drain region; preferably, the energy of the implanted ions is greater than the energy of the metal ions.

Technical Field

The invention relates to a CMOS (complementary metal oxide semiconductor) process compatible Bulk Acoustic Wave (BAW) resonator and a manufacturing method thereof.

Background

In wireless communication, the rf filter is used as an intermediary for filtering signals with specific frequencies, and is used to reduce signal interference in different frequency bands, and to implement functions such as image cancellation, spurious filtering, and channel selection in the wireless transceiver. With the deployment of 4GLTE networks and the growth of the market, the design of the radio frequency front end is developing towards miniaturization, low power consumption and integration, and the market has higher and higher requirements on filtering performance. Because the film bulk acoustic resonator (FBAR, also called bulk acoustic wave, or "BAW") has the characteristics of small size, high working frequency, low power consumption, high quality factor (Q value), direct output of frequency signals, compatibility with CMOS process, etc., it has become an important device in the field of radio frequency communication and is widely used at present.

FBAR is a thin film device with a sandwich structure of electrodes-piezoelectric film-electrodes fabricated on a substrate material. The FBAR has a structure of a cavity type, a bragg reflection type (SMR), and a back surface etching type. The Q value of the cavity type FBAR is higher than that of the SMR type FBAR, the loss is small, and the electromechanical coupling coefficient is high; compared with the back etching FBAR, the back etching FBAR does not need to remove a large-area substrate, and has higher mechanical strength. Therefore, the cavity FBAR is the first choice for integration in CMOS devices.

However, due to the complexity of manufacturing, existing BAW filters and Bulk Acoustic Resonators (BARs) are manufactured as independent planar or two-dimensional (2D) layout devices. That is, the BAW filter and the Bulk Acoustic Resonator (BAR) are not provided as structures integrated with other CMOS, bicmos, SiGe HBT and/or passive devices, thereby resulting in higher manufacturing costs and increased manufacturing processes.

In addition, the 2D BAW resonator as an independent device has large volume and area and low integration level, is difficult to be manufactured on the same chip with a driving circuit thereof by adopting a CMOS process, and is further difficult to be integrated with 3D devices such as a FinFET and a NAND memory. If a plurality of 2D BAW resonators are stacked together by using a 3D packaging technology, although the integration level can be effectively improved, each chip needs to use bonding (bonding), grinding (grinding) and Through Silicon Via (TSV) technologies to reduce the packaging height, the process is complicated, extremely high alignment precision is required, and the manufacturing cost is high. In addition, such a 3D package has problems of complicated wiring and large parasitic impedance.

Disclosure of Invention

It is therefore an object of the present invention to provide a CMOS process compatible BAW resonator and a method of fabricating the same that overcomes the above technical obstacles.

The invention provides a Bulk Acoustic Wave (BAW) resonator compatible with a CMOS process, which comprises:

the piezoelectric film array comprises a plurality of piezoelectric films between a substrate and an upper cover cap layer of the chip, wherein a plurality of first cavities are formed among the adjacent piezoelectric films in the vertical direction, between the piezoelectric films and the cover cap layer and between the piezoelectric films and the substrate, a common second cavity is formed among the adjacent piezoelectric films in the horizontal first direction, and a common third cavity is formed among the adjacent piezoelectric films in the horizontal second direction;

a plurality of electrode layers covering at least the top and bottom surfaces of each piezoelectric film;

a plurality of electrode interconnection layers connected to the electrode layer on the bottom surface of the piezoelectric film along the side surfaces of the third cavity;

the driving transistor is positioned in the cap layer, and the drain electrode of the driving transistor is electrically connected with the top electrode layer of the top piezoelectric film;

wherein the source and drain electrodes of the driving transistor have ohmic contact layers thereon.

Wherein, an electrode layer, a first isolation layer and an electrode interconnection layer are arranged between each first cavity and the shared third cavity; optionally, an electrode layer and a second separator layer surround each first cavity; optionally, an interlayer dielectric layer and a contact plug in the interlayer dielectric layer are further arranged above the driving transistor, preferably, an intermetallic dielectric layer and a rewiring layer are arranged above the interlayer dielectric layer, and preferably, the depth of the interlayer dielectric layer extending into the second cavity and the third cavity is less than or equal to 1/3 of the thickness of the cap layer.

Wherein the substrate and/or cap layer material is selected from the group consisting of silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and cap layer material are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the ohmic contact layer is a metal silicide or a metal germanide; optionally, the interlevel dielectric layer is a low-k material.

The invention also provides a manufacturing method of the Bulk Acoustic Wave (BAW) resonator compatible with the CMOS process, which comprises the following steps:

forming a plurality of sacrificial layers and a plurality of piezoelectric layers alternately stacked on a substrate;

forming a cap layer on the sacrificial layer at the top, and forming a hard mask on the cap layer;

sequentially etching the layers until the substrate is exposed to form a plurality of first openings extending along a first direction;

forming a first isolation layer in each opening;

etching until the substrate is exposed, and forming a plurality of second openings extending along a second direction;

removing the plurality of sacrificial layers through the second openings, and leaving a plurality of first cavities between the adjacent piezoelectric layers, between the piezoelectric layers and the capping layer, and between the piezoelectric layers and the substrate;

forming a plurality of electrode layers at least on the top surface and the bottom surface of the piezoelectric layer through the second openings;

forming an electrode interconnection layer connecting bottom electrodes of the piezoelectric layers in the first openings;

forming a drive transistor in the cap layer, wherein a drain of the drive transistor is electrically connected to the top electrode layer of the top piezoelectric layer;

an ohmic contact layer is formed on the source/drain electrodes of the driving transistor.

Wherein an electrode layer, a first isolation layer and an electrode interconnection layer are formed between each first cavity and the common third cavity; optionally, forming an electrode layer and a second separator layer surrounding each first cavity; optionally, an interlayer dielectric layer and a contact plug in the interlayer dielectric layer are further formed on the driving transistor, further preferably, an intermetallic dielectric layer and a rewiring layer are formed on the interlayer dielectric layer, and preferably, the depth of the interlayer dielectric layer extending into the second cavity and the third cavity is less than or equal to 1/3 of the thickness of the cap layer.

Wherein the substrate and/or cap layer material is selected from the group consisting of silicon-on-insulator (SOI), bulk Ge, GeOI, GaN, GaAs, SiC, InP, GaP, and preferably the substrate and cap layer material are the same; optionally, the electrode layer and/or electrode interconnect layer material is a simple metal selected from Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, alloys of these metals, conductive oxides or conductive nitrides of these metals, and any combination thereof; optionally, the piezoelectric film is made of ZnO, AlN, BST, BT, PZT, PBLN, PT; optionally, the material of the first barrier layer and/or the second barrier layer is SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBSG or any combination thereof, and preferably the first barrier layer and the second barrier layer are the same material; optionally, the ohmic contact layer is a metal silicide or a metal germanide; optionally, the interlevel dielectric layer is a low-k material.

Wherein a mask selective ion implantation process is utilized and a first anneal is performed to form a shallower source region and a deeper drain region.

The process for forming the ohmic contact layer comprises the following steps:

a) forming a metal layer on the source region and the drain region, and performing second annealing to enable the metal layer to react with the semiconductor material of the cap layer to form metal silicide or metal germanide, wherein the metal layer is preferably W, Co, Pt, Ti, Ni and Ta; or

b) And performing ion implantation to form a source drain region, and simultaneously forming an ohmic contact layer in situ, wherein the ohmic contact layer is preferably silicide or germanide of W, Co, Pt, Ti, Ni and Ta.

Wherein step a) further comprises:

step a1), low-temperature annealing is carried out at a first temperature so that the metal layer reacts with the semiconductor material of the cap layer to form a silicon-rich or germanium-rich compound;

step a2), performing a high temperature anneal at a second temperature to convert the silicon-rich or germanium-rich compound to a low resistivity state, wherein the second temperature is higher than the first temperature.

Preferably, the annealing of step a2) is performed in combination with the aforementioned first annealing;

preferably, the first temperature is below 450 degrees celsius and the second temperature is 450 to 650 degrees celsius.

Wherein, the step b) comprises that the target material for ion implantation is a compound of implanted ions and metal contained in the ohmic contact layer; preferably, the implanted ions are As, P, Sb and B, and the metal is W, Co, Pt, Ti, Ni and Ta; preferably, a first mass analyzer is used for selecting the implanted ions to perform vertical ion implantation, and a second mass analyzer is used for alternately selecting the metal ions to be obliquely guided to the surface of the source drain region; preferably, the energy of the implanted ions is greater than the energy of the metal ions.

According to the BAW resonator and the manufacturing method thereof, the three-dimensional resonator with the plurality of cavities surrounding the piezoelectric film is manufactured by adopting a CMOS compatible process, and the driving circuit electrically connected with the top electrode of the piezoelectric film is formed in the top cap layer through ion deep implantation, so that the packaging volume is reduced, and the interface resistance is reduced.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.

Drawings

The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:

FIG. 1A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, FIG. 1B shows a cross-sectional view taken along line B-B 'of FIG. 1A, and FIG. 1C shows a cross-sectional view taken along line A-A' of FIG. 1A;

fig. 2A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 2B is a cross-sectional view taken along line B-B 'of fig. 2A, and fig. 2C is a cross-sectional view taken along line a-a' of fig. 2A;

fig. 3A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 3B is a cross-sectional view taken along line B-B 'of fig. 3A, and fig. 3C is a cross-sectional view taken along line a-a' of fig. 3A;

fig. 4A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 4B is a cross-sectional view taken along line B-B 'of fig. 4A, and fig. 4C is a cross-sectional view taken along line a-a' of fig. 4A;

fig. 5A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 5B is a sectional view taken along line B-B 'of fig. 5A, and fig. 5C is a sectional view taken along line a-a' of fig. 5A;

fig. 6A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 6B shows a cross-sectional view taken along line B-B 'of fig. 6A, and fig. 6C shows a cross-sectional view taken along line a-a' of fig. 6A;

fig. 7A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 7B shows a cross-sectional view taken along line B-B 'of fig. 7A, and fig. 7C shows a cross-sectional view taken along line a-a' of fig. 7A;

fig. 8A is a plan view illustrating a process of manufacturing a resonator according to an embodiment of the present invention, fig. 8B is a sectional view taken along line B-B 'of fig. 8A, and fig. 8C is a sectional view taken along line a-a' of fig. 8A;

fig. 9A shows a plan view of a resonator manufacturing process according to an embodiment of the present invention, fig. 9B shows a cross-sectional view taken along line B-B 'of fig. 9A, and fig. 9C shows a cross-sectional view taken along line a-a' of fig. 9A;

fig. 10A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 10B is a sectional view taken along line B-B 'of fig. 10A, and fig. 10C is a sectional view taken along line a-a' of fig. 10A;

fig. 11A is a plan view illustrating a process of manufacturing a resonator according to an embodiment of the present invention, fig. 11B is a sectional view taken along line B-B 'of fig. 11A, and fig. 11C is a sectional view taken along line a-a' of fig. 1A;

fig. 12A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 12B is a sectional view taken along line B-B 'of fig. 12A, and fig. 12C is a sectional view taken along line a-a' of fig. 12A;

fig. 13A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 13B is a sectional view taken along line B-B 'of fig. 13A, and fig. 13C is a sectional view taken along line a-a' of fig. 13A;

fig. 14A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 14B is a sectional view taken along line B-B 'of fig. 14A, and fig. 14C is a sectional view taken along line a-a' of fig. 14A;

fig. 15A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 15B is a sectional view taken along line B-B 'of fig. 15A, and fig. 15C is a sectional view taken along line a-a' of fig. 1A;

fig. 16A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 16B is a sectional view taken along line B-B 'of fig. 16A, and fig. 16C is a sectional view taken along line a-a' of fig. 16A;

fig. 17A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 17B is a sectional view taken along line B-B 'of fig. 17A, and fig. 17C is a sectional view taken along line a-a' of fig. 17A;

fig. 18A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 18B is a sectional view taken along line B-B 'of fig. 18A, and fig. 18C is a sectional view taken along line a-a' of fig. 18A;

fig. 19A is a plan view showing a process of manufacturing a resonator according to an embodiment of the present invention, fig. 19B is a sectional view taken along line B-B 'of fig. 19A, and fig. 19C is a sectional view taken along line a-a' of fig. 19A;

fig. 20A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 20B is a sectional view taken along line B-B 'of fig. 20A, and fig. 20C is a sectional view taken along line a-a' of fig. 20A;

fig. 21A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 21B is a sectional view taken along line B-B 'of fig. 21A, and fig. 21C is a sectional view taken along line a-a' of fig. 21A;

FIG. 22 shows a cross-sectional view along line B-B' of a resonator fabrication process according to an embodiment of the present invention;

fig. 23A is a plan view showing a resonator manufacturing process according to an embodiment of the present invention, fig. 23B is a sectional view taken along line B-B 'of fig. 23A, and fig. 23C is a sectional view taken along line a-a' of fig. 23A; and

fig. 24 shows a cross-sectional view taken along line B-B' of a resonator manufacturing process according to an embodiment of the present invention.

Detailed Description

The features and technical effects of the technical scheme of the invention are explained in detail below with reference to the accompanying drawings and the exemplary embodiments, and a CMOS process compatible BAW resonator and a method for manufacturing the same are disclosed. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.

As shown in fig. 1A to 1C, a stacked structure including at least one sacrificial layer 11A to 11B (which may be N +1, N is a natural number) and at least one piezoelectric layer 12A (which may be N, N is a natural number) stacked alternately in this order from bottom to top is formed on a substrate 10A, wherein the number of sacrificial layers is preferably one more than the number of piezoelectric layers. In an embodiment of the invention, only one piezoelectric layer 12A is shown, but other embodiments of the invention are not limited thereto and more piezoelectric layer stacks may be formed. The substrate 10A may be bulk Si or silicon-on-insulator (SOI) or bulk Ge, GeOI to be compatible with CMOS processes and integrated with other digital and analog circuits, a compound semiconductor for MEMS, photoelectric devices, power devices such as GaN, GaAs, SiC, InP, GaP, etc., and a transparent insulating material for display panels such as glass, plastic, sapphire, etc. In a preferred embodiment of the present invention, the substrate 10A is a single crystal such as bulk Si to facilitate epitaxial growth of the stacked structure above.

At least one sacrificial layer 11A-11B (the number is not limited to 2, but N +1, N being a natural number) and at least one piezoelectric layer 12A (the number is not limited to 1, but an arbitrary natural number N) alternately stacked are epitaxially grown in sequence on the substrate 10A by a conventional process such as PECVD, UHVCVD, HDPCVD, MOCVD, MBE, ALD, or the like. The sacrificial layer material may be a semiconductor material such as SiGe, SiGeC, SiGeSn, SiGaN, SiGaP, siggaas, InSiN, InSiP, InSiAs, InSiSb, and ingaas, or a non-semiconductor material such as amorphous carbon or (oxidized) graphene. Piezoelectric layer materials are ceramic materials such as ZnO, AlN, BST (barium strontium titanate), BT (barium titanate), PZT (lead zirconate titanate), PBLN (lead barium lithium niobate), PT (lead titanate), and the like. Preferably, the number of sacrificial layers is one more than the number of piezoelectric layers. It is further preferable that the stacked structure further includes a cap layer 10B formed on the top sacrificial layer 11D, and the material of the cap layer is preferably the same as that of the substrate 10A, so as to serve as an upper cover plate of the topmost resonant cavity in the subsequent process.

As shown in fig. 2A-2C, a hard mask layer 13 is formed on top of the stacked structure to protect the stacked structure, and in particular, the cap layer 10B on top of the stacked structure, in subsequent processes. The hard mask layer 13 is deposited by LPCVD, PECVD, HDPCVD, etc., and is made of SiN, SiON, SiNC, SiNF, etc. Next, a photoresist pattern 14 is formed on top of the hard mask layer 13. The photoresist coating layer is formed by spin coating, spray coating, screen printing, etc., and is exposed and developed to form photoresist patterns 14, wherein the photoresist patterns extend along a first direction, i.e., a-a ', while leaving openings extending along the first direction between adjacent photoresist patterns (a second direction, i.e., B-B') to expose the hard mask layer 13.

As shown in fig. 3A to 3C, the photoresist pattern 14 is used as a mask to sequentially etch the stack of the hard mask layer 13, the cap layer 10B, the sacrificial layer 11 and the piezoelectric film 12, stopping on the substrate 10A, and forming a plurality of first openings 14A vertically penetrating through the above layers until the substrate 10A is exposed. The etching process is preferably an anisotropic dry etching process, such as plasma dry etching or reactive ion etching using a fluorocarbon based etching gas. Since the substrate 10A is a semiconductor material such as Si and does not contain an element normally contained in an insulating material such as C, N, O, the stop time can be determined by observing a change in the wavelength spectrum of the atmosphere in the etching chamber. For example, when the intensity of the plasma glow signal corresponding to CN and/or NO radicals is monitored to decrease below 1%, particularly 0.2%, of the peak value and is constant for 10 to 500 microseconds, it is judged that etching has reached the top of the substrate 10A.

As shown in fig. 4A-4C, the width of the top of the first opening 14A is enlarged such that a second portion 13A of the top of the first opening in the direction B-B' has a larger width than the first portion 14A below, the second portion 13A exposing a portion of the top of the piezoelectric layer 12A. Forming a second photoresist pattern with a smaller size, or performing a shrinking process (shrink) on the photoresist pattern 14 to reduce the size of the photoresist pattern, and etching the cap layer 10B and the sacrificial layer 11B with the photoresist pattern with the smaller size as a mask until the piezoelectric layer 12A is exposed. The photoresist pattern 14 is then removed to expose the hard mask layer 13, and the photoresist of organic material is removed by acid and/or oxidant, preferably by a wet process, so as to leave a plurality of T-shaped first openings formed by narrower first portions 14A distributed along the first direction a-a' and wider second portions 13A located above the same. Preferably, HF-based etching solution such as dHF, dBOE and the like is adopted to remove the native oxide on the surface of each layer by a wet method so as to improve the growth quality of the subsequent film.

As shown in fig. 5A-5C, an isolation layer 15 is formed over the entire device. The isolation layer 15 is preferably formed by a process with good conformality, such as HDPCVD, MBE, ALD, in-situ water vapor doping thermal oxidation/nitridation, and is made of an insulating dielectric material different from the hard mask 13, such as SiOx, SiOC, SiOF, SiFC, BSG, PSG, and PBSG. The isolation layer 15 uniformly covers the first portion 14A, the second portion 13A and the top of the hard mask 13, in particular the sidewalls of the sacrificial layer 11 and the piezoelectric layer 12 exposed in the first portion 14A, the second portion 13A. The spacer layer 15 will subsequently act as an insulating spacer material between the individual sub-resonators of the stacked BAW and will serve as a temporary mechanical support structure in subsequent processes. Preferably, the thickness of the isolation layer 15 is 1-50 nm, preferably 10-25 nm, and if the thickness of the isolation layer is too thin, the isolation layer cannot provide sufficient mechanical support, and if the thickness of the isolation layer is too thick, the isolation layer can easily fill the bottom of the first portion 14A too early. Preferably, twice the thickness of the isolation layer 15 is less than 1/4 and preferably less than 1/8, but equal to or greater than 1/10 of the width of the first portion 14A of the first opening.

As shown in fig. 6A-6C, a photoresist layer 16 is formed over the entire device by spin coating, spray coating, screen printing, etc., completely filling the first portion 14A and the second portion 13A of the first opening.

As shown in fig. 7A-7C, the photoresist layer 16 is patterned using an exposure and development process, leaving a plurality of second openings 16A extending along the second direction B-B' to expose the underlying isolation layer 15. Preferably, the second opening 16A is not continuous along the second direction but is further divided into a plurality of sub-portions so as to retain the underlying discontinuous isolation layer pattern 15, so as to avoid the isolation layer 15 from being completely broken in the first direction a-a' to cause local collapse in the subsequent sacrificial layer removing process. It is further preferred that the wavelength and dose of the exposure and development are selected such that the corners of the opening 16A are rounded to reduce the stress concentration at the corners of the rectangle to ensure that the mechanical support properties of the isolation layer 15 are intact.

As shown in fig. 8A-8C, the stack of the isolation layer 15, the hard mask layer 13, the cap layer 10B, the sacrificial layer 11 and the piezoelectric layer 12 is etched down in sequence by using the photoresist pattern 16 as a mask and using an anisotropic dry etching process, for example, plasma dry etching or reactive ion etching using a fluorocarbon-based etching gas, stopping on the substrate 10A. That is, the plurality of openings 16A are made deeper until the substrate 10A is exposed. The etching process is further preferably selected with a gas having a relatively large fluorocarbon content, such as CFH₃、C₂F₃H₃、CF₂H₂And the like, so that during the etching process, C and elements such as Si, N and the like form a temporary protective layer on the side wall to inhibit lateral corrosion and ensure that the side wall of the second opening 16A has enough verticality.

As shown in fig. 9A-9C, the photoresist pattern 16 is removed. The photoresist of the organic material is removed by a dry ashing process to avoid excessive etching of the underlying isolation layer 15 by the wet etching solution. More preferably, the surface of the spacer 15 is cleaned with an HF-based etchant such as dHF or dBOE.

As shown in fig. 10A to 10C, the isotropic selective etching removes the sacrificial layer 11, leaving a plurality of piezoelectric layer patterns 12 (not limited to 12A shown in the figures) supported by the isolation layer 15 on the substrate, and having a plurality of recesses 15A in the horizontal direction between adjacent piezoelectric layer patterns, between the top piezoelectric layer and the cap layer 10B, and between the bottom piezoelectric layer and the substrate 10A, in addition to the T-shaped first openings in the vertical direction. In a preferred embodiment of the present invention, the substrate 10A and the cap layer 10B are Si, the sacrificial layer 11 is SiGe, and wet etching is performed, and the etching solution is a combination of a strong oxidant, a strong inorganic acid and a weak organic acid to increase the etching selectivity of SiGe to Si. Wherein the strong oxidant is nitric acid, hydrogen peroxide, ozone and perchloric acid, the strong inorganic acid is hydrofluoric acid, hydrochloric acid and sulfuric acid, and the weak organic acid is acetic acid and oxalic acid, for example, the strong oxidant is 30-50 parts, the strong inorganic acid is 0.5-2 parts, the weak organic acid is 1-4 parts, and the solvent water is 40-70 parts (volume ratio). For example, for single crystal Si_0.8Ge_0.2And Si, 40:1:2:57 HNO may be used₃(70％):HF(49％):CH₃COOH(99.9％):H₂O, thereby achieving a 300:1 selection ratio. In another embodiment of the present invention, the sacrificial layer 11 is a C-based material such as amorphous carbon (e.g. ta-C), graphene oxide, graphene, etc., and oxygen plasma dry etching or thermal oxidation can be selected so that the sacrificial layer reacts with oxygen to form gas to be pumped out, at which time oxygen will form a thin oxide layer on the surface of the piezoelectric layer 12, and the thin oxide layer needs to be removed by using an etchant such as dHF, dBOE, etc.

As shown in fig. 11A to 11C, a metal layer 17 is formed on the entire device by a deposition process having good conformality such as ALD, MBE, MOCVD or the like, and is used as a contact electrode of the piezoelectric layer 12. The material of the metal layer 17 includes, for example, a metal simple substance or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials, that is, a seed layer or a barrier layer and a conductive layer. As shown in fig. 11C, in the cross-sectional view, the metal layer 17 not only surrounds the piezoelectric layer 12 (at least three sides, preferably four sides), but is also deposited on the substrate 10A, the cap layer 10B to serve as a contact layer for the bottom and top surfaces.

As shown in fig. 12A-12C, the photoresist is spin-coated and exposed to light and developed to form photoresist patterns 18 extending in the second direction B-B 'with a pitch in the first direction a-a' equal to the original width of the second opening 16A, i.e., the sidewalls of the photoresist patterns 18 are flush with the sidewalls of the piezoelectric layer 12 in the vertical direction.

As shown in fig. 13A to 13C, with the photoresist pattern 18 as a mask, the respective layers are sequentially anisotropically dry etched until the substrate 10A is exposed, thereby removing the vertical portions of the metal layer 17 and leaving only the horizontal portions, that is, leaving only the bottom of the cap layer 10B, the top and bottom of the piezoelectric layer 12, and the top of the substrate 10A as contact electrode layers.

As shown in fig. 14A-14C, the photoresist pattern 18 is removed, exposing the electrode layer 17 in the first opening and on top of the isolation layer 15. As shown in fig. 14B, the electrode layer 17 encapsulates the recess 15A and directly contacts the top and bottom of the piezoelectric layer 12, which will be used as top and bottom electrodes in the future.

As shown in fig. 15A-15C, the second isolation layer 19 is formed by using a process with good conformality, such as HDPCVD, MBE, ALD, in-situ water vapor doping thermal oxidation/nitridation, and the material of the second isolation layer can be the same as that of the (first) isolation layer 15, such as SiOx, SiOC, SiOF, SiFC, BSG, PSG, PBS. The second isolation layer 19 is mainly used for insulating and isolating the piezoelectric layer, the capping layer and the substrate in the vertical direction.

As shown in fig. 16A-16C, the photoresist is applied and exposed to light and developed to form photoresist patterns 20 extending along the first direction a-a ', and the pitch between the photoresist patterns 20 along the second direction B-B' is preferably equal to the original width of the lower first portion 14A of the first opening, i.e., the sidewalls of the photoresist patterns 20 are flush with the sidewalls of the piezoelectric layer 12A in the vertical direction.

As shown in fig. 17A to 17C, each film layer is anisotropically dry etched using the photoresist pattern 20 as a mask until the substrate 10A is exposed, re-exposing the first portion 14A of the first opening. In this process, since the width of the first opening second portion 13A is large, the first isolation layer 15 of the insulating material will remain on the sidewall of the second portion 13A, i.e., as shown in fig. 17B, the isolation layer 15 sidewall is flush with the piezoelectric layer 12A. The remaining isolation layer 15 will serve to isolate the top and bottom electrode leads of the piezoelectric layer 12A in the horizontal direction.

As shown in fig. 18A to 18C, the photoresist pattern 20 is removed using a dry ashing process.

As shown in fig. 19A to 19C, a metal layer 21 is formed on the entire device by a deposition process having good conformality, such as ALD, MBE, MOCVD, or the like, and is used as a bottom electrode lead line of the piezoelectric layer 12. The material of the metal layer 21 includes a metal simple substance or a metal alloy such as Mo, W, Ru, Al, Cu, Ti, Ta, In, Zn, Zr, Fe, Mg, etc., or a conductive oxide or a conductive nitride of these metals, and any combination of the above materials, that is, a seed layer or a barrier layer and a conductive layer. As shown in fig. 19B, the first isolation layer 15 effectively insulates the piezoelectric layer top and bottom electrodes because the metal layer 21 can only contact the metal layer 17 at the bottom of the piezoelectric layer 12A surrounding the cavity portion, but not the metal layer 17 above, due to the presence of the first isolation layer 15.

As shown in fig. 20A to 20C, the filling layer 16 is planarized by CMP or etch back until the hard mask layer 13 is exposed.

As shown in fig. 21A to 21C, the hard mask 13 is removed. The removal process may be CMP planarization or wet etching. In the CMP process, an oxidizing agent such as hydrogen peroxide, ozone or nitric acid may be added to the polishing slurry to accelerate the CMP speed, and at the same time, an ultra-thin silicon oxide layer is formed in situ on the top of the cap layer 10B to be used as a liner layer or a gate dielectric interface layer in a subsequent process.

As shown in fig. 22, a drive transistor 22 is formed in the cap layer 10B. Specifically, for example, a photoresist (not shown) is used to shield the first opening and expose only the active region of the cap layer 10B, a gate stack 22G formed by a gate dielectric layer and a gate conductive layer is formed in the active region, and an ion doping implantation is performed using the gate stack 22G as a mask to form a source region 22S and a drain region 22D. In particular, after the source region 22S and the drain region 22D are formed by simultaneous implantation, the source region is masked by a photoresist pattern to expose only the drain region, and the ion implantation depth is increased so that the doped region 22D directly contacts the metal layer 17 surrounding the recess 15A, thereby finally electrically contacting the top of the piezoelectric layer 12A along the sidewall of the recess 15A. In other words, the drain of the driving transistor 22 is electrically connected to the piezoelectric film 12A, so that the path length of the driving transistor and the piezoelectric layer can be shortened inside the wafer, the series resistance can be reduced, the driving capability can be improved, the integration can be improved, and the package cost can be reduced.

In a preferred embodiment of the present invention, the cap layer 10B is P-doped or intrinsic, and n-type source regions 22S and drain regions 22D are formed by ion implantation of n-type doped ions such As, P, and Sb into the cap layer 10B. In addition, p-type source and drain regions can be formed by implanting p-type impurities such as B and the like into the n-cap layer. Wherein, the implantation depth of the drain region 22D in the selective implantation process is preferably greater than or equal to the thickness of the cap layer 10B, so that the drain region 22D directly contacts and electrically connects with the top electrode layer 17 of the cavity 15A under the cap layer 10B, set according to the depth of the cap layer 10B. Further preferably, after the ion implantation, an annealing process such as RTA is performed to activate the dopant ions and further repair the damages of the top of the cap layer 10B, the sidewall of the insulating layer 15, the sidewall of the electrode layer 21 and the bottom of the electrode layer in the previous process steps, thereby effectively improving the performance and stability of the driving transistor.

In a preferred embodiment of the present invention, after forming the source/drain regions 22S/D, an ohmic contact layer (not shown) is formed on top of the gate 22G, the source region 22S and the drain region 22D, and the material of the ohmic contact layer is metal silicide, metal germanide or the like, so as to effectively reduce the surface contact resistance. For example, a thin metal layer of W, Co, Pt, Ti, Ni, Ta, etc. is formed on top of the driving transistor, and an annealing process is performed to react these metals with the semiconductor elements such as Si, Ge, etc. in the gate, source and drain regions of the driving transistor in the cap layer 10B to form goldOf silicides or metal germanides, e.g. WSi₂CoSi, NiSi, and the like. In a preferred embodiment of the invention, the annealing process is performed in two steps, a first step of relatively low temperature annealing (e.g., less than 450 degrees celsius) to form a silicon-rich or germanium-rich compound, and a second step of relatively high temperature annealing (e.g., 450 to 650 degrees celsius) to convert the Si/Ge-rich compound to a low resistance state. Advantageously, at least a portion of the annealing process used herein to form the ohmic contact layer (e.g., the second high temperature anneal) may be combined with the aforementioned annealing process to activate the dopant ions to save process steps and reduce costs.

In another preferred embodiment of the present invention, the process for forming the ohmic contact layer includes, when ion implantation is performed to form the source/drain regions 22S/D, the target in the process chamber is a compound of the ion implantation dopant and the metal, such As a compound of As, P, Sb, B and W, Co, Pt, Ti, Ni, Ta, such As WP, NiP, TiB₂And so on. In addition to employing a mass analyzer to pick and vertically direct implanted ions such as B, P, etc. onto the cap layer 10B for vertical ion implantation, a second mass analyzer is further employed to obliquely direct the knocked-out metal ions from the sides of the implanted region to the source and drain regions surfaces (preferably repeated alternately with vertical ion implantation), thereby forming an ohmic contact layer in situ. The energy of the vertical ion implantation may be chosen to be greater than the metal ion energy (preferably greater than 1 order of magnitude) so that the implanted B, P-like dopant ions can penetrate through the very thin ohmic contact layer to the depth of the cap layer 10B. Therefore, the process steps of annealing to form silicide and germanide after deposition can be saved, the device does not need to be transferred from the ion implantation chamber to the deposition annealing chamber, the process time is saved, and the process cost is reduced.

As shown in fig. 23A to 23C, an interlayer dielectric layer 23 is formed on the driving transistor 22, and a contact plug 24 is formed in the interlayer dielectric layer (ILD) 23. The ILD layer 23 of low-k material is formed by spin-coating, spray-coating, screen-printing, etc., wherein the low-k material includes, but is not limited to, organic low-k materials (e.g., organic polymers containing aryl or multi-membered rings), inorganic low-k materials (e.g., amorphous carbon nitride films, poly boron nitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous diamond, porous organic polymers). ILD layer 23 closes at least the top of opening 16A as shown in fig. 23C. Since layer 23 is a low temperature process-formed soft low-k material that does not penetrate too far into opening 16A (e.g., filling only 1/3 to a depth less than the thickness of cap layer 10B), it does not affect the cavity profile at the side of piezoelectric layer 12A, i.e., the resonator Q value. The ILD layer is etched to form a via hole exposing the bottom electrode lead 21, the gate/source/drain region of the driving transistor 22 and a metal material is deposited to form a contact plug 24. The contact plugs are divided into contact plugs 24B connected to the bottom electrodes of the piezoelectric films and contact plugs 24G, 24S, and 24D connected to the gate 22G, the source 22S, and the drain 22D of the driving transistor, according to the positions.

As shown in fig. 24, it is preferable to further form a Metal Interlayer Dielectric (MID)25 on the ILD layer 23 and a re-wiring (RDL) layer 26 in the MID25 for rearranging the distribution positions of the contact plugs 24 to flexibly adjust the layout of the external electrical contacts. The MID25 and ILD 23 may be low-k materials, and the RDL layer 26 may be the same material as the contact plug 24. In a preferred embodiment of the present invention, after the ILD 23 and the MID25 are sequentially formed, the contact plug 24 and the RDL layer 26 are formed using a damascene process.

Thus, having fully described the fabrication process of a CMOS process compatible BAW resonator according to one embodiment of the present invention with reference to fig. 1A to 24, the finally completed stacked BAW resonator on a first wafer comprises: a substrate 10A and a cap layer 10B, an array of at least one piezoelectric film 12A between the substrate 10A and the cap layer 10B (distributed along intersecting first and second directions a-a 'and B-B'), first cavities 15A between the top piezoelectric film 12A and the cap layer 10B, between the bottom piezoelectric film 12A and the substrate 10A, and between vertically adjacent piezoelectric films 12, a second cavity 16A (second opening) between horizontally adjacent piezoelectric films 12A along the first direction a-a 'and a third cavity (first opening 14A/13A) along the second direction B-B', a metal layer 17 surrounding each first cavity 15A to serve as top and bottom electrodes of the piezoelectric layer 12A, bottom electrode lead-outs 21 distributed at sidewalls of the third cavity, first isolation layers 15 between the bottom electrode lead-outs 21 and the top electrodes 17 of the piezoelectric layer 12A, wherein the cap layer 10B has a driving transistor 22 therein, and a drain region 22D of the driving transistor 22 is electrically connected to the top electrode of the piezoelectric layer 12A. The cap layer 10B further has an ILD layer 23 and a contact plug 24 therein, and further has an MID layer 25 and an RDL layer 26 therein. It is preferable that the source and drain regions and the gate electrode of the driving transistor 22 have an ohmic contact layer formed in situ or deposited annealed thereon to effectively reduce the interface resistance.

The package structure may then be further completed, for example by forming contact pads and a passivation layer (both not shown). For example, a passivation layer of silicon oxide, silicon nitride or other organic resin is formed for insulation protection or as a build-up layer for future soldering. Preferably, the passivation layer is subjected to a treatment, such as oxygen and/or nitrogen atmosphere plasma annealing or laser annealing, to enhance the bonding strength between the passivation layer and the bonding pad and between the future structures, and the surface treatment also repairs the surface damage to the electrodes on both sides of the piezoelectric film and the electrode interconnection layer in each etching deposition process step, thereby being beneficial to reducing the series resistance and the parasitic capacitance. Specifically, a planarization process is performed on the passivation layer to expose the pad pattern. Thereafter, it is further preferable that a conductive bump is formed over the pad pattern to be electrically connected to the outside.

According to the BAW resonator and the manufacturing method thereof, the three-dimensional resonator with the plurality of cavities surrounding the piezoelectric film is manufactured by adopting a CMOS compatible process, and the driving circuit electrically connected with the top electrode of the piezoelectric film is formed in the top cap layer through ion deep implantation, so that the packaging volume is reduced, and the interface resistance is reduced.

While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.