阅读说明：本技术 显示设备 (Display device ) 是由 林泰坤 金受姸 朴东园 李宰汉 曹政焕 于 2020-02-13 设计创作，主要内容包括：显示设备包括显示面板、源极驱动器和对齐检测电路。显示面板包括数据线和连接至数据线的焊盘。源极驱动器包括输出线和检测电路,其中,输出线连接至焊盘以供应数据信号,检测电路选择性地将供应有第一检测电压的第一检测线和供应有第二检测电压的第二检测线连接至输出线。对齐检测电路包括检测电容器和电压检测电路,其中,检测电容器连接在第一检测线与第二检测线之间,电压检测电路连接至检测电容器的一端以检测检测电容器的电压。检测电路将输出线中的第2n-1输出线连接至第一检测线,并且将输出线中的第2n输出线连接至第二检测线。(The display device includes a display panel, a source driver, and an alignment detection circuit. The display panel includes a data line and a pad connected to the data line. The source driver includes an output line connected to the pad to supply a data signal, and a detection circuit selectively connecting a first detection line supplied with a first detection voltage and a second detection line supplied with a second detection voltage to the output line. The alignment detection circuit includes a detection capacitor connected between a first detection line and a second detection line, and a voltage detection circuit connected to one end of the detection capacitor to detect a voltage of the detection capacitor. The detection circuit connects a 2n-1 th one of the output lines to a first detection line, and connects a 2 n-th one of the output lines to a second detection line.)

1. A display device, comprising:

a display panel including a plurality of data lines and a plurality of pads connected to the data lines;

a source driver, comprising:

a plurality of output lines connected to the pads, wherein the source driver supplies data signals to the pads through the output lines; and

a detection circuit selectively connecting a first detection line and a second detection line to the output line, wherein the first detection line is supplied with a first detection voltage and the second detection line is supplied with a second detection voltage; and

an alignment detection circuit including a detection capacitor connected between the first detection line and the second detection line and a voltage detection circuit connected to one end of the detection capacitor, wherein the voltage detection circuit detects a voltage of the detection capacitor,

wherein the detection circuit connects a 2n-1 th one of the output lines to the first detection line, and connects a 2n th one of the output lines to the second detection line, where n is a natural number of 1 or more.

2. The display device of claim 1, wherein the source driver further comprises:

a digital-to-analog converter converting the digital image data into analog image data; and

a buffer circuit including a plurality of buffers that generate the data signals based on the analog image data.

3. The display device of claim 2, wherein the detection circuit comprises:

a first switch connecting the output line to the buffer;

a first dummy amplifier supplying the first detection voltage to the first detection line;

a second dummy amplifier supplying the second detection line with the second detection voltage having a voltage level lower than that of the first detection voltage;

a second switch connecting the first detection line to the 2n-1 output line; and

a third switch connecting the second detection line to the 2 n-th output line.

4. The display device according to claim 3, wherein the detection circuit turns off the first switch and turns on the second switch and the third switch during an inspection process of detecting whether the output line is misaligned with the pad.

5. The display device of claim 3, wherein the detection circuit turns on the first switch and turns off the second switch and the third switch to transmit the data signal to the pad through the output line.

6. The display device according to claim 1, wherein the voltage detection circuit includes a comparator that compares the voltage of the detection capacitor with a reference voltage.

7. The display device of claim 6, further comprising:

a timing controller generating a control signal to control the source driver,

wherein the voltage detection circuit outputs a turn-off signal to turn off the timing controller based on a comparison result between the voltage of the detection capacitor and the reference voltage.

8. The display device of claim 6, further comprising:

a voltage generator supplying the first detection voltage and the second detection voltage,

wherein the voltage detection circuit outputs a turn-off signal to turn off the voltage generator based on a comparison result between the voltage of the detection capacitor and the reference voltage.

9. The display device of claim 1,

one end of the source driver is connected to the pad of the display panel, an

The opposite end of the source driver is connected to a printed circuit board.

10. The display device of claim 9, wherein the alignment detection circuit is disposed on the printed circuit board.

Technical Field

Exemplary embodiments relate to a display panel driving apparatus and a display apparatus including the same.

Background

Recently, various flat panel display devices having reduced weight and thin thickness compared to conventional Cathode Ray Tube (CRT) displays have been developed. Such flat panel display devices include Liquid Crystal Displays (LCDs), Field Emission Displays (FEDs), Plasma Display Panels (PDPs), and Organic Light Emitting Displays (OLEDs).

The display device may include a display panel to display an image, and may include a display panel driving device to supply a signal to the display panel. The source driver included in the display panel driving apparatus may generate the data signal. The source driver may be coupled to the non-display area of the display panel in the form of an Integrated Circuit (IC), or may be connected to the non-display area of the display panel through a Flexible Printed Circuit Board (FPCB) or the like.

Disclosure of Invention

In the display apparatus, when an Integrated Circuit (IC) is misaligned with a pad of a display panel, a screen abnormality may occur or the display panel may be damaged. Therefore, a technique for detecting whether the display panel and the IC are misaligned has been studied.

Exemplary embodiments provide a display device capable of detecting misalignment between a display panel and a source driver.

Exemplary embodiments provide a display panel driving apparatus capable of detecting misalignment between a display panel and a source driver.

According to an exemplary embodiment, a display apparatus includes: a display panel including a plurality of data lines and a plurality of pads connected to the data lines; a source driver including a plurality of output lines connected to the pad and a sensing circuit selectively connecting a first sensing line and a second sensing line to the output lines, wherein the source driver supplies a data signal to the pad through the output lines, wherein the first sensing line is supplied with a first sensing voltage and the second sensing line is supplied with a second sensing voltage; and an alignment detection circuit including a detection capacitor connected between the first detection line and the second detection line and a voltage detection circuit connected to one end of the detection capacitor to detect a voltage of the detection capacitor. In this embodiment, the detection circuit connects the 2n-1 th one of the output lines to a first detection line, and connects the 2n th one of the output lines to a second detection line, where n is a natural number of 1 or more.

In an exemplary embodiment, the source driver may further include a digital-to-analog converter converting the digital image data into analog image data, and a buffer circuit including a plurality of buffers generating data signals based on the analog image data.

In an exemplary embodiment, the detection circuit may include a first switch connecting the output line to the buffer, a first dummy amplifier supplying a first detection voltage to the first detection line, a second dummy amplifier supplying a second detection voltage having a voltage level lower than that of the first detection voltage to the second detection line, a second switch connecting the first detection line to the 2n-1 th output line, and a third switch connecting the second detection line to the 2 n-th output line.

In an exemplary embodiment, the detection circuit may turn off the first switch and may turn on the second switch and the third switch during a checking process of detecting whether the output line is misaligned with the pad.

In an exemplary embodiment, the detection circuit may turn on the first switch and may turn off the second switch and the third switch to transmit the data signal to the pad through the output line.

In an exemplary embodiment, the voltage detection circuit may include a comparator that compares the voltage of the detection capacitor with a reference voltage.

In an exemplary embodiment, the display apparatus may further include a timing controller generating a control signal to control the source driver. In this embodiment, the voltage detection circuit may output a turn-off signal to turn off the timing controller based on a comparison result between the voltage of the detection capacitor and the reference voltage.

In an exemplary embodiment, the display apparatus may further include a voltage generator supplying the first and second detection voltages. In this embodiment, the voltage detection circuit may output a shutdown signal to shut down the voltage generator based on a comparison result between the voltage of the detection capacitor and the reference voltage.

In an exemplary embodiment, one end of the source driver may be connected to a pad of the display panel, and the opposite end of the source driver may be connected to the printed circuit board.

In an exemplary embodiment, the alignment detection circuit may be disposed on a printed circuit board.

According to an exemplary embodiment, a display panel driving apparatus includes a source driver including a plurality of output lines through which data signals are transmitted, and a detection circuit selectively connecting a first detection line and a second detection line to the output lines, wherein the first detection line transmits a first detection voltage and the second detection line transmits a second detection voltage, and an alignment detection circuit including a detection capacitor connected between the first detection line and the second detection line and a voltage detection circuit connected to one end of the detection capacitor, wherein the voltage detection circuit detects a voltage of the detection capacitor. In this embodiment, the detection circuit connects the 2n-1 th one of the output lines to a first detection line, and may connect the 2n th one of the output lines to a second detection line, where n is a natural number of 1 or more.

In an exemplary embodiment, the source driver may further include a digital-to-analog converter converting the digital image data into analog image data, and a buffer circuit including a plurality of buffers generating data signals based on the analog image data.

In an exemplary embodiment, the detection circuit may include a first switch connecting the output line to the buffer, a first dummy amplifier supplying a first detection voltage to the first detection line, a second dummy amplifier supplying a second detection voltage having a voltage level lower than that of the first detection voltage to the second detection line, a second switch connecting the first detection line to the 2n-1 th output line, and a third switch connecting the second detection line to the 2 n-th output line.

In an exemplary embodiment, the detection circuit may turn off the first switch and may turn on the second switch and the third switch during an inspection process of detecting whether the output line is misaligned with the plurality of pads of the display panel.

In an exemplary embodiment, the detection circuit may turn on the first switch and may turn off the second switch and the third switch to output the data signal through the output line.

In an exemplary embodiment, the voltage detection circuit may include a comparator that compares the voltage of the detection capacitor with a reference voltage.

In an exemplary embodiment, the display panel driving apparatus may further include a timing controller generating a control signal to control the source driver. In this embodiment, the voltage detection circuit may output a turn-off signal to turn off the timing controller based on a comparison result between the voltage of the detection capacitor and the reference voltage.

In an exemplary embodiment, the display panel driving apparatus may further include a voltage generator supplying the first and second detection voltages. In this embodiment, the voltage detection circuit may output a shutdown signal to shut down the voltage generator based on a comparison result between the voltage of the detection capacitor and the reference voltage.

In an exemplary embodiment, one end of the source driver may be connected to a pad of the display panel, and the opposite end of the source driver may be connected to the printed circuit board.

In an exemplary embodiment, the alignment detection circuit may be disposed on a printed circuit board.

In exemplary embodiments of the present invention, as set forth herein, during an inspection process of a display device, the display device and the display panel driving device may detect misalignment between a pad of the display panel and an output line of a source driver by supplying a first detection voltage to odd-numbered output lines via a first detection line, by supplying a second detection voltage to even-numbered output lines via a second detection line, and by detecting a voltage of a detection capacitor connected between the first detection line and the second detection line. Therefore, in such an embodiment, a bonding defect between the display panel and the source driver may be easily detected.

Drawings

The above and other features of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a display device according to an exemplary embodiment;

fig. 2A and 2B are diagrams illustrating a display panel and a source driver included in the display device of fig. 1;

fig. 3 is a block diagram illustrating a source driver included in the display apparatus of fig. 1;

fig. 4 is a diagram illustrating a detection circuit and an alignment detection circuit included in the source driver of fig. 3;

FIG. 5 is a diagram illustrating an exemplary embodiment of the alignment detection circuit of FIG. 4; and

fig. 6A to 6C are diagrams for describing operations of the detection circuit and the alignment detection circuit of fig. 4.

Detailed Description

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being directly on another element, there are no intervening elements present.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "first component," "first region," "first layer," or "first section" discussed below could be termed a second element, second component, second region, second layer, or second section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, including "at least one", unless the content clearly indicates otherwise. "or" means "and/or". "at least one of A and B" means "A and/or B". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," or "includes" and/or "including," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper" depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary terms "below" or "beneath" can therefore encompass both an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a display device according to an exemplary embodiment, and fig. 2A and 2B are diagrams illustrating a display panel and a source driver included in the display device of fig. 1.

Referring to fig. 1, an exemplary embodiment of a display apparatus 100 may include a display panel 110 and a display panel driving circuit 120. The display panel driving circuit 120 may include a timing controller 121, a voltage generator 122, a source driver 123, an alignment detection circuit 125, and a scan driver 126.

The display panel 110 may include a plurality of data lines DL, a plurality of scan lines SL, and a plurality of pixels PX. The data line DL may extend in a first direction D1, and may be arranged in a second direction D2 perpendicular to the first direction D1. The scan lines SL may extend in the second direction D2 and may be arranged in the first direction D1. In one exemplary embodiment, for example, the first direction D1 may be parallel to a short side of the display panel 110, and the second direction D2 may be parallel to a long side of the display panel 110. The pixels PX may be disposed in regions where the data lines DL and the scan lines SL intersect. The pixels PX may be responsive to the SCAN signal SCAN supplied through the SCAN lines SL to emit light corresponding to the DATA signal DATA supplied through the DATA lines DL. In an exemplary embodiment, the pixel PX may include a thin film transistor electrically connected to the data line DL and the scan line SL, a storage capacitor connected to the thin film transistor, a driving transistor connected to the storage capacitor, and an organic light emitting diode connected to the driving transistor. In this embodiment, the display panel 110 may be an organic light emitting display panel, and the display device 100 may be an organic light emitting display device. In an alternative exemplary embodiment, the pixel PX may include a thin film transistor electrically connected to the scan line SL and the data line DL, and a liquid crystal capacitor and a storage capacitor connected to the thin film transistor. In this embodiment, the display panel 110 may be a liquid crystal display panel, and the display device 100 may be a liquid crystal display device.

The display panel 110 may include a display area and a non-display area. The pixels PX are disposed or defined in the display area, and an image may be displayed based on the DATA signal DATA supplied through the DATA lines DL. A circuit portion or the like may be provided in the non-display area to drive the pixels PX. In this embodiment, a pad part including a plurality of pads connected to the data lines DL may be disposed or defined in the non-display area of the display panel 110. The pad may be connected to a source driver 123 for supplying a DATA signal DATA.

The timing controller 121 may receive the first image data IMG1 and the control signal CON from an external device. The timing controller 121 may convert the first image data IMG1 supplied from an external device into the second image data IMG 2. The timing controller 121 may apply an algorithm for correcting the image quality of the first image data IMG1 to convert the first image data IMG1 into the second image data IMG2 and supply the second image data IMG2 to the source driver 123. The timing controller 121 may generate the scan control signal CTL _ S and the data control signal CTL _ D to control the driving timing of the second image data IMG2 based on the control signal CON. In one exemplary embodiment, for example, the scan control signal CTL _ S may include a vertical start signal and at least one scan clock signal, and the data control signal CTL _ D may include a horizontal start signal and a horizontal synchronization signal. The timing controller 121 may supply a scan control signal CTL _ S to the scan driver 126 and supply a data control signal CTL _ D to the source driver 123.

In an exemplary embodiment, the voltage generator 122 may receive Direct Current (DC) power from the outside to generate a plurality of voltages for operating the display panel 110. In one exemplary embodiment, for example, the voltage generator 122 may generate a start voltage and a stop voltage supplied to the scan driver 126 and a data driving voltage, a first detection voltage VD1, and a second detection voltage VD2 supplied to the source driver 123. The voltage generator 122 may generate a start-up voltage and a shut-down voltage to supply the start-up voltage and the shut-down voltage to the scan driver 126. The turn-on voltage and the turn-off voltage may be driving voltages that generate the SCAN signal SCAN applied to the SCAN line SL. The voltage generator 122 may generate a data driving voltage to supply the data driving voltage to the source driver 123. In one exemplary embodiment, for example, the voltage generator 122 may generate an analog power supply voltage, a digital power supply voltage, or the like to supply the generated voltage to the source driver 123. The analog power supply voltage and the digital power supply voltage may be driving voltages that generate the DATA signal DATA applied to the DATA lines DL. In this embodiment, the voltage generator 122 may supply the first and second detection voltages VD1 and VD2 to the source driver 123 during the inspection process. Here, the voltage level of the second detection voltage VD2 may be lower than the voltage level of the first detection voltage VD 1. The first detection voltage VD1 and the second detection voltage VD2 may be voltages provided to the detection circuit 124 of the source driver 123 to detect whether the source driver 123 is misaligned with the display panel 110.

The source driver 123 may generate the DATA signal DATA based on the second image DATA IMG2 and the DATA control signal CTL _ D supplied from the timing controller 121. The source driver 123 may convert the second image DATA IMG2, which is digital image DATA, into analog image DATA, and generate the DATA signal DATA based on the analog image DATA.

The source driver 123 may be implemented as a Chip On Film (COF) including an Integrated Circuit (IC) and a Flexible Printed Circuit Board (FPCB) on which the IC is mounted. Alternatively, the source driver 123 may be implemented as a Chip On Glass (COG) type IC to be mounted on the non-display area of the display panel 110. The source driver 123 may include a plurality of output lines.

Referring to fig. 2A, one end of the output line OL may be implemented as a connection pad CPAD to be connected to a pad part in a non-display area of the display panel 110. The connection PADs CPAD of the output line OL may be connected to the PADs PAD of the PAD portion of the display panel 110, respectively. As shown in fig. 2B, when the source driver 123 and the PAD of the display panel 110 are misaligned, a short circuit may occur between the output lines OL of the source driver 123 or between the PAD PADs of the display panel 110, so that a screen abnormality may occur or the display panel 110 may be damaged. In an exemplary embodiment of the present invention, the display apparatus 100 includes the alignment detection circuit 125 and the source driver 123 having the detection circuit 124, so that the misalignment between the output line OL of the source driver 123 and the pad portion of the display panel 110 may be detected during the inspection process.

In an exemplary embodiment, the source driver 123 may include a detection circuit 124. The detection circuit 124 may connect the buffer supplied with the DATA signal DATA to the output line OL, or connect the first and second detection lines to the output line OL. When the display device 100 is driven, the detection circuit 124 may connect the buffer and the output line OL so that the DATA signal DATA may be supplied to the pad portion of the display panel 110 through the output line OL. The detection circuit 124 may connect the first and second detection lines to the output line OL during the inspection process, so that misalignment between the output line OL of the source driver 123 and the pad portion of the display panel 110 may be detected. In this embodiment, the detection circuit 124 may include a first dummy amplifier, a second dummy amplifier, a first detection line, and a second detection line. The first dummy amplifier may receive the first detection voltage VD1 supplied from the voltage generator 122 to supply the first detection voltage VD1 to the first detection line. The second dummy amplifier may receive the second detection voltage VD2 supplied from the voltage generator 122 to supply the second detection voltage VD2 to the second detection line. The first sensing line may be connected to a portion of the output line OL, and the second sensing line may be connected to the remaining output line OL. In one exemplary embodiment, for example, a first sensing line may be connected to the 2n-1 th output line, and a second sensing line may be connected to the 2n th output line. The 2n-1 output line may supply the first detection voltage VD1 supplied through the first detection line to the 2n-1 pad of the display panel 110, and the 2n output line may supply the second detection voltage VD2 supplied through the second detection line to the 2n pad of the display panel 110. However, when the output line OL of the source driver 123 is misaligned with the pad of the display panel 110, the second sensing voltage VD2 may be supplied to the 2n-1 th pad, or the first sensing voltage VD1 may be supplied to the 2 n-th pad.

The alignment detection circuit 125 may include a detection capacitor and a voltage detection circuit. The sensing capacitor may be connected between the first sensing line and the second sensing line. The detection capacitor may include a first electrode and a second electrode. When the output line OL of the source driver 123 is normally aligned with the PAD of the display panel 110, a voltage having a predetermined value may be applied to the first and second electrodes of the detection capacitor. However, when the output line OL of the source driver 123 is misaligned with the PAD of the display panel 110, the voltage levels of the voltages applied to the first and second electrodes of the detection capacitor may be changed. The voltage detection circuit may be connected to one end of the detection capacitor to detect a voltage of the detection capacitor. In an exemplary embodiment, the voltage detection circuit may be connected to the first electrode of the detection capacitor to detect a voltage of the first electrode. In an alternative exemplary embodiment, a voltage detection circuit may be connected to the second electrode of the detection capacitor to detect the voltage of the second electrode. In one exemplary embodiment, for example, the voltage detection circuit may include a comparator. The comparator may compare a voltage applied to the first electrode of the detection capacitor with a first reference voltage or compare a voltage applied to the second electrode of the detection capacitor with a second reference voltage. The voltage detection circuit may output the shutdown signal SHUT based on the comparison result of the comparator. In this embodiment, the voltage detection circuit may output the shutdown signal SHUT when the voltage of the detection capacitor is higher than the reference voltage. In an alternative exemplary embodiment, the voltage detection circuit may output the shutdown signal SHUT when the voltage of the detection capacitor is lower than the reference voltage. In one exemplary embodiment, for example, the voltage detection circuit may supply a turn-off signal SHUT to the timing controller 121 to turn off the timing controller 121. Alternatively, the voltage detection circuit may supply the shutdown signal SHUT to the voltage generator 122 to SHUT down the voltage generator 122.

The SCAN driver 126 may generate a SCAN signal SCAN supplied to the pixels PX. The SCAN driver 126 may generate a SCAN signal SCAN based on the SCAN control signal CTL _ S supplied from the timing controller 121 and sequentially supply the SCAN signal SCAN to the SCAN lines SL disposed on the display panel 110. The scan driver 126 may be provided simultaneously with the transistors of the pixels PX or formed to be mounted on the display panel 110 in the form of an amorphous silicon Thin Film Transistor (TFT) gate driving unit circuit (ASG) or a silicon oxide TFT gate driving unit circuit (OSG). Alternatively, the scan driver 126 may be formed of a plurality of driving chips or defined by a plurality of driving chips in common to be mounted on the non-display area of the display panel 110 in a COG type. Alternatively, the scan driver 126 may be formed of or collectively defined by a plurality of driving chips in the form of COFs mounted on the FPCB as being connected to the display panel 110.

In the exemplary embodiment of the present invention, as described above, the display device 100 includes the source driver 123 and the alignment detection circuit 125, wherein the source driver 123 includes the detection circuit 124 to supply the first detection voltage VD1 to the 2n-1 th output line through the first detection line and the second detection voltage VD2 to the 2n th output line through the second detection line during the inspection process of the display device 100, and the alignment detection circuit 125 includes the detection capacitor connected between the first detection line and the second detection line and the voltage detection circuit for detecting the voltage of the detection capacitor, so that the misalignment between the PAD of the display panel 110 and the output line OL of the source driver 123 may be detected. Accordingly, a bonding failure between the display panel 110 and the source driver 123 may be easily detected.

Fig. 3 is a block diagram illustrating a source driver included in the display device of fig. 1, fig. 4 is a diagram illustrating a detection circuit and an alignment detection circuit included in the source driver of fig. 3, and fig. 5 is a diagram illustrating an exemplary embodiment of the alignment detection circuit of fig. 4.

Referring to fig. 3, an exemplary embodiment of the source driver 200 may include a shift register 210, a latch 220, a digital-to-analog converter (referred to as DAC in fig. 3) 230, a buffer circuit 240, and a detection circuit 250.

The shift register 210 may control the operation timing of the latch 220 based on the data control signal CTL _ D supplied from the timing controller 121. The data control signal CTL _ D may include a horizontal synchronization signal. The horizontal synchronization signal may be a signal having a predetermined period. The latch 220 may sample and store the second image data IMG2 as digital image data based on a shift instruction of the shift register 210. The latch 220 may output the stored second image data IMG2 to the digital-to-analog converter 230 in response to a latch signal.

The digital-to-analog converter 230 may convert the second image data IMG2, which is digital image data, into analog image data.

Referring to fig. 4, the buffer circuit 240 may include a plurality of buffers B1, B2, B3, B4, … …, B (k-1), and B (k). Each of the buffers B1, B2, … …, B (k-1), and B (k) may generate a DATA signal DATA (here, k is a natural number of 2 or more) based on analog image DATA. Each of the buffers B1, B2, … …, B (k-1), and B (k) may be implemented as an operational amplifier. Each of the buffers B1, B2, … …, B (k-1), and B (k) may supply the DATA signal DATA to output lines OL1, OL2, … …, OL (k-1), and OL (k). In one exemplary embodiment, for example, the source driver 200 may include k buffers B1, B2, … …, B (k-1), and B (k). k buffers B1, B2, … …, B (k-1), and B (k) may be connected to k output lines OL1, OL2, … …, OL (k-1), and OL (k), respectively.

The detection circuit 250 may include output lines OL1, OL2, … …, OL (k-1) and OL (k), a first switch SW1, a first dummy amplifier 252, a second dummy amplifier 254, a second switch SW2, and a third switch SW 3.

One end of each of the output lines OL1, OL2, … …, OL (k-1), and OL (k) may be connected to the first switch SW1, and the other end thereof may be connected to PADs PAD1, PAD2, PAD3, PAD4, … …, PAD (k-1), and PAD (k) of the display panel 400. In an exemplary embodiment, in the case where the source driver 200 includes k buffers B1, B2, … …, B (k-1), and B (k), the detection circuit 250 may include k output lines OL1, OL2, … …, OL (k-1), and OL (k). The k output lines OL1, OL2, … …, OL (k-1), and OL (k) may be connected to k PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) in the non-display region, respectively.

First switch SW1 may connect each of output lines OL1, OL2, … …, OL (k-1), and OL (k) to buffers B1, B2, … …, B (k-1), and B (k). When the display apparatus 100 is driven, the first switch SW1 may be turned on. When the first switch SW1 is turned on, the output lines OL1, OL2, … …, OL (k-1), and OL (k) are connected to the buffers B1, B2, … …, B (k-1), and B (k) so that the DATA signals DATA output from the buffers B1, B2, … …, B (k-1), and B (k) can be supplied to the output lines OL1, OL2, … …, OL (k-1), and OL (k).

The first dummy amplifier 252 may supply the first detection voltage VD1 to the first detection line Ld 1. The first dummy amplifier 252 may receive the first detection voltage VD1 from the voltage generator 122 to supply the first detection voltage VD1 to the first detection line Ld 1.

The second dummy amplifier 254 may supply the second detection voltage VD2 to the second detection line Ld 2. The second dummy amplifier 254 may receive the second detection voltage VD2 from the voltage generator 122 to supply the second detection voltage VD2 to the second detection line Ld 2.

The second switch SW2 may connect the first detection line Ld1 to the 2n-1 th output lines OL1, OL3, … … and OL (k-1) (here, n is a natural number of 1 or more). In this embodiment, the second switch SW2 may connect the first detection line Ld1 and the odd-numbered output lines OL1, OL3, … …, and OL (k-1). The second switch SW2 may be turned on during a checking process for checking the bonding between the display panel 400 and the source driver 200. When the second switch SW2 is turned on, the first detection line Ld1 is connected to the 2n-1 output lines OL1, OL3, … …, and OL (k-1), so that the first detection voltage VD1 can be supplied.

The third switch SW3 may connect the second detection line Ld2 to the 2 n-th output lines OL2, OL4, … …, and OL (k). In this embodiment, the third switch SW3 may connect the second detection line Ld2 to the even-numbered output lines OL2, OL4, … …, and OL (k). The third switch SW3 may be turned on during a checking process for checking the bonding between the display panel 400 and the source driver 200. When the third switch SW3 is turned on, the second detection line Ld2 is connected to the 2 n-th output line OL2, OL4, … …, and OL (k), so that the second detection voltage VD2 may be supplied.

One end of the source driver 200 may be connected to PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) of the display panel 400, and the other end of the source driver 200 may be connected to the FPCB. In an exemplary embodiment, in the case where the source driver 200 is implemented as a COF, one end of a film on which an IC is mounted may be connected to PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) of the display panel 400, and the other end of the film may be connected to an FPCB. In an alternative exemplary embodiment, in the case where the source driver 200 is implemented as a COG, one end of the IC may be connected to PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) of the display panel 400, and the other end of the IC may be connected to a Printed Circuit Board (PCB). The other end of the PCB may be connected to the FPCB.

In an exemplary embodiment, the alignment detection circuit 300 may include a detection capacitor Cd and a voltage detection circuit 320.

The detection capacitor Cd may be connected between the first detection line Ld1 and the second detection line Ld 2. In one exemplary embodiment, for example, the detection capacitor Cd may include a first electrode (+) connected to the first detection line Ld1 and a second electrode (-) connected to the second detection line Ld 2. The detection capacitor Cd may store a voltage corresponding to a difference between the voltage applied to the first electrode (+) and the voltage applied to the second electrode (-).

The voltage detection circuit 320 may be connected to one end of the detection capacitor Cd. The voltage detection circuit 320 may be connected to a first electrode (+) or a second electrode (-) of the detection capacitor Cd. Referring to fig. 5, the voltage detection circuit 320 may include a comparator Comp to compare the voltage Vcd of the detection capacitor Cd with the reference voltage Vref. In an exemplary embodiment, the voltage detection circuit 320 may be connected to a first electrode (+) of the detection capacitor Cd. In this embodiment, a voltage having a positive value may be applied to the first electrode (+), and the voltage detection circuit 320 may compare the reference voltage Vref having a positive value with the voltage of the first electrode (+). In this embodiment, the voltage detection circuit 320 may output the shutdown signal SHUT when the voltage of the first electrode (+) is lower than the reference voltage Vref. In an alternative exemplary embodiment, the voltage detection circuit 320 may be connected to the second electrode (-) of the detection capacitor Cd. In this embodiment, a voltage having a negative value may be applied to the second electrode (-) and the voltage detection circuit 320 may compare the reference voltage Vref having a negative value with the voltage of the second electrode (-). In this embodiment, the voltage detection circuit 320 may output the turn-off signal SHUT when the voltage of the second electrode (-) is higher than the reference voltage Vref.

The alignment detection circuit 300 may be mounted on the FPCB connected to the source driver 200. The detection capacitor Cd and the voltage detection circuit 320 may be implemented as a driving chip mounted on the FPCB to be connected to the source driver 200.

Fig. 6A to 6C are diagrams for describing operations of the detection circuit and the alignment detection circuit of fig. 4.

Referring to fig. 6A, when the display apparatus 100 is driven, the first switch SW1 may be turned on, and the second switch SW2 and the third switch SW3 may be turned off. When the first switch SW1 is turned on, buffers B1, B2, … …, B (k-1), and B (k) of the buffer circuit 240 may be connected to output lines OL1, OL2, … …, OL (k-1), and OL (k), respectively. Each of the buffers B1, B2, … …, B (k-1), and B (k) may supply the DATA signal DATA to the PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) connected to the DATA lines of the display panel 400 through the output lines OL1, OL2, … …, OL (k-1), and OL (k). When the second switch SW2 is turned off, the first detection line Ld1 may not be connected to the output lines OL1, OL2, … … OL (k-1) and OL (k). In this embodiment, when the third switch SW3 is turned off, the second detection line Ld2 may not be connected to the output lines OL1, OL2, … …, OL (k-1), and OL (k).

Referring to fig. 6B, during a checking process for checking the coupling between the display panel 400 and the source driver 200, the first switch SW1 may be turned off, and the second switch SW2 and the third switch SW3 may be turned on. When the first switch SW1 is turned off, the buffers B1, B2, … …, B (k-1), and B (k) of the buffer circuit 240 may not be connected to the output lines OL1, OL2, … …, OL (k-1), and OL (k). When the second switch SW2 is turned on, the first detection line Ld1 may be connected to the 2n-1 output lines OL1, OL3, … …, and OL (k-1) among the output lines OL1, OL2, … …, OL (k-1), and OL (k). The first detection voltage VD1 can be supplied to the 2n-1 output lines OL1, OL3, … … and OL (k-1) through the first detection line Ld 1. When the third switch SW3 is turned on, the second detection line Ld2 may be connected to the 2 n-th output lines OL2, OL4, … …, and OL (k) among the output lines OL1, OL2, … …, OL (k-1), and OL (k). The second detection voltage VD2 may be supplied to the 2 n-th output lines OL2, OL4, … …, and OL (k) through the second detection line Ld 2.

The voltage of the first detection line Ld1 may be applied to a first electrode (+) of the detection capacitor Cd, and the voltage of the second detection line Ld2 may be applied to a second electrode (-). Here, the voltage applied to the first electrode (+) may have a positive value, and the voltage applied to the second electrode (-) may have a negative value. The voltage detection circuit 320 may be connected to a first electrode (+) or a second electrode (-) of the detection capacitor Cd. When the voltage detection circuit 320 is connected to the first electrode (+) of the detection capacitor Cd, the voltage detection circuit 320 may compare the voltage of the first electrode (+) of the detection capacitor Cd with a first reference voltage. When the voltage detection circuit 320 is connected to the second electrode (-) of the detection capacitor Cd, the voltage detection circuit 320 may compare the voltage of the second electrode (-) of the detection capacitor Cd with the second reference voltage. As shown in fig. 6B, when the output lines OL1, OL2, … …, OL (k-1), and OL (k) of the source driver 200 are normally combined with the PADs PAD1, PAD2, … … …, PAD (k-1), and PAD (k) of the display panel 400, the voltage detection circuit 320 may not output the turn-off signal SHUT. The voltage detection circuit 320 may not output the turn-off signal SHUT when the voltage of the first electrode (+) is equal to or higher than the first reference voltage. The voltage detection circuit 320 may not output the turn-off signal SHUT when the voltage of the second electrode (-) is equal to the second reference voltage or lower than the second reference voltage.

Referring to fig. 6C, the output lines OL1, OL2, … …, OL (k-1), and OL (k) of the source driver 200 may be misaligned with and combined with the PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) of the display panel 400. As shown in fig. 6C, when the third output line OL3 of the source driver 200 is coupled to the second PAD2 of the display panel 400, the voltage supplied to the first electrode (+) of the detection capacitor Cd may decrease and the voltage supplied to the second electrode (-) may increase, so that the voltage levels of the voltages applied to the first electrode (+) and the second electrode (-) of the detection capacitor Cd may vary. When the voltage detection circuit 320 is connected to the first electrode (+) of the detection capacitor Cd, the voltage detection circuit 320 may compare the voltage of the first electrode (+) with a first reference voltage, and when the voltage of the first electrode (+) is lower than the first reference voltage, the voltage detection circuit 320 may output the turn-off signal SHUT. When the voltage detection circuit 320 is connected to the second electrode (-) of the detection capacitor Cd, the voltage detection circuit 320 may compare the voltage of the second electrode (-) with a second reference voltage, and when the voltage of the second electrode (-) is higher than the second reference voltage, the voltage detection circuit 320 may output the turn-off signal SHUT. Fig. 6C illustrates a short circuit condition caused by connection between the output lines (i.e., the second output line OL2 and the third output line OL3) of the source driver 200 and the second PAD2 due to misalignment between the source driver 200 and the display panel 400. However, when the PADs PAD1, PAD2, … …, PAD (k-1), and PAD (k) of the display panel 400 are connected due to misalignment between the source driver 200 and the display panel 400 (see fig. 2B), a short circuit may occur. Even in such a case, the voltages applied to the first and second detection lines Ld1 and Ld2 may change, so that the voltage levels of the voltages applied to the first and second electrodes (+) and (-) of the detection capacitor Cd may change.

In the exemplary embodiment of the present invention, as described above, the source driver 200 and the alignment detection circuit 300 are configured to supply the first detection voltage VD1 to the 2n-1 output lines OL1, OL3, … …, and OL (k-1) through the first detection line Ld1, supply the second detection voltage VD2 to the 2n output lines OL2, OL4, … …, and OL (k) through the second detection line Ld2, and detect the voltage of the detection capacitor Cd connected between the first detection line Ld1 and the second detection line Ld2, thereby detecting misalignment between the pads of the display panel 400 and the output lines OL1, OL2, … …, OL (k-1), and OL (k), (k) of the source driver 200 during the inspection process of the display apparatus 100. Therefore, in this embodiment, the bonding failure between the display panel 400 and the source driver 200 can be easily detected.

Exemplary embodiments of the present invention may be applied to electronic devices including display devices, for example, televisions, computer display screens, laptop computers, digital cameras, cellular phones, smart phones, smartpads, tablet Personal Computers (PCs), Personal Digital Assistants (PDAs), Portable Multimedia Players (PMPs), MP3 players, car navigation systems, video phones, Head Mounted Display (HMD) devices, and the like.

The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.