阅读说明：本技术 显示装置及其制造方法 (Display device and method for manufacturing the same ) 是由 李旺宇 高武恂 禹珉宇 于 2020-02-10 设计创作，主要内容包括：本发明提供一种显示装置及其制造方法。显示装置包括：基底基板；有源层,配置在所述基底基板上且包括第1有源图案；第1绝缘层,配置在所述有源层上；第1栅极导电层,配置在所述第1绝缘层上；第2绝缘层,配置在所述第1栅极导电层上；以及第3栅极导电层,包括配置在所述第2绝缘层上的第3a栅极图案。所述第3栅极导电层不与所述第1栅极导电层直接连接。(The invention provides a display device and a method of manufacturing the same. The display device includes: a base substrate; an active layer disposed on the base substrate and including a 1 st active pattern; a 1 st insulating layer disposed on the active layer; a 1 st gate conductive layer disposed on the 1 st insulating layer; a 2 nd insulating layer disposed on the 1 st gate conductive layer; and a 3 rd gate conductive layer including a 3 rd gate pattern disposed on the 2 nd insulating layer. The 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer.)

1. A display device, comprising:

a base substrate;

an active layer disposed on the base substrate and including a 1 st active pattern;

a 1 st insulating layer disposed on the active layer;

a 1 st gate conductive layer disposed on the 1 st insulating layer;

a 2 nd insulating layer disposed on the 1 st gate conductive layer; and

a 3 rd gate conductive layer including a 3 rd gate pattern disposed on the 2 nd insulating layer,

the 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer.

2. The display device according to claim 1,

the 3 rd gate pattern is directly connected to the 1 st active pattern through a 1 st contact hole, wherein the 1 st contact hole is formed through the 2 nd insulating layer and the 1 st insulating layer.

3. The display device according to claim 2, further comprising:

a 4 th insulating layer disposed on the 3 rd gate conductive layer; and

a source-drain conductive layer disposed on the 4 th insulating layer and including a 1 st source-drain pattern and a 2 nd source-drain pattern,

the 1 st gate conductive layer includes a 1 st gate pattern and a 1 st gate pattern, the 1 st gate pattern overlapping the 1 st active pattern, the 1 st gate pattern being separated from the 1 st gate pattern,

the 1 st source-drain pattern is directly connected to the 3 rd gate pattern through a 2 nd contact hole, wherein the 2 nd contact hole is formed through the 4 th insulating layer,

the 2 nd source/drain pattern is directly connected to the 1b th gate pattern through a 3 rd contact hole, wherein the 3 rd contact hole is formed through the 4 th insulating layer and the 2 nd insulating layer.

4. The display device according to claim 1, further comprising:

a 2 nd gate conductive layer disposed on the 2 nd insulating layer; and

a 3 rd insulating layer disposed on the 2 nd gate conductive layer and below the 3 rd gate conductive layer,

the 3 rd gate conductive layer is not directly connected with the 2 nd gate conductive layer.

5. The display device according to claim 1,

the active layer includes polysilicon.

6. The display device according to claim 1,

the 1 st gate conductive layer is formed of a single layer of aluminum or an aluminum alloy.

7. The display device according to claim 6,

the 1 st gate conductive layer includes a main conductive layer and a capping layer disposed on the main conductive layer.

8. The display device according to claim 7,

the main conductive layer is formed of a single layer of aluminum or an aluminum alloy, and the cover layer includes titanium and hasThe following thicknesses.

9. The display device according to claim 1, further comprising:

a sealing member disposed between a display area in which an image is displayed and a peripheral area surrounding the display area; and

a sealing substrate sealing the structure in the display region together with the sealing member,

the 1 st gate conductive layer further includes a 1 st connection wiring arranged to overlap with the sealing member,

the 3 rd gate conductive layer further includes a shield electrode disposed between the 1 st connection wiring and the sealing member.

10. A display device, comprising:

a base substrate including a display area displaying an image and a peripheral area as a non-display area, wherein the peripheral area is adjacent to the display area;

an active layer disposed on the base substrate;

a 1 st insulating layer disposed on the active layer;

a 1 st gate conductive layer disposed on the 1 st insulating layer and including a 1 st connection wiring;

a 2 nd insulating layer disposed on the 1 st gate conductive layer;

a 3 rd gate conductive layer disposed on the 2 nd insulating layer and including a 1 st shield electrode overlapping the 1 st connection wiring;

a 4 th insulating layer disposed on the 3 rd gate conductive layer;

a sealing member disposed on the 4 th insulating layer, between the display region and the peripheral region, and overlapping the 1 st shield electrode; and

and a sealing substrate sealing the structure in the display region together with the sealing member.

11. A method of manufacturing a display device, comprising:

a step of forming an active layer including a 1 st active pattern on a base substrate;

a step of forming a 1 st insulating layer on the active layer;

a step of forming a 1 st gate conductive layer on the 1 st insulating layer;

a step of forming a 2 nd insulating layer on the 1 st gate conductive layer;

forming a 1 st contact hole exposing the 1 st active pattern through the 2 nd insulating layer and the 1 st insulating layer; and

a step of forming a 3 rd gate conductive layer on the 2 nd insulating layer, the 3 rd gate conductive layer including a 3 rd gate pattern directly connected to the 1 st active pattern through the 1 st contact hole,

in the step of forming the 1 st contact hole, the 1 st gate conductive layer is entirely covered with the 2 nd insulating layer.

12. The method for manufacturing a display device according to claim 11,

after the step of forming the 1 st contact hole and before the step of forming the 3 rd gate conductive layer, the method further includes:

and a step of cleaning a surface of the 1 st active pattern exposed through the 1 st contact hole using a cleaning solution having an etching force with respect to metal.

13. The method for manufacturing a display device according to claim 12,

in the step of performing a cleaning, a wet cleaning is performed using a buffered oxide etchant cleaning solution.

14. The method for manufacturing a display device according to claim 11,

after forming the 1 st gate conductive layer and before forming the 2 nd insulating layer, further comprising:

doping impurities to a part of the active layer to form a source drain region; and

and activating the active layer by performing heat treatment for activating the dopant of the active layer.

15. The method for manufacturing a display device according to claim 11,

the 1 st gate conductive layer includes a connection wiring,

the 3 rd gate conductive layer includes a shield electrode overlapping the connection wiring.

16. The method for manufacturing a display device according to claim 15, further comprising:

a step of forming a sealing member on the sealing substrate;

bonding the sealing substrate and the base substrate on which the 3 rd gate conductive layer is formed, using the sealing member; and

a step of irradiating the sealing member with a laser beam through the sealing substrate to cure the sealing member,

the shield electrode is located between the sealing member and the connection wiring so as to block the laser light from being irradiated to the connection wiring.

17. The method for manufacturing a display device according to claim 11,

before the step of forming the 3 rd gate conductive layer, the method further comprises:

a step of forming a 2 nd gate conductive layer on the 2 nd insulating layer; and

and forming a 3 rd insulating layer on the 2 nd gate conductive layer.

18. The method for manufacturing a display device according to claim 11,

the 1 st gate conductive layer is formed of a single layer of aluminum or an aluminum alloy.

19. The method for manufacturing a display device according to claim 11,

the 3 rd gate conductive layer includes molybdenum or a molybdenum alloy.

Technical Field

The present invention relates to a display device and a method of manufacturing the display device, and more particularly, to a display device with improved display quality and a method of manufacturing the display device.

Background

Recently, with the development of technology, display products having a smaller size, lighter weight, and more excellent performance have been produced. Conventionally, a Cathode Ray Tube (CRT) television has been widely used as a display device because it has many advantages in terms of performance and price, but a display device, such as a plasma display device, a liquid crystal display device, an organic light emitting display device, and the like, which overcomes the disadvantages of the CRT and has advantages such as miniaturization, weight reduction, and low power consumption in terms of miniaturization and portability, has been attracting attention.

The display device includes a gate conductive layer constituting a scan wiring or the like. When the display device is increased in size and resolution and high-speed driving is required, a scanning signal transmitted through the gate conductive layer is delayed, and display quality is degraded. Accordingly, it is necessary to solve problems that may occur in the process while reducing the resistance value of the gate conductive layer.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a display device including a low-resistance gate conductive layer to improve display quality.

Another object of the present invention is to provide a method of manufacturing the display device.

A display device according to an embodiment for achieving the object of the present invention includes: a base substrate; an active layer disposed on the base substrate and including a 1 st active pattern; a 1 st insulating layer disposed on the active layer; a 1 st gate conductive layer disposed on the 1 st insulating layer; a 2 nd insulating layer disposed on the 1 st gate conductive layer; and a 3 rd gate conductive layer including a 3 rd gate pattern disposed on the 2 nd insulating layer. The 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer.

In an embodiment of the present invention, the 3 rd gate pattern may be directly connected to the 1 st active pattern through a 1 st contact hole, wherein the 1 st contact hole is formed through the 2 nd insulating layer and the 1 st insulating layer.

In an embodiment of the present invention, the display device may further include: a 4 th insulating layer disposed on the 3 rd gate conductive layer; and a source/drain conductive layer disposed on the 4 th insulating layer and including a 1 st SD pattern and a 2 nd SD pattern. The 1 st gate conductive layer includes a 1 st gate pattern and a 1b gate pattern, the 1 st gate pattern overlaps the 1 st active pattern, and the 1b gate pattern may be separated from the 1 st gate pattern. The 1 st SD pattern may be directly connected to the 3 rd gate pattern through a 2 nd contact hole, wherein the 2 nd contact hole is formed through the 4 th insulating layer. The 2 nd SD pattern may be directly connected to the 1b th gate pattern through a 3 rd contact hole, wherein the 3 rd contact hole is formed through the 4 th insulating layer and the 2 nd insulating layer.

In an embodiment of the present invention, the display device may further include: a 2 nd gate conductive layer disposed on the 2 nd insulating layer; and a 3 rd insulating layer disposed on the 2 nd gate conductive layer and below the 3 rd gate conductive layer. The 3 rd gate conductive layer may not be directly connected with the 2 nd gate conductive layer.

In an embodiment of the present invention, the active layer may include polysilicon.

In an embodiment of the present invention, the 1 st gate conductive layer may be formed of a single layer of aluminum or an aluminum alloy.

In an embodiment of the invention, the 1 st gate conductive layer may include a main conductive layer and a capping layer disposed on the main conductive layer.

In an embodiment of the present invention, the main conductive layer is formed of a single layer of aluminum or aluminum alloy, and the capping layer includes titanium (Ti) and may haveThe following thicknesses.

In an embodiment of the present invention, the display device may further include: a sealing member disposed between a display area in which an image is displayed and a peripheral area surrounding the display area; and a sealing substrate that seals the structure in the display region together with the sealing member. The 1 st gate conductive layer may further include a 1 st connection wiring arranged to overlap with the sealing member. The 3 rd gate conductive layer may further include a shield electrode disposed between the 1 st connection wiring and the sealing member.

A display device according to an embodiment for achieving the object of the present invention described above includes: a base substrate including a display area displaying an image and a peripheral area adjacent to the display area as a non-display area; an active layer disposed on the base substrate; a 1 st insulating layer disposed on the active layer; a 1 st gate conductive layer disposed on the 1 st insulating layer and including a 1 st connection wiring; a 2 nd insulating layer disposed on the 1 st gate conductive layer; a 3 rd gate conductive layer disposed on the 2 nd insulating layer and including a 1 st shield electrode overlapping the 1 st connection wiring; a 4 th insulating layer disposed on the 3 rd gate conductive layer; a sealing member disposed on the 4 th insulating layer, between the display region and the peripheral region, and overlapping the 1 st shield electrode; and a sealing substrate that seals the structure in the display region together with the sealing member.

A method of manufacturing a display device according to an embodiment for achieving the above object of the present invention includes: a step of forming an active layer including a 1 st active pattern on a base substrate; a step of forming a 1 st insulating layer on the active layer; a step of forming a 1 st gate conductive layer on the 1 st insulating layer; a step of forming a 2 nd insulating layer on the 1 st gate conductive layer; forming a 1 st contact hole exposing the 1 st active pattern through the 2 nd insulating layer and the 1 st insulating layer; and a step of forming a 3 rd gate conductive layer on the 2 nd insulating layer, the 3 rd gate conductive layer including a 3 rd gate pattern directly connected to the 1 st active pattern through the 1 st contact hole. In the step of forming the 1 st contact hole, the 1 st gate conductive layer is entirely covered with the 2 nd insulating layer.

In an embodiment of the invention, after the step of forming the 1 st contact hole and before the step of forming the 3 rd gate conductive layer, the method may further include: and a step of cleaning a surface of the 1 st active pattern exposed through the 1 st contact hole using a cleaning solution having an etching force with respect to metal.

In an embodiment of the invention, in the step of performing the cleaning, a BOE (buffered oxide etch) cleaning solution may be used for performing the wet cleaning.

In an embodiment of the invention, after forming the 1 st gate conductive layer and before forming the 2 nd insulating layer, the manufacturing method may further include: doping impurities to a part of the active layer to form a source drain region; and a step of performing heat treatment for dopant activation (activation) of the active layer to activate the active layer.

In an embodiment of the present invention, the 1 st gate conductive layer may include a connection wiring. The 3 rd gate conductive layer may include a shield electrode overlapping the connection wiring.

In an embodiment of the present invention, the manufacturing method may further include: a step of forming a sealing member on the sealing substrate; bonding the sealing substrate and the base substrate on which the 3 rd gate conductive layer is formed, using the sealing member; and a step of irradiating the sealing member with laser light through the sealing substrate to cure the sealing member. The shield electrode is located between the sealing member and the connection wiring so that the irradiation of the laser light to the connection wiring can be blocked.

In an embodiment of the invention, before the step of forming the 3 rd gate conductive layer, the manufacturing method may further include: a step of forming a 2 nd gate conductive layer on the 2 nd insulating layer; and a step of forming a 3 rd insulating layer on the 2 nd gate conductive layer.

In an embodiment of the present invention, the 1 st gate conductive layer may be formed of a single layer of aluminum or an aluminum alloy.

In an embodiment of the invention, the 3 rd gate conductive layer may include molybdenum or a molybdenum alloy.

According to the present embodiment, a display device includes: a base substrate; an active layer disposed on the base substrate and including a 1 st active pattern; a 1 st insulating layer disposed on the active layer; a 1 st gate conductive layer disposed on the 1 st insulating layer; a 2 nd insulating layer disposed on the 1 st gate conductive layer; and a 3 rd gate conductive layer including a 3 rd gate pattern disposed on the 2 nd insulating layer. Since the 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer or the 2 nd gate conductive layer through a contact hole, when a cleaning process using a cleaning solution is required, the 1 st gate conductive layer and the 2 nd gate conductive layer are entirely covered with the 2 nd insulating layer and the 3 rd insulating layer, and thus the 1 st gate conductive layer and the 2 nd gate conductive layer do not require an additional cover layer or only a very thin cover layer is not problematic. Thus, the display device can be realized with a simple structure which solves the process problem and reduces the manufacturing cost while reducing the wiring resistance.

Further, the laser light for curing the sealing member is irradiated to the sealing member through the sealing substrate, and thus the shielding electrode can block the laser light from being irradiated to the connection wiring. This can prevent the connection wiring including aluminum from being damaged by the irradiation of the laser beam.

However, the effects of the present invention are not limited to the above-described effects, and various modifications can be made without departing from the spirit and scope of the present invention.

Drawings

Fig. 1 is a sectional view of a display device according to an embodiment of the present invention.

Fig. 2 is a top view of a display device according to an embodiment of the present invention.

Fig. 3 is a sectional view taken along line I-I 'and line II-II' of fig. 2.

Fig. 4 is a partially enlarged sectional view of a display device according to an embodiment of the present invention.

Fig. 5A to 5F are cross-sectional views for explaining a method of manufacturing the display device of fig. 3.

Fig. 6 is a block diagram illustrating an electronic device according to an embodiment of the present invention.

Fig. 7A is a diagram showing an example in which the electronic apparatus of fig. 6 is implemented by a television set.

Fig. 7B is a diagram showing an example of implementing the electronic device of fig. 6 by a smartphone.

In the figure: 100-a base substrate; 110-a buffer layer; 120-1 st insulating layer; 130-2 nd insulating layer; 140-insulating layer 3; 150-4 th insulating layer; 180-light emitting structure; 200-sealing the substrate.

Detailed Description

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

Fig. 1 is a sectional view of a display device according to an embodiment of the present invention.

Referring to fig. 1, the display device may include a base substrate 100, a buffer layer 110, an active layer, a 1 st insulating layer 120, a 1 st gate conductive layer, a 2 nd insulating layer 130, a 2 nd gate conductive layer, a 3 rd insulating layer 140, a 3 rd gate conductive layer, a 4 th insulating layer 150, and a source drain conductive layer.

The base substrate 100 may be made of a transparent or opaque material. For example, the base substrate 100 may include a quartz substrate, a synthetic quartz (synthetic quartz) substrate, a calcium fluoride substrate, a fluorine-doped quartz (F-doped quartz) substrate, a soda lime (soda lime) glass substrate, a non-alkali (non-alkali) glass substrate, and the like. Alternatively, the base substrate 100 may also be formed of a transparent resin substrate having flexibility. As an example of a transparent resin substrate that can be used as the base substrate 100, a polyimide substrate can be cited.

The buffer layer 110 may be disposed on the entire base substrate 100. The buffer layer 110 may prevent a phenomenon in which metal atoms or impurities are diffused from the base substrate 100 to the active layer, and adjust a heat transfer rate during a crystallization process for forming the active layer, so that the active layer may be substantially uniform. In addition, in the case where the surface of the base substrate 100 is not uniform, the buffer layer 110 may play a role of improving the flatness of the surface of the base substrate 100.

The active layer may be disposed on the buffer layer 110. The active layer may include a 1 st active pattern ACTa and a 2 nd active pattern ACTb. The active layer may include polysilicon (Poly Crystal Silicon). The active pattern ACT may include: a drain region and a source region doped (doping) with impurities; and a channel region between the drain region and the source region. The polysilicon may be formed by depositing amorphous silicon and then crystallizing it. Here, the amorphous silicon may be crystallized by various methods such as RTA (rapid thermal annealing), SPC (solid phase crystallization), ELA (excimer laser annealing), MIC (metal induced crystallization), MILC (metal induced lateral crystallization), and SLS (sequential lateral solidification).

The 1 st insulating layer 120 may be disposed on the buffer layer 110 provided with the active layer. The 1 st insulating layer 120 may sufficiently cover the active layer on the buffer layer 110, and may have a substantially flat upper surface without generating a level difference around the active layer. In contrast, the 1 st insulating layer 120 may cover the active layer on the buffer layer 110, and may be configured with a substantially equal thickness along a Profile (Profile) of the active layer. The 1 st insulating layer 120 may include an inorganic insulating material such as a silicon compound or a metal oxide.

The 1 st gate conductive layer may be disposed on the 1 st insulating layer 120. The 1 st gate conductive layer may include a 1 st gate pattern GAT1a and a 1 st gate pattern GAT1b separated from the 1 st gate pattern GAT1 a. The 1 st gate pattern GAT1a may overlap the 1 st active pattern ACTa to form a gate electrode of the 1 st thin film transistor. The 1 st gate pattern GAT1b may overlap the 2 nd active pattern ACTb to form a gate electrode of the 2 nd thin film transistor. The 1 st gate conductive layer may further include a signal wiring such as a scan line for transmitting a scan signal. The 1 st thin film transistor may be a switching element of a pixel, and the 2 nd thin film transistor may be a driving element of the pixel.

The 1 st gate conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like. For example, the 1 st gate conductive layer may be a single layer including aluminum (Al) or an aluminum alloy having low resistance and high conductivity. This can reduce wiring resistance.

The 2 nd insulating layer 130 may be disposed on the 1 st insulating layer 120 provided with the 1 st gate conductive layer. The 2 nd insulating layer 130 may sufficiently cover the 1 st gate conductive layer on the 1 st insulating layer 120, and may have a substantially flat upper surface without generating a step around the 1 st gate conductive layer. In contrast, the 2 nd insulating layer 130 may cover the 1 st gate conductive layer on the 1 st insulating layer 120, and may be disposed with a substantially equal thickness along the profile of the 1 st gate conductive layer. The 2 nd insulating layer 130 may include an inorganic insulating substance such as a silicon compound or a metal oxide.

The 2 nd gate conductive layer may be disposed on the 2 nd insulating layer 130. The 2 nd gate conductive layer may include a 2a nd gate pattern GAT2a and a 2b nd gate pattern GAT2b separated from the 2a nd gate pattern GAT2 a. The 2 nd gate conductive layer may further include a signal wiring such as a scan line for transmitting a scan signal.

The 2 nd gate conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like. For example, the 2 nd gate conductive layer may be a single layer including aluminum (Al) or an aluminum alloy having low resistance and high conductivity. This can reduce the wiring resistance.

The 3 rd insulating layer 140 may be disposed on the 2 nd insulating layer 130 provided with the 2 nd gate conductive layer. The 3 rd insulating layer 140 may substantially cover the 2 nd gate conductive layer on the 2 nd insulating layer 130, and may have a substantially flat upper surface without generating a step around the 2 nd gate conductive layer. In contrast, the 3 rd insulating layer 140 may cover the 2 nd gate conductive layer on the 2 nd insulating layer 130, and may be configured with a substantially equal thickness along the profile of the 2 nd gate conductive layer. The 3 rd insulating layer 140 may include an inorganic insulating material such as a silicon compound or a metal oxide.

The 3 rd gate conductive layer may be disposed on the 3 rd insulating layer 140. The 3 rd gate conductive layer may include a 3a th gate pattern GAT3a and a 3b th gate pattern GAT3b separated from the 3a th gate pattern GAT3 a.

The 3 rd gate conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like. For example, the 3 rd gate conductive layer may be a single layer including molybdenum (Mo) or a molybdenum alloy. According to other embodiments, the 3 rd gate conductive layer may have a stacked structure including: a main conductive layer including molybdenum (Mo) or a molybdenum alloy; and a capping layer including titanium (Ti) disposed on the main conductive layer.

The 3 rd gate conductive layer may be directly connected to the active layer through a contact hole formed through the 3 rd to 1 st insulating layers 140 to 120. However, the 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer or the 2 nd gate conductive layer through a contact hole.

For example, the 3a gate pattern GAT3a may be directly connected to the 1 st active pattern ACTa through a 1 st contact hole, wherein the 1 st contact hole is formed through the 3 rd to 1 st insulating layers 140 to 120.

The 4 th insulating layer 150 may be disposed on the 3 rd insulating layer 140 provided with the 3 rd gate conductive layer. The 4 th insulating layer 150 may substantially cover the 3 rd gate conductive layer on the 3 rd insulating layer 140, and may have a substantially flat upper surface without generating a step around the 3 rd gate conductive layer. In contrast, the 4 th insulating layer 150 may cover the 3 rd gate conductive layer on the 3 rd insulating layer 140, and may be disposed with a substantially equal thickness along the profile of the 3 rd gate conductive layer. The 4 th insulating layer 150 may include an inorganic insulating material such as a silicon compound or a metal oxide.

The source/drain conductive layer may be disposed on the 4 th insulating layer 150. The source/drain conductive layer may include a 1 st SD (source-drain) pattern SDa, a 2 nd SD pattern SDb, and a 3 rd SD pattern SDc.

The source-drain conductive layer may be directly connected to the 3 rd gate conductive layer, the 2 nd gate conductive layer, or the 1 st gate conductive layer through a contact hole. For example, the 1 st SD pattern SDa may be directly connected to the 3 rd gate pattern GAT3a through a 2 nd contact hole, wherein the 2 nd contact hole is formed through the 4 th insulating layer 150. The 2 nd SD pattern SDb may be directly connected to the 2 nd gate pattern GAT2a through a 3 rd contact hole, wherein the 3 rd contact hole is formed through the 4 th insulating layer 150 and the 3 rd insulating layer 140. The 3 rd SD pattern SDc may be directly connected to the 1b th gate pattern GAT1b through a 4 th contact hole, wherein the 4 th contact hole is formed through the 4 th insulating layer 150, the 3 rd insulating layer 140, and the 2 nd insulating layer 130.

The source/drain conductive layer may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive substance, or the like. The source-drain conductive layer may be formed as a plurality of layers. For example, the source-drain conductive layer may include a titanium (Ti) layer and a molybdenum (Mo) layer on the titanium layer (Ti/Mo structure). Alternatively, the source and drain conductive layers may include a titanium (Ti) layer, an aluminum (Al) layer on the titanium layer, and a titanium (Ti) layer on the aluminum layer (Ti/Al/Ti structure).

The display device may further include a light-emitting structure or the like disposed on the source/drain conductive layer (see fig. 3 and the like). A detailed description thereof will be omitted.

As the display device is increased in size, resolution increases, and the necessity for high-speed driving also increases. Accordingly, it is necessary to reduce the wiring resistance of the 1 st gate conductive layer or the 2 nd gate conductive layer, and in the case where the 1 st gate conductive layer or the 2 nd gate conductive layer is formed as a conductive layer including molybdenum, it is limited to increase the thickness of the conductive layer in order to reduce the wiring resistance.

On the contrary, even if a metal having a low resistance value, excellent conductivity and easy process is used as the 1 st gate conductive layer or the 2 nd gate conductive layer, a buffer Oxide Etchant (Buffered Oxide Etchant) is used for the heat treatment or BOE (Buffered Oxide Etchant) of the 1 st gate conductive layer or the 2 nd gate conductive layer in the process) Cleaning solutions, etc., the possibility of occurrence of defects still remains. Thus, it is necessary to further provide several thousands of conductive layersA graded thicker thickness of the cover layer. Thus, there is a problem that the wiring design is not facilitated according to the increased thickness, and it is difficult to finely process the pattern.

In contrast, according to the present embodiment, the 3 rd gate conductive layer is not directly connected to the 1 st gate conductive layer or the 2 nd gate conductive layer through a contact hole, and thus, when a process requiring cleaning using the BOE cleaning solution is performed, the 1 st gate conductive layer and the 2 nd gate conductive layer are entirely covered with the 2 nd insulating layer 130 and the 3 rd insulating layer 140, and thus, the 1 st gate conductive layer and the 2 nd gate conductive layer do not require an additional cover layer or use of only a very thin cover layer is not problematic. Thus, the display device can be realized with a simple structure that solves the process problem and reduces the manufacturing cost while reducing the wiring resistance.

Fig. 2 is a top view of a display device according to an embodiment of the present invention. Fig. 3 is a sectional view taken along line I-I 'and line II-II' of fig. 2.

Referring to fig. 2 and 3, the display device may include a display area DA displaying an image and a peripheral area PA surrounding the display area DA as a non-display area.

The display device may include a plurality of pixels PX arranged in a matrix form in the display area DA.

The display device may further include: a drive circuit which is arranged in the peripheral area PA and generates drive signals for driving the plurality of pixels PX; and a connection wiring SL for transmitting a driving signal to the display area DA. For example, the connection wiring SL may include a 1 st connection wiring SL1 and a 2 nd connection wiring SL 2.

The sealing member CS may be disposed between the display region DA and the peripheral region PA, and between the sealing substrate 200 and the base substrate 100, to seal the display region DA in which the light emitting structure 180 is formed. The sealing member CS may be formed of a material that melts upon application of a predetermined thermal energy. The sealing part CS may include a substance cured by light. For example, the sealing member CS may include a glass frit (glass frit).

Here, the connection wiring SL may be disposed to pass through a boundary between the display area DA and the peripheral area PA, and may be disposed to overlap the sealing member CS.

Referring again to fig. 3, the display device may include a base substrate 100, a buffer layer 110, an active layer, a 1 st insulating layer 120, a 1 st gate conductive layer, a 2 nd insulating layer 130, a 2 nd gate conductive layer, a 3 rd insulating layer 140, a 3 rd gate conductive layer, a 4 th insulating layer 150, a source drain conductive layer, a via insulation layer (via insulation layer)160, a pixel definition film PDL, the light emitting structure 180, the sealing member CS, and the sealing substrate 200.

The components of the display device are substantially the same as those of the display device described with reference to fig. 1 except for the 1 st connecting line SL1 and the 2 nd connecting line SL2, the shield electrode, the sealing member CS, the through-hole insulating layer 160, the pixel defining film PDL, the light-emitting structure 180, and the sealing substrate 200. And therefore, duplicate explanation is omitted.

The buffer layer 110 may be disposed on the base substrate 100. The active layer may be disposed on the buffer layer 110. The active layer may include a 1 st active pattern ACTa and a 2 nd active pattern ACTb. The 1 st insulating layer 120 may be disposed on the buffer layer 110 provided with the active layer.

The 1 st gate conductive layer may be disposed on the 1 st insulating layer 120. The 1 st gate conductive layer may include a 1 st gate pattern GAT1a and a 1 st gate pattern GAT1b separated from the 1 st gate pattern GAT1 a. The 1 st gate conductive layer may further include the 1 st connection wiring SL 1.

The 2 nd insulating layer 130 may be disposed on the 1 st insulating layer 120 provided with the 1 st gate conductive layer.

The 2 nd gate conductive layer may be disposed on the 2 nd insulating layer 130. The 2 nd gate conductive layer may include a 2a nd gate pattern GAT2a and a 2b nd gate pattern GAT2b (not shown in fig. 3) separated from the 2a nd gate pattern GAT2 a. The 2 nd gate conductive layer may further include the 2 nd connecting wiring SL 2.

The 3 rd insulating layer 140 may be disposed on the 2 nd insulating layer 130 provided with the 2 nd gate conductive layer.

The 3 rd gate conductive layer may be disposed on the 3 rd insulating layer 140. The 3 rd gate conductive layer may include a 3a th gate pattern GAT3a and a 3b th gate pattern GAT3b (not shown in fig. 3) separated from the 3a th gate pattern GAT3 a. The 3 rd gate conductive layer may further include the shield electrode. The shielding electrodes may include a 1 st shielding electrode SE1 and a 2 nd shielding electrode SE 2. The 1 st shield electrode SE1 may be disposed to overlap the 1 st connection wiring SL 1. The 2 nd shield electrode SE2 may be disposed to overlap the 2 nd connecting wiring SL 2. According to other embodiments, the 1 st shield electrode SE1 and the 2 nd shield electrode SE2 may be formed in one pattern so as to also overlap the 1 st connecting wiring SL1 and the 2 nd connecting wiring SL2 at the same time. The 1 st shield electrode SE1 and the 2 nd shield electrode SE2 may float (floating), or may be applied with a certain voltage.

The 4 th insulating layer 150 may be disposed on the 3 rd insulating layer 140 provided with the 3 rd gate conductive layer. The source/drain conductive layer may be disposed on the 4 th insulating layer 150. The source and drain conductive layers may include a 1 st SD pattern SDa, a 2 nd SD pattern SDb, and a 3 rd SD pattern SDc.

The via insulating layer 160 may be disposed on the source and drain conductive layer. The via hole insulating layer 160 may have a single-layer structure or a multilayer structure including at least 2 insulating films. The via hole insulating layer 160 may be formed using an organic substance such as a photoresist, an acrylic resin, a polyimide resin, a polyamide resin, or a siloxane-based resin.

The light emitting structure 180 may include a 1 st electrode 181, a light emitting layer 182, and a 2 nd electrode 183.

The 1 st electrode 181 may be disposed on the via insulating layer 160. The 1 st electrode 181 may be formed using a reflective material or a light-transmissive material according to a light-emitting mode of the display device. In an exemplary embodiment, the 1 st electrode 181 may be formed of a single layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and/or a transparent conductive substance film.

The pixel defining film PDL may be disposed on the via hole insulating layer 160 provided with the 1 st electrode 181. The pixel defining film PDL may be formed using an organic substance, an inorganic substance, or the like. For example, the pixel defining film PDL may be formed using a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, a silicon compound, or the like. According to an exemplary embodiment, the pixel defining film PDL may be etched to form an opening (exposing) exposing a portion of the 1 st electrode 181. The light-emitting region and the non-light-emitting region of the display device can be defined by the opening of such a pixel definition film PDL. For example, the portion where the opening of the pixel definition film PDL is located may correspond to the light emitting region, and the non-light emitting region may correspond to a portion adjacent to the opening of the pixel definition film PDL.

The light emitting layer 182 may be disposed on the 1 st electrode 181 exposed through the opening of the pixel defining film PDL. Further, the light emitting layer 182 may extend onto the sidewall of the opening of the pixel defining film PDL. In an exemplary embodiment, the light emitting layer 182 may have a multi-layer structure including an organic light Emitting Layer (EL), a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and the like. In other embodiments, the hole injection layer, the hole transport layer, the electron injection layer, and the like may be formed in common in correspondence with a plurality of pixels in addition to the organic light emitting layer. The organic light emitting layer of the light emitting layer 182 may be formed using a light emitting substance that can generate light of different colors such as red light, green light, and blue light from each pixel of the display device. According to other exemplary embodiments, the organic light emitting layer of the light emitting layer 182 may have a structure in which a plurality of light emitting substances that can emit light of different colors such as red light, green light, and blue light are stacked to emit white light. In this case, the light-emitting structure is formed in common in correspondence with a plurality of pixels, and the respective pixels can be separated by color filter layers.

The 2 nd electrode 183 may be disposed on the pixel defining film PDL and the light emitting layer 182. The 2 nd electrode 183 may include a substance having a light-transmitting property or a substance having a reflecting property according to a light-emitting mode of the display device. In an exemplary embodiment, the 2 nd electrode 183 may also be formed of a single layer structure or a multi-layer structure including a metal film, an alloy film, a metal nitride film, a conductive metal oxide film, and/or a transparent conductive substance film.

The sealing member CS may be disposed on the 4 th insulating layer 150 to overlap the 1 st connection wiring SL1, the 2 nd connection wiring SL2, the 1 st shield electrode SE1, and the 2 nd shield electrode SE 2. The sealing substrate 200 and the sealing member CS may seal the light emitting structure 180 disposed in the display region DA to prevent penetration of moisture and oxygen from the outside.

The sealing member CS is formed on the sealing substrate 200, then bonded to the base substrate 100, and then cured by laser irradiation or the like, thereby sealing the display region DA in which the light emitting structure 180 is disposed. At this time, the laser beam is irradiated to the sealing member CS through the sealing substrate 200, and thus the shielding electrode including molybdenum can block the laser beam from being irradiated to the 1 st connecting line SL1 and the 2 nd connecting line SL 2. This can prevent the 1 st connecting line SL1 and the 2 nd connecting line SL2 made of aluminum from being damaged by the irradiation of the laser beam.

Fig. 4 is a partially enlarged sectional view of a display device according to an embodiment of the present invention.

Referring to fig. 1 and 4, the display device is the same as the display device of fig. 1 except for a point that a 1 st gate conductive layer is formed of a 1 st main conductive layer and a 1 st capping layer and a 2 nd gate conductive layer is formed of a 2 nd main conductive layer and a 2 nd capping layer. And therefore, duplicate explanation is omitted.

The 1 b-th gate conductive pattern GAT1b may include a 1 st main conductive layer M1 and a 1 st capping layer C1 disposed on the 1 st main conductive layer M1. The 1 st main conductive layer M1 may be formed of a single layer of aluminum or aluminum alloy, and the 1 st capping layer C1 may include titanium (Ti) and haveThe following thicknesses.

The 2 a-th gate conductive pattern GAT2a may include a 2 nd main conductive layer M2 and a 2 nd capping layer C2 disposed on the 2 nd main conductive layer M2. The 2 nd main conductive layer M2 may be formed of a single layer of aluminum or aluminum alloy, and the 2 nd capping layer C2 may include titanium (Ti) and haveThe following thicknesses.

Fig. 5A to 5F are cross-sectional views for explaining a method of manufacturing the display device of fig. 3.

Referring to fig. 5A, a buffer layer 110 may be formed on a base substrate 100. An active layer may be formed on the buffer layer 110. The active layer may include a 1 st active pattern ACTa and a 2 nd active pattern ACTb. The 1 st insulating layer 120 may be formed on the buffer layer 110 configured with the active layer.

A 1 st gate conductive layer may be formed on the 1 st insulating layer 120. The 1 st gate conductive layer may include a 1 st gate pattern GAT1a and a 1 st gate pattern GAT1b separated from the 1 st gate pattern GAT1 a. The 1 st gate conductive layer may further include the 1 st connection wiring SL 1.

Then, impurities may be doped into a portion of the active layer to form source and drain regions. Then, for dopant activation (activation) of the active layer, heat treatment is performed, whereby the active layer can be activated (activation) (rapid thermal annealing: RTA).

A 2 nd gate conductive layer may be formed on the 1 st insulating layer 120 provided with the 1 st gate conductive layer. The 2 nd gate conductive layer may include a 2a nd gate pattern GAT2a and a 2b nd gate pattern GAT2b (not shown in fig. 5A) separated from the 2a nd gate pattern GAT2 a. The 2 nd gate conductive layer may further include the 2 nd connecting wiring SL 2.

The 3 rd insulating layer 140 may be formed on the 2 nd insulating layer 130 provided with the 2 nd gate conductive layer.

Referring to fig. 5B, a 1 st contact hole CNT1 may be formed, and a 1 st contact hole CNT1 penetrates the 3 rd insulating layer 140, the 2 nd insulating layer 130, and the 1 st insulating layer 120 to expose the 1 st active pattern ACTa.

Here, in order to improve the electrical connection through the 1 st contact hole CNT1, the upper surface of the 1 st active pattern ACTa exposed through the 1 st contact hole CNT1 may be cleaned. For example, the wet cleaning process may be performed using a BOE (Buffered Oxide etch) cleaning solution having an etching force with respect to the metal. A cleaning process may be performed using the BOE solution to remove the residue under the 1 st contact hole CNT1 and the exposed oxide film of the 1 st active pattern ACTa.

At this time, since the 1 st gate conductive layer and the 2 nd gate conductive layer are entirely covered with the 2 nd insulating layer 130 and the 3 rd insulating layer 140 during the formation of the 1 st contact hole CNT1, there is no concern that the 1 st gate conductive layer and the 2 nd gate conductive layer are etched by the cleaning solution. That is, even if the 1 st gate conductive layer and the 2 nd gate conductive layer are formed of a material such as aluminum which is easily affected by the BOE (Buffered Oxide etch) cleaning solution, it is possible to prevent the occurrence of damage in the process.

Referring to fig. 5C, a 3 rd gate conductive layer may be formed on the 3 rd insulating layer 140 provided with the 1 st contact hole CNT 1. The 3 rd gate conductive layer may include a 3a th gate pattern GAT3a and a 3b th gate pattern GAT3b (not shown in fig. 5C) separated from the 3a th gate pattern GAT3 a. The 3 rd gate conductive layer may further include the shield electrode. The shielding electrodes may include a 1 st shielding electrode SE1 and a 2 nd shielding electrode SE 2.

Referring to fig. 5D, a 4 th insulating layer 150 may be formed on the 3 rd insulating layer 140 provided with the 3 rd gate conductive layer. It is possible to form: a 2 nd contact hole CNT2 penetrating the 4 th insulating layer 150; a 3 rd contact hole CNT3 penetrating the 4 th insulating layer 150 and the 3 rd insulating layer 140; a 4 th contact hole CNT4 passing through the 4 th insulating layer 150, the 3 rd insulating layer 140, and the 2 nd insulating layer 130.

The 2 nd contact hole CNT2 to the 4 th contact hole CNT4 expose the 3 rd gate conductive layer, the 2 nd gate conductive layer, and the 1 st gate conductive layer, but do not expose the active layer, and thus the 2 nd contact hole CNT2 to the 4 th contact hole CNT4 may be sufficiently cleaned with a cleaning solution having no etching force with respect to metal. For example, even if DI water washing is used, washing can be sufficiently performed. Thus, the 1 st gate conductive layer and the 2 nd gate conductive layer formed of aluminum or the like can be prevented from being damaged.

According to another embodiment, the 1 st gate conductive layer and the 2 nd gate conductive layer may include a capping layer including titanium or the like on a main conductive layer formed of aluminum or the like, and in this case, the capping layer may have a thin thickness as long as it functions as an etching stopper when the 2 nd contact holes CNT2 to the 4 th contact holes CNT4 are formed.

Referring to fig. 5E, a source-drain conductive layer may be formed on the 4 th insulating layer 150. The source and drain conductive layers may include a 1 st SD pattern SDa, a 2 nd SD pattern SDb, and a 3 rd SD pattern SDc.

The via insulating layer 160 may be formed on the source and drain conductive layer. The 1 st electrode 181 may be formed on the via insulating layer 160. A pixel defining film PDL may be formed on the via hole insulating layer 160 provided with the 1 st electrode 181. A light emitting layer 182 may be formed on the 1 st electrode 181 exposed through the opening of the pixel defining film PDL. The 2 nd electrode 183 may be formed on the pixel defining film PDL and the light emitting layer 182.

Referring to fig. 5F, the sealing member CS may be formed on the sealing substrate 200. After the sealing member CS is bonded to the base substrate 100, a LASER (LASER) may be irradiated to the sealing member CS to cure the sealing member CS. Thereby, the display region in which the light emitting structure 180 is arranged can be sealed.

At this time, the laser beam is irradiated to the sealing member CS through the sealing substrate 200, so that the shielding electrode including molybdenum or the like can block the laser beam from being irradiated to the 1 st connecting line SL1 and the 2 nd connecting line SL 2. Thus, the problem that the 1 st connecting line SL1 and the 2 nd connecting line SL2 made of aluminum or the like are damaged by the irradiation of the laser beam can be prevented.

Thereby, the display device can be manufactured.

Fig. 6 is a block diagram showing an electronic apparatus according to an embodiment of the present invention, fig. 7A is a diagram showing an example of implementing the electronic apparatus of fig. 6 by a television, and fig. 7B is a diagram showing an example of implementing the electronic apparatus of fig. 6 by a smartphone.

Referring to fig. 6 to 7B, the electronic device 500 may include a processor 510, a storage (memory) device 520, a storage (storage) device 530, an input-output device 540, a power supply device 550, and a display device 560. At this time, the display device 560 may correspond to the display device of fig. 1. The electronic device 500 may further include a plurality of ports (ports) that communicate with video cards, sound cards, memory cards (memory cards), USB devices, etc., or may communicate with other systems. In one embodiment, as shown in fig. 7A, the electronic device 500 may be implemented by a television. In other embodiments, as shown in fig. 7B, the electronic device 500 may be implemented by a smartphone. These are exemplary and the electronic device 500 is not limited thereto. For example, the electronic device 500 may be implemented by a portable phone, a video phone, a smart tablet (smart pad), a smart watch (smart watch), a tablet (tablet) PC, a vehicle navigation device, a computer monitor, a notebook computer, a Head Mounted Display (HMD), or the like.

The processor 510 may perform specific calculations or tasks (tasks). According to an embodiment, the Processor 510 may be a micro Processor (microprocessor), a Central Processing Unit (CPU), an Application Processor (AP), or the like. The processor 510 may be connected to other components through an address bus (address bus), a control bus (control bus), a data bus (data bus), and the like. According to an embodiment, the processor 510 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. The storage device 520 may store data required by the electronic device 500 when operating. For example, the storage device 520 may include: nonvolatile Memory devices such as Erasable Programmable Read-Only Memory (EPROM) devices, Electrically Erasable Programmable Read-Only Memory (EEPROM) devices, flash Memory devices (flash Memory devices), phase change Random Access Memory (PRAM) devices, Random Access Memory (RRAM) devices, Nano Floating Gate Memory (NFGM) devices, Polymer Random Access Memory (cell) devices, Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (ram) devices, and the like; and/or volatile Memory devices such as Dynamic Random Access Memory (DRAM) devices, Static Random Access Memory (SRAM) devices, mobile DRAM devices, and the like. The storage device 530 may include a Solid State Drive (SSD), a Hard Disk Drive (HDD), a CD-ROM, and the like. The input and output device 540 may include an input unit such as a keyboard, a Keypad (Keypad), a touch pad, a touch screen, a mouse, etc., and an output unit such as a speaker, a printer, etc. The power supply unit 550 may supply power required for the operation of the electronic device 500.

The display device 560 may be connected to other components via the bus or other communication link. According to an embodiment, the display device 560 may also be included in the input-output device 540. As described above, the display device 560 can improve display quality by reducing wiring resistance, and can prevent problems that may occur in the manufacturing process. However, since the above description has already been given, a repetitive description thereof will be omitted.

The present invention can be applied to an organic light emitting display device and various electronic apparatuses including the organic light emitting display device. For example, the present invention can be applied to a portable phone, a smart phone, a video phone, a smart tablet, a smart watch, a tablet PC, a navigation device for a vehicle, a television, a computer display, a notebook computer, a head-mounted display, and the like.

Although the present invention has been described with reference to the exemplary embodiments, it will be understood by those skilled in the art that modifications and variations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the appended claims.