阅读说明：本技术 显示装置 (Display device ) 是由 庐明勋 于 2020-02-14 设计创作，主要内容包括：本公开涉及一种显示装置,所述显示装置包括：显示基底,包括显示区域和设置在所述显示区域的外围的焊盘区域；和显示面板,包括设置在所述显示基底的所述焊盘区域中的至少一个布线焊盘,其中,所述布线焊盘包括：主焊盘部分,在第一方向上延伸；第一突出焊盘部分,从所述主焊盘部分的在与所述第一方向相交的第二方向上的第一侧突出；以及第二突出焊盘部分,从所述主焊盘部分的在所述第二方向上的第二侧突出,并且所述第一突出焊盘部分设置为比所述第二突出焊盘部分更靠近所述显示区域。(The present disclosure relates to a display device, including: a display substrate including a display area and a pad area disposed at a periphery of the display area; and a display panel including at least one routing pad disposed in the pad region of the display substrate, wherein the routing pad includes: a main pad portion extending in a first direction; a first protruding pad part protruding from a first side of the main pad part in a second direction intersecting the first direction; and a second protruding pad part protruding from a second side of the main pad part in the second direction, and the first protruding pad part is disposed closer to the display area than the second protruding pad part.)

1. A display device, wherein the display device comprises:

a display substrate including a display area and a pad area disposed at a periphery of the display area; and

a display panel including a routing pad disposed in the pad region of the display substrate, the routing pad including:

a main pad portion extending in a first direction;

a first protruding pad part protruding from a first side of the main pad part in a second direction intersecting the first direction; and

a second protruding pad part protruding from a second side of the main pad part in the second direction,

wherein the first protruding pad portion is disposed closer to the display area than the second protruding pad portion.

2. The display device according to claim 1,

the first direction is a direction from the display region toward an end of the pad region where the wiring pad is provided, and

the second side of the main pad section in the second direction is opposite to the first side of the main pad section in the second direction.

3. The display device according to claim 2, wherein the wiring pad further comprises a third protruding pad portion protruding from the first side of the main pad portion in the second direction and a fourth protruding pad portion protruding from the second side of the main pad portion in the second direction.

4. The display device according to claim 3, wherein the third protruding pad portion is disposed between the second protruding pad portion and the fourth protruding pad portion and is disposed closer to the display area than the fourth protruding pad portion.

5. The display device according to claim 3,

the second protruding pad portion is disposed between the third protruding pad portion and the fourth protruding pad portion, and

the third protruding pad portion is disposed closer to the display area than the fourth protruding pad portion.

6. The display device according to claim 2,

the wiring pad further includes a third protruding pad part protruding from the second side of the main pad part in the second direction, and

the area of the first protruding pad portion is the same as the area of the second protruding pad portion and the area of the third protruding pad portion.

7. The display device according to claim 2, wherein the main pad part includes a first sub-main pad part disposed at a second side of the first protruding pad part in the second direction and a second sub-main pad part disposed at a first side of the second protruding pad part in the second direction and spaced apart from the first sub-main pad part in the first direction.

8. The display device according to claim 2, wherein the first protruding pad portion and the second protruding pad portion have the same area and the same shape as each other.

9. The display device according to claim 2, wherein the display device further comprises:

a printed circuit board attached on the pad region of the display substrate and including a lead-out line connected to the wiring pad.

10. The display device according to claim 9, wherein the lead-out line overlaps the main pad portion of the wiring pad in a thickness direction, and at least partially overlaps at least one of the first protruding pad portion and the second protruding pad portion in the thickness direction.

11. The display device according to claim 9, wherein the lead-out line is directly connected to the wiring pad.

12. The display device according to claim 11, wherein the lead-out line is ultrasonically bonded to the wiring pad.

13. The display device according to claim 2,

the wiring pad overlaps and is electrically connected to a signal line passing through the display region in a thickness direction, and

the signal line is a gate signal line.

14. The display device according to claim 13, wherein the display device further comprises:

a pad insulating film disposed between the signal line and the wiring pad of the pad region and having a plurality of contact holes defined therein that at least partially expose the signal line,

wherein the wiring pad is electrically connected to the signal line through the plurality of contact holes.

15. The display device according to claim 2, wherein a plurality of wiring pads are arranged along the first direction and include a power wiring pad electrically connected to a power voltage line in the display region through a signal line and a data wiring pad electrically connected to a data line in the display region through the signal line.

16. The display device according to claim 15, wherein the display device further comprises:

a panel alignment mark disposed on a first side of the array of the plurality of routing pads in the first direction and having an alignment hole defined therein.

17. The display device according to claim 16, wherein the display device further comprises:

a printed circuit board including a circuit alignment mark ultrasonically bonded to the panel alignment mark and having a circuit alignment hole defined therein.

18. A display device, wherein the display device includes a display area and a pad area disposed at a periphery of the display area, the display area including a thin film transistor, the display device comprising:

a substrate;

a first conductive layer disposed on the substrate, the first conductive layer including a gate electrode of the thin film transistor disposed in the display region and a gate signal line disposed in the pad region;

a first insulating layer disposed on the first conductive layer;

a second conductive layer disposed on the first insulating layer, the second conductive layer including source and drain electrodes of the thin film transistor and a plurality of wiring pads disposed in the pad region;

a second insulating layer disposed on the second conductive layer; and

a third conductive layer disposed on the second insulating layer,

wherein the content of the first and second substances,

the plurality of routing pads overlap with the gate signal line in a thickness direction and are electrically connected to the gate signal line, each of the plurality of routing pads including:

a main pad portion extending in a first direction;

a first protruding pad part protruding from a first side of the main pad part in a second direction intersecting the first direction; and

a second protruding pad part protruding from a second side of the main pad part in the second direction, an

The first protruding pad portion is disposed closer to the display area than the second protruding pad portion.

19. The display device according to claim 18,

the first direction is a direction from the display region toward an end of the pad region where the plurality of wiring pads are provided, and

the second side of the main pad section in the second direction is opposite to the first side of the main pad section in the second direction.

20. The display device according to claim 19, wherein the display device further comprises:

a printed circuit board attached on the pad area and including lead-out lines connected to the plurality of wiring pads,

wherein the lead-out line overlaps with a main pad portion of the plurality of wiring pads in the thickness direction, and at least partially overlaps with at least one of first and second protruding pad portions of the plurality of wiring pads in the thickness direction.

Technical Field

Exemplary embodiments of the present disclosure relate to a display device.

Background

The display device visually displays the data. The display device includes a substrate divided into a display area and a non-display area. In the display region, a plurality of pixels are disposed on the substrate, and in the non-display region, a plurality of pads are disposed on the substrate. A chip on film ("COF"), on which a driving circuit and the like are mounted, is coupled to a pad transmitting a driving signal to the pixel.

The COF includes a plurality of wires bonded to pads, and the wires may be bonded to individual pads. Bonding of the wire may be performed using an ultrasonic bonding process.

Disclosure of Invention

However, when the degree of misalignment between the leads and the pads is different in the bonding process during the manufacture of each display device, the total bonding area between the leads and the pads may vary from one display device to another, and as a result, chip on film ("COF") bonding defects or resistance irregularities may occur in the bonding portion.

Exemplary embodiments of the present disclosure provide a display device including a uniform bonding area between a lead-out line and a panel pad.

However, the exemplary embodiments of the present disclosure are not limited to the exemplary embodiments set forth herein. The foregoing and other exemplary embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

An exemplary embodiment of the present disclosure provides a display device including: a display substrate including a display area and a pad area disposed at a periphery of the display area; and a display panel including a routing pad disposed in the pad region of the display substrate, wherein the routing pad includes: a main pad portion extending in a first direction; a first protruding pad part protruding from a first side of the main pad part in a second direction intersecting the first direction; and a second protruding pad part protruding from a second side of the main pad part in the second direction, and the first protruding pad part is disposed closer to the display area than the second protruding pad part.

In an exemplary embodiment, the first direction may be a direction from the display area toward an end of the pad area where the wiring pad is disposed, and the second side of the main pad part in the second direction may be opposite to the first side of the main pad part in the second direction.

In an exemplary embodiment, the wiring pad may further include a third protruding pad part protruding from the first side of the main pad part in the second direction and a fourth protruding pad part protruding from the second side of the main pad part in the second direction.

In an exemplary embodiment, the third protruding pad part may be disposed between the second protruding pad part and the fourth protruding pad part, and may be disposed closer to the display area than the fourth protruding pad part.

In an exemplary embodiment, the second protruding pad part may be disposed between the third protruding pad part and the fourth protruding pad part, and the third protruding pad part may be located closer to the display area than the fourth protruding pad part.

In an exemplary embodiment, the wiring pad may further include a third protruding pad part protruding from the second side of the main pad part in the second direction, and an area of the first protruding pad part is the same as an area of the second protruding pad part and an area of the third protruding pad part.

In an exemplary embodiment, the main pad part may include a first sub-main pad part disposed at a second side of the first protruding pad part in the second direction and a second sub-main pad part disposed at a first side of the second protruding pad part in the second direction and spaced apart from the first sub-main pad part in the first direction.

In an exemplary embodiment, the first protruding pad portion and the second protruding pad portion may have the same area and the same shape as each other.

In an exemplary embodiment, the display apparatus may further include: a printed circuit board attached on the pad region of the display substrate and including a lead-out line connected to the wiring pad.

In an exemplary embodiment, the lead-out line may overlap the main pad portion of the wiring pad in a thickness direction and at least partially overlap at least one of the first and second protruding pad portions in the thickness direction.

In an exemplary embodiment, the outlet may be directly connected to the routing pad.

In an exemplary embodiment, the lead-out wire may be ultrasonically bonded to the wiring pad.

In an exemplary embodiment, the routing pad may overlap a signal line passing through the display region in a thickness direction and may be electrically connected to the signal line, and the signal line is a gate signal line.

In an exemplary embodiment, the display apparatus may further include: a pad insulating film disposed between the signal line and the wiring pad of the pad region and having a plurality of contact holes defined therein that at least partially expose the signal line, wherein the wiring pad is electrically connected to the signal line through the plurality of contact holes.

In an exemplary embodiment, the plurality of routing pads may be arranged along the first direction and include a power routing pad electrically connected to a power voltage line in the display area through a signal line and a data routing pad electrically connected to a data line in the display area through the signal line.

In an exemplary embodiment, the display apparatus may further include: a panel alignment mark disposed on a first side of the array of the plurality of routing pads in the first direction and having an alignment hole defined therein.

In an exemplary embodiment, the printed circuit board may include a circuit alignment mark ultrasonically bonded to the panel alignment mark and including a circuit alignment hole therein.

An exemplary embodiment of the present disclosure provides a display device including a display area and a pad area disposed at a periphery of the display area, the display area including a thin film transistor, the display device including: a substrate; a first conductive layer disposed on the substrate; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer, wherein the first conductive layer includes a gate electrode of the thin film transistor disposed in the display region and a gate signal line disposed in the pad region, the second conductive layer includes source and drain electrodes of the thin film transistor and a plurality of routing pads disposed in the pad region, the plurality of routing pads overlap with the gate signal line in a thickness direction and are electrically connected to the gate signal line, each of the plurality of routing pads includes: a main pad portion extending in a first direction; a first protruding pad part protruding from a first side of the main pad part in a second direction intersecting the first direction; and a second protruding pad part protruding from a second side of the main pad part in the second direction, and the first protruding pad part is disposed closer to the display area than the second protruding pad part.

In an exemplary embodiment, the first direction may be a direction from the display area toward an end of the pad area where the plurality of wiring pads are disposed, and the second side of the main pad part in the second direction may be opposite to the first side of the main pad part in the second direction.

In an exemplary embodiment, the display apparatus may further include: a printed circuit board attached on the pad area of the display substrate and including a lead-out line connected to the plurality of routing pads, wherein the lead-out line overlaps a main pad portion of the plurality of routing pads in the thickness direction and at least partially overlaps at least one of first and second protruding pad portions of the plurality of routing pads in the thickness direction.

Other features and embodiments will be apparent from the following detailed description, the accompanying drawings, and the claims.

Drawings

The above and other exemplary embodiments and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

fig. 1 is a plan view of an exemplary embodiment of a display device according to the present disclosure;

fig. 2A is a sectional view of the display device of fig. 1, and fig. 2B and 2C are enlarged views of a portion of the display device in fig. 2A;

fig. 3 is a plan view illustrating a pad area of the display device of fig. 1;

fig. 4 is a partial plan view illustrating a printed circuit board ("PCB") of the display device of fig. 1;

fig. 5 is a partial plan view illustrating a case where the pad region of fig. 3 and the PCB of fig. 4 are attached to each other and properly aligned with each other without misalignment therebetween (i.e., α ═ 0% (where α denotes an alignment error);

fig. 6 is an enlarged plan view showing a region a of fig. 5;

FIG. 7 is a sectional view taken along line VII-VII' of FIG. 6;

FIG. 8 is a cross-sectional view taken along line VIII-VIII' of FIG. 6;

fig. 9 is a plan view illustrating a case where the pad area of fig. 3 and the PCB of fig. 4 are attached to each other but are misaligned (i.e., α <0) from each other;

fig. 10 is an enlarged plan view showing a region B of fig. 9;

FIG. 11 is a sectional view taken along line XI-XI' of FIG. 10;

FIG. 12 is a sectional view taken along line XII-XII' of FIG. 10;

fig. 13 is a plan view illustrating a case where the pad area of fig. 3 and the PCB of fig. 4 are attached to each other but are misaligned with each other (i.e., α > 0);

fig. 14 is an enlarged plan view showing a region C of fig. 13;

FIG. 15 is a sectional view taken along line XV-XV' of FIG. 14;

fig. 16A to 16C are enlarged plan views illustrating an exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 17 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 18 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 19 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 20 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 21 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 22 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure;

fig. 23 is a partial plan view illustrating another exemplary embodiment of a PCB of a display device according to the present disclosure;

fig. 24 is a plan view of another exemplary embodiment of a display device according to the present disclosure; and

fig. 25 is a cross-sectional view of another exemplary embodiment of a display device according to the present disclosure.

Detailed Description

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "portion" discussed below could be termed a second element, component, region, layer or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, including at least one of "… …", unless the context clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," or "including" and/or "having," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device is turned over in one of the figures, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below … …" or "below … …" can encompass both an orientation of above and below.

Spatially relative terms such as "below … …," "below … …," "below," "above … …," and "above" may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. In exemplary embodiments, when the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "about" or "approximately" includes the stated value, and is intended to be within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, given the measurement in question and the error associated with measurement of the specified quantity (i.e., the limitations of the measurement system). In exemplary embodiments, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated values.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. In this way, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. In exemplary embodiments, the regions shown or described as flat may generally have rough and/or non-linear features. In addition, the sharp corners shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Fig. 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure, fig. 2A is a cross-sectional view of the display device of fig. 1, fig. 3 is a plan view illustrating a pad region of the display device of fig. 1, and fig. 4 is a partial plan view illustrating a printed circuit board ("PCB") of the display device of fig. 1. Specifically, fig. 2A is a cross-sectional view illustrating the pixel region and the panel pad region P _ PA of fig. 1.

The display device 1, which is a device displaying still images or moving images, may be used in a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook computer, an electronic book, a portable multimedia player ("PMP"), a navigation device, or an ultra mobile PC ("UMPC"), and the display device 1 may also be used in various other products such as a television ("TV"), a notebook computer, a monitor, a billboard, or an internet of things ("IoT") device.

Referring to fig. 1 to 4, the display device 1 may include a display panel 100 displaying an image, a PCB300 connected to the display panel 100, and a main circuit board 500 connected to the PCB 300.

In an exemplary embodiment, an organic light emitting diode ("OLED") display panel may be used as the display panel 100, for example. Hereinafter, the display panel 100 is described as an OLED display panel, but the present disclosure is not limited thereto. In alternative exemplary embodiments, various other display panels, such as a liquid crystal display ("LCD") panel, a quantum dot OLED ("QD-OLED") display panel, a quantum dot LCD ("QD-LCD"), a quantum dot nano light emitting diode ("QNED") display panel, or a micro LED ("mLED") display panel, may be used as the display panel 100.

The display panel 100 includes a display area DA including a plurality of pixel areas and a non-display area NA disposed at the periphery of the display area DA. In a plan view, the display area DA may have a rectangular shape having right-angled corners or having rounded corners. The display area DA may have a short side and a long side. The short side of the display area DA may extend in the first direction DR 1. The long side of the display area DA may extend in the second direction DR 2. The planar shape of the display area DA is not particularly limited, and the display area DA may have various shapes other than a rectangular shape, such as a circular shape, an elliptical shape, and the like. The non-display area NA may be disposed adjacent to both short sides and both long sides of the display area DA, in which case the non-display area NA may surround all sides of the display area DA and may form an edge of the display area DA. However, the present disclosure is not limited thereto. In alternative exemplary embodiments, the non-display area NA may be disposed adjacent to only two short sides or two long sides of the display area DA.

The non-display area NA of the display panel 100 may include a panel pad area P _ PA. The panel pad area P _ PA may be disposed adjacent to one of the short sides of the display area DA, but the present disclosure is not limited thereto. In alternative exemplary embodiments, the panel pad area P _ PA may be disposed adjacent to two short sides and/or two long sides of the display area DA.

The PCB300 may include a printing substrate film 310 and a driver integrated circuit ("IC") 390 disposed on the printing substrate film 310. The printing substrate film 310 may include an insulating material.

The PCB300 may include a circuit region CA, which may include a first circuit region CA1 attached to the panel pad region P _ PA of the display panel 100, a second circuit region CA2 disposed at a first side (e.g., a lower side) of the first circuit region CA1 in the second direction DR2, and a third circuit region CA3 disposed at a first side of the second circuit region CA2 in the second direction DR2 and to which the main circuit board 500 is attached. The driver IC390 may be disposed on a first surface of the second circuit area CA2 of the PCB 300. In an exemplary embodiment, the driver IC390 may be, for example, a data driver IC, and may be implemented in the form of, for example, a chip on film ("COF").

The main circuit board 500 may include a circuit pad area C _ PA attached to the third circuit area CA3 of the PCB 300. In the circuit pad region C _ PA of the main circuit board 500, a plurality of circuit pads may be disposed, and the plurality of circuit pads may be connected to the lead-out lines disposed in the third circuit region CA3 of the PCB 300.

Referring to fig. 2A, the display device 1 may further include a panel bottom sheet 200 disposed at the bottom of the display panel 100. The panel bottom sheet 200 may be attached to the rear surface of the display panel 100. The panel bottom sheet 200 may comprise one or more functional layers. The functional layer may be a layer that performs a heat dissipation function, an electromagnetic wave shielding function, a grounding function, a buffering function, a strength enhancing function, a supporting function, and/or a digitizing function. The functional layer may be a sheet layer comprising a sheet, a film layer comprising a film, a film layer, a coating layer, a panel or a plate. The functional layer may have a single layer structure or a stack of a plurality of thin films or coating layers. The functional layer may be, for example, a support member, a heat dissipation layer, an electromagnetic wave shielding layer, an impact absorption layer, or a digitizer.

As shown in fig. 2A, the PCB300 may be bent in a downward direction in the third direction DR 3. A portion of the PCB300 and the main circuit board 500 may be disposed under the panel bottom sheet 200. The bottom surface of the panel bottom sheet 200 may be bonded to the main circuit board 500 via an adhesive layer, but the present disclosure is not limited thereto.

The display panel 100 may include a display substrate 101, a plurality of conductive layers, a plurality of insulating layers for insulating the conductive layers, and an organic layer EL.

The display substrate 101 may be disposed in and across the display area DA and the non-display area NA. The display substrate 101 may support various elements disposed thereon. The display substrate 101 may be a rigid substrate including a rigid material such as soft glass or quartz, but the present disclosure is not limited thereto. In alternative exemplary embodiments, the display substrate 101 may be a flexible substrate including a flexible material such as polyimide ("PI").

The buffer layer 102 may be disposed on the display substrate 101. The buffer layer 102 may prevent external moisture and oxygen from penetrating through the display substrate 101. In an exemplary embodiment, for example, the buffer layer 102 may include silicon nitride (SiN)_x) Film, silicon oxide (SiO)₂) Film and silicon oxynitride (SiO)_xN_y) At least one of the films.

The semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 may form a channel of a thin film transistor ("TFT"). When necessary, the semiconductor layer 105 may be disposed in each pixel in the display area DA, even in the non-display area NA. The semiconductor layer 105 may include source/drain regions and an active region. In an exemplary embodiment, the semiconductor layer 105 may include, for example, polysilicon.

The first insulating layer 111 may be disposed on the semiconductor layer 105. The first insulating layer 111 may be disposed on the entire surface of the display substrate 101. The first insulating layer 111 may be a gate insulating film having a gate insulating function. In an exemplary embodiment, the first insulating layer 111 may include a silicon compound, a metal oxide, or the like. In an exemplary embodiment, for example, the first insulating layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like, and these materials may be used alone or in combination with each other.

The first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include a gate electrode GE of the TFT, a first electrode CE1 of a sustain capacitor (sustain capacitor) Cst, and a gate signal line GSL. In an exemplary embodiment, for example, the first conductive layer 120 may include at least one metal including at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may be a single film or a stack of a plurality of films.

Second insulating layers 112a and 112b may be disposed on first conductive layer 120. The second insulating layers 112a and 112b may insulate the first conductive layer 120 from the second conductive layer 130. The second insulating layers 112a and 112b may include at least one of the foregoing exemplary materials of the first insulating layer 111. In the panel pad region P _ PA, a plurality of contact holes CNT (refer to fig. 6) partially exposing the gate signal lines GSL may be defined in the second insulating layer 112 b.

The second conductive layer 130 may be disposed on the second insulating layers 112a and 112 b. The second conductive layer 130 may include a second electrode CE2 of the sustain capacitor Cst. The second conductive layer 130 may include at least one of the foregoing exemplary materials of the first conductive material. The first electrode CE1 and the second electrode CE2 of the sustain capacitor Cst may form a capacitor through the second insulating layers 112a and 112 b.

The third insulating layer 113 may be disposed on the second conductive layer 130. The third insulating layer 113 may include at least one of the foregoing exemplary materials of the first insulating layer 111. In some exemplary embodiments, the third insulating layer 113 may include an organic insulating material. The organic insulating material may include at least one of exemplary materials of a first through layer (VIA) VIA1, which will be described later.

The third conductive layer 140 may be disposed on the third insulating layer 113. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high potential voltage electrode eldde, and a wiring PAD. In an exemplary embodiment, for example, the third conductive layer 140 may include at least one of Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu. The third conductive layer 140 may be a single layer film, but the present disclosure is not limited thereto. In an alternative exemplary embodiment, the third conductive layer 140 may be a stack of a plurality of films. In an exemplary embodiment, the third conductive layer 140 may have a stack structure of Ti/Al/Ti, Mo/Al/Mo, Mo/AlGe/Mo, or Ti/Cu, for example.

The wiring PAD of the third conductive layer 140 may overlap the gate signal line GSL of the first conductive layer 120 in the thickness direction (the third direction DR3) and may be electrically connected to the gate signal line GSL through the contact hole CNT of the second insulating layer 112 b. The wiring PAD may include surface unevenness. The protruding portion of the wiring PAD may be a portion of the wiring PAD overlapping with the second insulating layer 112b in the thickness direction, and the recessed portion of the wiring PAD may be a portion of the wiring PAD not overlapping with the second insulating layer 112b in the thickness direction.

The first through layer VIA1 may be disposed on the third conductive layer 140. The first through layer VIA1 may comprise an organic insulating material. In an exemplary embodiment, for example, the organic insulating material may include at least one of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, and benzocyclobutene ("BCB").

The structure (e.g., the first through layer VIA1 and elements to be described later disposed on the first through layer VIA 1) above the third conductive layer 140 may not be disposed in the panel pad region P _ PA or may be removed from the panel pad region P _ PA. Accordingly, the top surface of the wiring PAD may be exposed in the panel PAD area P _ PA.

The PCB300 may further include lead lines LE disposed on the first surface of the first circuit region CA1 and circuit lead lines C _ LE disposed on the first surface of the third circuit region CA 3. The lead line LE is connected to the wiring PAD. The lead line LE may be directly connected to the exposed top surface of the wiring PAD. In an exemplary embodiment, the lead lines LE may be bonded to the wiring PADs PAD through an ultrasonic bonding process, for example.

The ultrasonic bonding process may be performed by ultrasonic apparatus 700. The ultrasonic apparatus 700 may include a vibration generator 710, a vibrator 720 connected to the vibration generator 710, a booster 730 amplifying an amplitude of vibration of the vibrator 720, and a vibration transmitter 740 connected to the vibrator 720.

The vibration generator 710 may convert the electrical energy into vibration energy. The vibrator 720 may vibrate using vibration energy obtained by the vibration generator 710. The vibrator 720 may vibrate in a predetermined vibration direction and a predetermined amplitude. The amplitude of the vibration of the vibrator 720 may be amplified in a predetermined vibration direction by a booster 730 connected to the vibrator 720. The vibration transmitter 740 may transmit the vibration of the vibrator 720 to the target element to be bonded. The supporting member 750 may fix the top and bottom surfaces of the vibrator 720, and thus may prevent the vibrator 720 and the vibration transmitter 740 from vertically fluctuating due to the vibration of the vibrator 720.

The ultrasonic device 700 may be in contact with the second surface of the PCB300 and may maintain a predetermined pressurization state in a downward direction, so that the vibration transmitter 740 may efficiently transmit the vibration of the vibrator 720 to the PCB 300. As shown in fig. 2C, the vibration transmitter 740 of the ultrasonic device 700 may overlap the entire PCB300 disposed under the ultrasonic device 700, and may perform ultrasonic bonding.

The ultrasonic device 700 may vibrate in a predetermined vibration direction to vibrate the lead line LE in the predetermined vibration direction. In this case, the wiring PAD may also slightly vibrate in the same direction as the lead-out line LE due to the vibration applied thereto through the lead-out line LE, but the amplitude of the vibration of the wiring PAD may be negligible. Therefore, the amplitude of the vibration transmitter 740 in the predetermined vibration direction may be substantially the same as the distance that the lead line LE moves over the wiring PAD. The predetermined vibration direction may be the second direction DR 2. That is, the predetermined vibration direction may be a direction in which the wiring PAD and the lead line LE extend.

If the lead line LE vibrates above the wiring PAD with ultrasonic waves, a predetermined frictional force is generated at an interface between the wiring PAD and the lead line LE, and thus, frictional heat is generated. When the frictional heat is sufficient to melt the materials of the wiring PAD and the lead line LE, the melted PAD region PADb of the wiring PAD adjacent to the lead line LE and the melted lead region LEb of the lead line LE adjacent to the PAD region PAD may be melted. That is, the wiring PAD may include the unmelted PAD area PADa and the melted PAD area PADb, and the leader line LE may include the unmelted lead area LEa and the melted lead area LEb.

The unmelted PAD area PADa may be an area including only the material of the wiring PAD. Unmelted lead region LEa may be a region that includes only the material of lead-out line LE.

The melted PAD region PADb may be a region in which the material of the lead-out line LE is diffused to be mixed with the material of the wiring PAD, and the melted lead region LEb may be a region in which the material of the wiring PAD is diffused to be mixed with the material of the wiring PAD. In an exemplary embodiment, for example, in the case where the lead lines LE include Ag, Au, or Cu and the wiring PAD includes Ti/Al/Ti, the melted PAD region PADb may be a region in which Ti and/or Al from the wiring PAD and Ag, Au, or Cu from the lead lines LE are mixed together, and the melted lead region LEb may be a region in which Ag, Au, or Cu from the lead lines LE and Ti and/or Al from the wiring PAD are mixed together.

In the melted PAD region PADb and the melted lead region LEb, the wiring PAD and the lead line LE are solidified and then bonded together. The interface between the wiring PAD and the lead line LE (i.e., the interface between the melted PAD region PADb and the melted lead region LEb) may have a non-flat shape.

In a region where the wiring PAD and the PCB300 are not surface-bonded together between the wiring PAD and the PCB300, an underfill resin UFR may be provided, and the underfill resin UFR may facilitate bonding between the wiring PAD and the PCB 300. That is, the underfill resin UFR may bond the wiring PAD and the lead-out line LE together in a region other than the ultrasonic bonding region as shown in fig. 2B. A typical adhesive material may be used as the underfill resin UFR. In an exemplary embodiment, an organic resin may be used as the underfill resin UFR, for example.

The fourth conductive layer 150 may be disposed on the first through layer VIA 1. The fourth conductive layer 150 may include a data line DL, a connection electrode CNE, and a high potential voltage wiring elddl. The data line DL may be electrically connected to the source electrode SE of the TFT through a contact passing through the first through layer VIA 1. The connection electrode CNE may be electrically connected to the drain electrode DE of the TFT through a contact hole passing through the first through layer VIA 1. The high potential voltage wiring elddl may be electrically connected to the high potential voltage electrode eldde through a contact hole passing through the first through layer VIA 1. Fourth conductive layer 150 may include at least one of the foregoing exemplary materials of third conductive layer 140.

The second through layer VIA2 is disposed on the fourth conductive layer 150. The second through-layer VIA2 may include at least one of the foregoing example materials of the first through-layer VIA 1.

The anode electrode ANO is provided on the second through layer VIA 2. The anode electrode ANO may be electrically connected to the connection electrode CNE through a contact hole passing through the second through layer VIA 2.

A BANK layer BANK may be disposed on the anode electrode ANO. The BANK layer BANK may include an opening exposing the anode electrode ANO. The BANK layer BANK may include an organic insulating material or an inorganic insulating material. In an exemplary embodiment, for example, the BANK layer BANK may include at least one of photoresist, polyimide resin, acrylic resin, silicon compound, and polyacrylic resin.

The organic layer EL may be disposed on the top surface of the anode electrode ANO and in the opening of the BANK layer BANK. The cathode electrode CAT is disposed on the organic layer EL and the BANK layer BANK. The cathode electrode CAT may be a common electrode disposed in and across a plurality of pixel areas.

The thin film encapsulation layer 170 is disposed on the cathode electrode CAT. The thin film encapsulation layer 170 may cover the OLED. The thin film encapsulation layer 170 may be a layer in which inorganic films and organic films are alternately stacked. In an exemplary embodiment, for example, the thin film encapsulation layer 170 may include a first encapsulation inorganic film 171, an encapsulation organic film 172, and a second encapsulation inorganic film 173, which are sequentially stacked.

The structure and shape of the stack of the gate signal line GSL and the wiring PAD in the panel PAD area P _ PA may be changed.

In some exemplary embodiments, for example, the gate signal line GSL may include a plurality of patterns, and the wiring PAD disposed on the gate signal line GSL may have surface unevenness to reflect a height difference provided by the patterns of the gate signal line GSL.

In some exemplary embodiments, the auxiliary PAD of the second conductive layer 130 may be further disposed between the gate signal line GSL and the wiring PAD. In this case, the size of the auxiliary PAD may be smaller than that of the wiring PAD. The wiring PAD, the auxiliary PAD, and the gate signal line GSL may overlap each other in a thickness direction, and may be electrically connected to each other.

In addition, in some exemplary embodiments, the gate signal line GSL may be provided as the second conductive layer 130, and the wiring PAD may be provided as the fourth conductive layer 150.

Referring to fig. 3, a plurality of wiring PADs PAD may be provided, and the plurality of wiring PADs PAD may be arranged along the first direction DR 1.

The wiring PAD may include a plurality of power PADs PW _ PAD1 and PW _ PAD2, a plurality of data PADs D _ PAD1 and D _ PAD2, and a plurality of panel dummy PADs DU _ PAD. The power PADs PW _ PAD1 and PW _ PAD2 may be electrically connected through the gate signal line GSL and the high potential voltage wiring elddl and/or the low potential voltage wiring, and the data PADs D _ PAD1 and D _ PAD2 may be electrically connected through the data line DL and the gate signal line GSL. The panel dummy PAD DU _ PAD may be isolated from the signal lines passing through the display area DA.

An array of panel dummy PADs DU _ PAD may be disposed between the array of the first data PADs D _ PAD1 and the array of the second data PADs D _ PAD2, and an array of the first data PADs D _ PAD1 may be disposed between the array of the first power PADs PW _ PAD1 and the array of the dummy PADs DU _ PAD, and an array of the second data PADs D _ PAD2 may be disposed between the array of the second power PADs PW _ PAD2 and the array of the dummy PADs DU _ PAD.

Each of the wiring PADs PAD may protrude in two different directions. In an exemplary embodiment, each of the wiring PADs PAD may protrude at both sides thereof in the first direction DR 1. The shape of the wiring PAD, for example, will be described in detail later.

Panel alignment marks P _ ALM1 and P _ ALM2 may be disposed at both sides of the array of wiring PADs PAD. That is, the first panel alignment mark P _ ALM1 may be disposed on a first side of the array of the wiring PADs PAD in the first direction DR1, and the second panel alignment mark P _ ALM2 may be disposed on a second side of the array of the wiring PADs PAD in the first direction DR 1. The panel alignment marks P _ ALM1 and P _ ALM2 may be used as marks in the process of attaching the PCB 300.

The panel alignment marks P _ ALM1 and P _ ALM2 may have the same stack structure or a similar stack structure as the wiring PAD, but the present disclosure is not limited thereto. In alternative exemplary embodiments, the panel alignment marks P _ ALM1 and P _ ALM2 may be constituted by only the gate signal lines GSL or only the wiring PADs PAD. In addition, the panel alignment marks P _ ALM1 and P _ ALM2 may include a conductive layer different from the gate signal lines GSL and the wiring PADs PAD.

Alignment holes P _ ALH may be defined in the panel alignment marks P _ ALM1 and P _ ALM 2. In a plan view, the alignment hole P _ ALH may be completely surrounded by the panel alignment marks P _ ALM1 and P _ ALM 2. The planar shape of the alignment hole P _ ALH is not limited to the planar shape shown in fig. 3, but may be changed.

Referring to fig. 4, a plurality of lead lines LE may be provided in the first circuit area CA1 and may be arranged along the first direction DR 1. The lead lines LE may include a plurality of power lead lines PW _ LE1 and PW _ LE2, a plurality of data lead lines D _ LE1 and D _ LE2, and a plurality of dummy lead lines DU _ LE. The power pinouts PW _ LE1 and PW _ LE2 may electrically connect the driver IC390 and the power PADs PW _ PAD1 and PW _ PAD2, and the data pinouts D _ LE1 and D _ LE2 may electrically connect the driver IC390 and the data PADs D _ PAD1 and D _ PAD 2. The dummy lead DU _ LE may be electrically isolated from the driver IC 390.

The array of dummy leads DU _ LE may be disposed between the array of first data lead D _ LE1 and the array of second data lead D _ LE2, the array of first data lead D _ LE1 may be disposed between the array of first power lead PW _ LE1 and the array of dummy leads DU _ LE, and the array of second data lead D _ LE2 may be disposed between the array of second power lead PW _ LE2 and the array of dummy leads DU _ LE.

The lead line LE may include a metal material. In an exemplary embodiment, for example, the lead line LE may include at least one metal selected from Mo, Al, Pt, palladium (Pd), Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Ti, Ta, W, and Cu.

The line alignment marks L _ ALM1 and L _ ALM2 may be disposed at both sides of the array of lead lines LE. That is, second line alignment mark L _ ALM2 may be disposed on a first side of the array of pinouts LE in first direction DR1, and first line alignment mark L _ ALM1 may be disposed on a second side of the array of pinouts LE in first direction DR 1.

Alignment holes L _ ALH may be defined in the wire alignment marks L _ ALM1 and L _ ALM 2. In a plan view, the alignment hole L _ ALH may be completely surrounded by the wire alignment marks L _ ALM1 and L _ ALM 2. Fig. 4 illustrates that the alignment hole L _ ALH is vertically symmetrical to the panel alignment marks P _ ALM1 and P _ ALM2, but the present disclosure is not limited thereto.

The wiring PAD and the board alignment marks P _ ALM1 and P _ ALM2 may be surface-bonded to the lead line LE and the lead alignment marks L _ LM1 and L _ LM2, respectively, by ultrasonic bonding. The first circuit region CA1 of fig. 4 is turned by 180 degrees (°) and then attached to the panel pad region P _ PA of fig. 3 in the thickness direction. That is, the power PADs PW _ PAD1 and PW _ PAD2 may be ultrasonically bonded to the power leads PW _ LE1 and PW _ LE2, the data PADs D _ PAD1 and D _ PAD2 may be ultrasonically bonded to the data leads D _ LE1 and D _ LE2, the panel dummy PAD DU _ PAD may be ultrasonically bonded to the dummy lead DU _ LE, and the panel alignment marks P _ ALM1 and P _ ALM2 may be ultrasonically bonded to the lead alignment marks L _ LM1 and L _ LM 2. As already discussed above, holes P _ ALH or L _ ALM are defined in the panel alignment marks P _ ALM1 and P _ ALM2 and the wire alignment marks L _ ALM1 and L _ ALM 2. Accordingly, during ultrasonic bonding, the panel alignment marks P _ ALM1 and P _ ALM2 and the lead alignment marks L _ ALM1 and L _ ALM2 may increase the contact area therebetween, and thus may enhance the bonding force therebetween.

Hereinafter, an exemplary plan view and a sectional view of the display device 1 including the wiring PAD and the panel alignment marks P _ ALM1 and P _ ALM2 ultrasonically bonded to the lead line LE and the lead line alignment marks L _ LM1 and L _ LM2, respectively, will be described. Alignment errors may occur in the process of aligning the wiring PAD and the board alignment marks P _ ALM1 and P _ ALM2 with the lead line LE and the lead line alignment marks L _ LM1 and L _ LM2, respectively, to ultrasonically bond the wiring PAD and the board alignment marks P _ ALM1 and P _ ALM2 to the lead line LE and the lead line alignment marks L _ LM1 and L _ LM2, respectively.

Fig. 5 is a partial plan view illustrating a case where the pad region of fig. 3 and the PCB of fig. 4 are attached to each other and properly aligned with each other without misalignment therebetween (i.e., α is 0% (where α represents an alignment error)), fig. 6 is an enlarged plan view illustrating a region a of fig. 5, fig. 7 is a sectional view taken along a line VII-VII 'of fig. 6, and fig. 8 is a sectional view taken along a line VIII-VIII' of fig. 6.

Referring to fig. 5 to 8, as has been discussed above, each of the wiring PADs PAD protrudes in two different directions. Hereinafter, a planar shape and a sectional structure of the wiring PAD will be described taking one first power PAD PW _ PAD1 as an example, and the description of the subsequent first power PAD PW _ PAD1 may be directly applied to the other first power PADs PW _ PAD1, second power PAD PW _ PAD2, data PADs D _ PAD1 and D _ PAD2, and panel dummy PAD DU _ PAD.

The first power PAD PW _ PAD1 may include main PAD portions MR1 and MR2 overlapping the gate signal line GSL. The main pad portions MR1 and MR2 may extend along the second direction DR 2. The first main pad portion MR1 and the second main pad portion MR2 may be spaced apart from each other in the second direction DR2 and may overlap each other in the second direction DR2 in a plan view. The first main pad part MR1 may be located closer to the display area DA than the second main pad part MR 2. The main pad portions MR1 and MR2 may be electrically connected to the gate signal line GSL through the contact hole CNT of the second insulating layer 112 b. The arrangement and number of the contact holes CNT of the second insulating layer 112b may vary. The main pad portions MR1 and MR2 may have a rectangular shape in plan view.

The pad connection portion CR may be disposed between the first main pad portion MR1 and the second main pad portion MR2 to physically connect the first main pad portion MR1 and the second main pad portion MR 2.

The main PAD portions MR1 and MR2 and the PAD connection portion CR of the first power PAD PW _ PAD1 may have a width WPA1 in the first direction DR1 and a width WPA2 in the second direction DR2, and a sum of areas of the main PAD portions MR1 and MR2 and the PAD connection portion CR of the first power PAD PW _ PAD1 may be WPA1 × WPA 2.

The first protruding pad part PR1 is disposed at a first side of the first main pad part MR1 in the first direction DR1, and the second protruding pad part PR2 is disposed at a second side of the second main pad part MR2 in the first direction DR 1. The first protruding pad part PR1 may be located closer to the display area DA than the second protruding pad part PR 2. Fig. 6 shows that the protruding pad portions PR1 and PR2 do not overlap the gate signal line GSL in the thickness direction, but the present disclosure is not limited thereto. That is, the protruding pad portions PR1 and PR2 may overlap the gate signal line GSL in the thickness direction.

The pad connection portion CR may include a first edge disposed adjacent to the first protruding pad part PR1 and a second edge disposed adjacent to the second protruding pad part PR 2. The first edge and the second edge of the pad connection portion CR may each extend in the second direction DR 2. A first edge of the pad connection portion CR may be a boundary between the first main pad portion MR1 and the first protruding pad portion PR1, and a second edge of the pad connection portion CR may be a boundary between the second main pad portion MR2 and the second protruding pad portion PR 2. That is, the protruding pad portions PR1 and PR2 may be portions of the pad connection portion CR that extend in the first direction DR1 from first and second edges of the pad connection portion CR and may be physically connected to the main pad portions MR1 and MR2 through the first and second edges of the pad connection portion CR.

The first and second protruding pad portions PR1 and PR2 may have the same area in a plan view. In addition, the first and second protruding pad parts PR1 and PR2 may have the same shape in a plan view. The first and second protruding pad parts PR1 and PR2 may have a rectangular shape or a square shape in a plan view. In an exemplary embodiment, for example, the first protruding pad part PR1 may have a width WP11 in the first direction DR1 and a width WP12 in the second direction DR2, and the second protruding pad part PR2 may have a width WP21 in the first direction DR1 and a width WP22 in the second direction DR 2. The first and second protruding pad portions PR1 and PR2 may have the same width and the same area in a plan view. That is, the area of each of the protruding pad portions PR1 and PR2 may be WP11 × WP 12. In addition, the width of the protruding pad portions PR1 and PR2 in the first direction DR1 may be the same as the width of the main pad portions MR1 and MR2 in the first direction DR1, but the present disclosure is not limited thereto.

As shown in fig. 6, the first power lead PW _ LE1 may have a linear shape extending in the second direction DR 2. In this case, the width of the first power outlet PW _ LE1 in the first direction DR1 may be WL.

A first power lead PW _ LE1 is bonded to a first power PAD PW _ PAD 1. The first power lead out PW _ LE1 may be bonded to the first power PAD PW _ PAD1 with its lead center line LCL aligned with the alignment line AGL. The alignment line AGL is a center line of the first power PAD PW _ PAD1 in the first direction DR1, and the wire center line LCL may be a center line of the first power lead PW _ LE1 in the first direction DR 1.

As already discussed above, a misalignment with an alignment error α may occur in the process of aligning the first power lead PW _ LE1 with the first power PAD PW _ PAD 1. The alignment error α satisfies the following equation:

where L represents the alignment error shift and D represents the distance between alignment line AGL and lead centerline LCL.

When the first power lead PW _ LE1 is properly aligned with the first power PAD PW _ PAD1, the distance D and the alignment error displacement L are both zero. When the first power lead PW _ LE1 is misaligned as a result of moving towards its first side in the first direction DR1, L ═ D (where D > 0). When the first power lead PW _ LE1 is misaligned as a result of moving towards its second side in the first direction DR1, L ═ D (where D > 0).

Referring to fig. 5 to 8, the first power lead PW _ LE1 may completely overlap the main PAD portions MR1 and MR2 and the PAD connection portion CR of the first power PAD PW _ PAD1 in the thickness direction, and may partially overlap the protruding PAD portions PR1 and PR2 of the first power PAD PW _ PAD1 in the thickness direction. Referring to fig. 6, the width of the overlapping region of the first protruding pad part PR1 and the first power lead PW _ LE1 in the first direction DR1 and the width of the overlapping region of the second protruding pad part PR2 and the first power lead PW _ LE1 in the first direction DR1 may be WP111 and WP211, respectively, and the width of the overlapping region of the first protruding pad part PR1 and the first power lead PW _ LE1 in the second direction DR2 and the width of the overlapping region of the second protruding pad part PR2 and the first power lead PW _ LE1 in the second direction DR2 may be WP12 and WP22, respectively. When the first power lead PW _ LE1 is properly aligned with the first power PAD PW _ PAD1, the width WP111 and the width WP211 may be the same.

As shown in fig. 7 and 8, the first power lead PW _ LE1 may be in surface contact with a protruding portion of a surface of the first power PAD PW _ PAD1, and may be spaced apart from a recessed portion of the surface of the first power PAD PW _ PAD 1. In an alternative exemplary embodiment, the first power lead PW _ LE1 may also be in partial-surface contact with a recessed portion of the surface of the first power PAD PW _ PAD 1. In an area where the first power lead PW _ LE1 and the first power PAD PW _ PAD1 are in surface contact with each other, the first power lead PW _ LE1 and the first power PAD PW _ PAD1 may be surface-bonded to each other.

The size of the area where the first power PAD PW _ PAD1 may be surface-bonded to the first power lead PW _ LE1 may be proportional to the size of the area where the first power PAD PW _ PAD1 and the first power lead PW _ LE1 overlap each other in the thickness direction.

Specifically, the overlapping area of the first power PAD PW _ PAD1 and the first power lead PW _ LE1 in the thickness direction may be the sum of the overlapping area of the first power lead PW _ LE1 and the main PAD portions MR1 and MR2 and the PAD connection portion CR of the first power PAD PW _ PAD1 and the overlapping area of the first power lead PW _ LE1 and the protruding PAD portions PR1 and PR2 of the first power PAD PW _ PAD1, that is, WPA1 × WPA2+2 × WP111 × WP 12. That is, when the first power lead PW _ LE1 and the first power PAD PW _ PAD1 are properly aligned, the size of the area where the first power lead PW _ LE1 and the first power PAD PW _ PAD1 may be surface-bonded together may be WPA1 × WPA2+2 × WP111 × WP 12.

Fig. 9 is a plan view illustrating a case where the pad region of fig. 3 and the PCB of fig. 4 are attached to each other but are misaligned with each other (i.e., α <0), fig. 10 is an enlarged plan view illustrating a region B of fig. 9, fig. 11 is a sectional view taken along a line XI-XI 'of fig. 10, and fig. 12 is a sectional view taken along a line XII-XII' of fig. 10.

Referring to fig. 9 to 12, when the first power lead PW _ LE1 is aligned with the first power PAD PW _ PAD1, an overlapping area in the thickness direction of the first power lead PW _ LE1 and the first power PAD PW _ PAD1 may be uniformly maintained under the condition that a first edge of the first power lead PW _ LE1 in the first direction DR1 is disposed in an area overlapping with the first protruding PAD portion PR1 of the first power PAD PW _ PAD1 and a second edge of the first power lead PW _ LE1 in the first direction DR1 is disposed in an area overlapping with the second protruding PAD portion PR2 of the first power PAD PW _ PAD 1.

In particular, when the lead centre line LCL of the first power lead PW _ LE1 is misaligned with the alignment line AGL in the first direction DR1 towards the first side of the alignment line AGL, but only to such an extent that the first edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the first protruding PAD portion PR1 of the first power PAD PW _ PAD1 and the second edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the second protruding PAD portion PR2, the overlapping region of the first power lead PW _ LE1 with the first main PAD portion MR 38, the second main PAD MR2 and the PAD connection portion PR 15 in the PAD thickness direction of the first power PAD PW _ LE1 is maintained, compared to when the first power lead PW _ LE1 and the first power PAD PW _ LE1 are properly aligned, the overlapping region of the first power lead PW _ LE 3626 with the first main PAD portion PW _ PAD portion PR 24, the second main PAD MR2 and the PAD connection portion CR 25 of the first power lead PW _ LE 6326 in the first direction PW _ PR1 thickness direction And the overlapping area of the first power lead PW _ LE1 with the second protruding PAD portion PR2 of the first power PAD PW _ PAD1 in the thickness direction decreases. In an exemplary embodiment, for example, when the lead center line LCL of the first power lead out wire PW _ LE1 is misaligned by being moved by up to-D away from the alignment line AGL, an overlapping area in the thickness direction of the first protruding pad portion PR1 and the first power lead out wire PW _ LE1 may be (WP111+ D) × WP12, and an overlapping area in the thickness direction of the second protruding pad portion PR2 and the first power lead out wire PW _ LE1 may be (WP211-D) × WP 22. As has been discussed above, the width in the second direction DR2 (i.e., WP12) of the first protruding pad part PR1 and the width in the second direction DR2 (i.e., WP22) of the second protruding pad part PR2 are the same, and when the WPs 111 and 211 are the same, the sum of the overlapping area in the thickness direction of the first power lead wire PW _ LE1 and the first protruding pad part PR1 and the overlapping area in the thickness direction of the first power lead wire PW _ LE1 and the second protruding pad part PR2 may be 2 × WP111 × WP 12.

That is, even when the lead center line LCL of the first power lead PW _ LE1 is misaligned with the alignment line AGL, when the first edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the first protruding PAD portion PR1 of the first power PAD PW _ PAD1 and the second edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the second protruding PAD portion PR2, the size of the region where the first power lead PW _ LE1 and the first power PAD PW _ PAD1 may be surface-bonded together may be maintained as WPA1 × WPA2+2 × WP111 × WP 3535 12, which is the same as when the first power lead PW _ LE1 and the first power PAD PW _ PAD PW 1 are properly aligned.

Fig. 13 is a plan view illustrating a case where the pad region of fig. 3 and the PCB of fig. 4 are attached to each other but are misaligned with each other (i.e., α >0), fig. 14 is an enlarged plan view illustrating a region C of fig. 13, and fig. 15 is a sectional view taken along a line XV-XV' of fig. 14.

Referring to fig. 13 to 15, even when the first power lead PW _ LE1 is misaligned with the first power PAD PW _ PAD1 in the direction opposite to the direction in the example of fig. 9 to 12, the overlapping area of the first power lead PW _ LE1 and the first power PAD PW _ PAD1 may be consistently maintained under the condition that the first edge of the first power lead PW _ LE1 in the first direction DR1 falls into an area overlapping with the first protruding PAD portion PR1 of the first power PAD PW _ PAD1 and the second edge of the first power lead PW _ LE1 in the first direction DR1 falls into an area overlapping with the second protruding PAD portion PR 2.

In particular, when the lead centre line LCL of the first power lead PW _ LE1 is misaligned with the alignment line AGL in the first direction DR1 towards the second side of the alignment line AGL, but only to such an extent that the first edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the first protruding PAD portion PR1 of the first power PAD PW _ PAD1 and the second edge of the first power lead PW _ LE1 in the first direction DR1 falls in a region overlapping the second protruding PAD portion PR2, the overlapping region of the first power lead PW _ LE1 with the first main PAD portion MR 38, the second main PAD MR2 and the PAD connection portion PR 59625 in the PAD thickness direction of the first power PAD PW _ LE1 is maintained, compared to when the first power lead PW _ LE1 and the first power PAD PW _ LE1 are properly aligned, the overlapping region of the first power lead PW _ LE 3626 with the first main PAD portion PW _ PAD portion PR 24, the second main PAD portion MR2 and the PAD connection portion CR 1 of the first power lead PW _ LE 6326 in the first direction PW _ PAD PR1 thickness direction And the overlapping area of the first power lead PW _ LE1 with the second protruding PAD portion PR2 of the first power PAD PW _ PAD1 in the thickness direction increases. In an exemplary embodiment, for example, when the lead center line LCL of the first power lead out wire PW _ LE1 is misaligned by being moved up to + D away from the alignment line AGL, an overlapping area in the thickness direction of the first protruding pad portion PR1 and the first power lead out wire PW _ LE1 may be (WP111-D) × WP12, and an overlapping area in the thickness direction of the second protruding pad portion PR2 and the first power lead out wire PW _ LE1 may be (WP211+ D) × WP 22. As has been discussed above, when the width in the second direction DR2 (i.e., WP12) of the first protruding PAD portion PR1 and the width in the second direction DR2 (i.e., WP22) of the second protruding PAD portion PR2 are the same, and when the WPs 111 and WP211 are the same, the overlapping area in the thickness direction of the first power lead PW _ LE1 and the first protruding PAD portion PR1 and the overlapping area in the thickness direction of the first power lead PW _ LE1 and the second protruding PAD portion PR2 may be 2 × WP111 × WP12, which is the same as when the first power lead PW _ LE1 and the first power PAD PW _ PAD1 are properly aligned and when the first side of the first power lead PW _ LE1 on the first direction DR1 and the first power PAD PW _ PAD1 are misaligned toward the alignment line AGL.

If the degree of misalignment of the lead lines LE and the wiring PADs PAD changes in the ultrasonic bonding process for bonding the wiring PADs PAD and the lead lines LE during the manufacture of the display device 1, the bonding area between the lead lines LE and the wiring PADs PAD may undesirably change, and thus, bonding defects and resistance irregularities (resistance irregularities) may occur. However, since each of the wiring PADs PAD protrudes in two different directions and includes protruding PAD portions PR1 and PR2 having the same area and the same shape, even when misalignment occurs, the overlapping area of the lead-out line LE and the wiring PAD in the thickness direction can be uniformly maintained. That is, the size of the area in which the lead lines LE and the wiring PADs PAD can be surface-bonded together can be uniformly maintained. Therefore, it is possible to prevent or at least reduce bonding defects and resistance irregularities that may occur between the wiring PAD and the lead-out line LE.

Hereinafter, a display device according to other exemplary embodiments of the present disclosure will be described. Like reference numerals refer to like elements throughout the specification, and the description thereof will be omitted or at least simplified.

Fig. 16A to 16C are enlarged plan views illustrating a pad region of a display device according to an embodiment of the present disclosure.

The pad region of fig. 16A to 16C is different from its counterpart of fig. 1 in that protruding pad portions are respectively provided in a semicircular shape, a triangular shape, or a trapezoidal shape.

Specifically, referring to fig. 16A, the protruding pad portions PR1_1 and PR2_1 may have a semicircular shape in a plan view. The first protruding pad portion PR1_1 and the second protruding pad portion PR2_1 may have the same area in a plan view and may have the identical profile in a plan view.

Referring to fig. 16B, the protruding pad parts PR1_2 and PR2_2 may have a triangular shape in a plan view. The first protruding pad portion PR1_2 and the second protruding pad portion PR2_2 may have the same area in a plan view and may have the identical profile in a plan view.

Referring to fig. 16C, the protruding pad portions PR1_3 and PR2_3 may have a trapezoidal shape in a plan view. The first protruding pad portion PR1_3 and the second protruding pad portion PR2_3 may have the same area in a plan view and may have the identical profile in a plan view.

In the exemplary embodiment of fig. 16A to 16C, each of the first power PAD PW _ PAD1_1, the first power PAD PW _ PAD1_2, and the first power PAD PW _ PAD1_3 has protruding PAD portions protruding in different directions and having the same area and the same shape. Therefore, even when misalignment occurs, the overlapping area in the thickness direction of the lead-out line and the panel pad can be uniformly maintained. That is, the size of the area in which the lead-out lines and the panel pads can be surface-bonded together can be uniformly maintained. Therefore, it is possible to prevent or at least alleviate bonding defects and resistance irregularities that may occur between the lead-out wires and the panel pads.

Fig. 17 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure. Unlike the first power PAD PW _ PAD1 of fig. 3, the first power PAD PW _ PAD1_4 of fig. 17 has a plurality of first protruding PAD portions PR1 and a plurality of second protruding PAD portions PR 2.

Specifically, referring to fig. 17, each of the first power PADs PW _ PAD1_4 may include a plurality of first protruding PAD portions PR1 and a plurality of second protruding PAD portions PR 2. The number of the first protruding pad portions PR1 may be the same as the number of the second protruding pad portions PR 2. The second protruding pad part PR2 may be disposed between the first protruding pad parts PR1 along the second direction DR 2.

In the exemplary embodiment of fig. 17, each of the first power PADs PW _ PAD1_4 has a plurality of protruding PAD portions protruding in different directions and having the same area and the same shape. Therefore, even when misalignment occurs, the overlapping area in the thickness direction of the lead-out line and the panel pad can be uniformly maintained. That is, the size of the area in which the lead-out lines and the panel pads can be surface-bonded together can be uniformly maintained. Therefore, it is possible to prevent or at least alleviate bonding defects and resistance irregularities that may occur between the lead-out wires and the panel pads.

Fig. 18 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure.

The first power PAD PW _ PAD1_5 of fig. 18 is different from the first power PAD PW _ PAD1_4 of fig. 17 in that in each first power PAD PW _ PAD1_5, a first protruding PAD portion PR1 is disposed between another first protruding PAD portion PR1 and a second protruding PAD portion PR 2.

Fig. 19 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure.

The first power PAD PW _ PAD1_6 of fig. 19 is different from the first power PAD PW _ PAD1_5 of fig. 18 in that, in each first power PAD PW _ PAD1_6, the first protruding PAD portion PR1_4 has an area different from that of the second protruding PAD portion PR2, and the first main PAD portion MR1_1 has an area different from that of the second main PAD portion MR 2.

Specifically, referring to fig. 19, the number of second protruding PAD portions PR2 provided in each first power PAD PW _ PAD1_6 is greater than the number of first protruding PAD portions PR1_4 provided in each first power PAD PW _ PAD1_6, but the sum of the areas of the second protruding PAD portions PR2 may be the same as the area of the first protruding PAD portions PR1_ 4. That is, the width of the first protruding pad part PR1_4 in the first direction DR1 may be the same as the width of the second protruding pad part PR2 in the first direction DR1, and the width of the first protruding pad part PR1_4 in the second direction DR2 may be the same as the sum of the widths of the second protruding pad parts PR 2.

In the exemplary embodiment of fig. 19, even when misalignment occurs in aligning the lead-out wires with the panel PADs, the sum of the areas in which the first and second protruding PAD portions PR1_4 and PR2 of each first power PAD PW _ PAD1_6 can be surface-bonded can be uniformly maintained. Therefore, it is possible to prevent or at least alleviate bonding defects and resistance irregularities that may occur between the lead-out wires and the panel pads.

Fig. 20 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure.

The first power PAD PW _ PAD1_7 of fig. 20 is different from the first power PAD PW _ PAD1 of fig. 3 in that the first power PAD PW _ PAD1_7 of fig. 20 does not include a PAD connection portion.

Specifically, referring to fig. 20, the first and second main PAD portions MR1 and MR2 of each first power PAD PW _ PAD1_7 may be spaced apart from each other in the second direction DR 2. In the gap between the first and second main pad portions MR1 and MR2, the contact hole CNT may not be defined in the second insulating layer 112 b.

In the exemplary embodiment of fig. 20, even when misalignment occurs in aligning the lead-out wires with the panel PADs, the sum of areas in which the first and second protruding PAD portions PR1 and PR2 of each first power PAD PW _ PAD1_7 can be surface-bonded can be uniformly maintained. Therefore, it is possible to prevent or at least alleviate bonding defects and resistance irregularities that may occur between the lead-out wires and the panel pads.

Fig. 21 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure.

Referring to fig. 21, in each of the first power PADs PW _ PAD1_8, a PAD connection portion may not be provided between the first main PAD portion MR1 and the second main PAD portion MR2, and the first main PAD portion MR1 and the second main PAD portion MR2 may be directly physically connected.

In the exemplary embodiment of fig. 21, even when misalignment occurs in aligning the lead-out wires with the panel PADs, the sum of areas in which the first and second protruding PAD portions PR1 and PR2 of each first power PAD PW _ PAD1_7 can be surface-bonded can be uniformly maintained. Therefore, it is possible to prevent or at least alleviate bonding defects and resistance irregularities that may occur between the lead-out wires and the panel pads.

Fig. 22 is an enlarged plan view illustrating another exemplary embodiment of a pad region of a display device according to the present disclosure, and fig. 23 is a partial plan view illustrating another exemplary embodiment of a PCB of a display device according to the present disclosure.

In the display panel 100_1 and the PCB300 _1 of fig. 22 and 23, the wiring PAD _1 and the lead line LE _1 of fig. 22 and 23 are different from the wiring PAD and the lead line LE of fig. 3 and 4 in that the first and second power PADs PW _ PAD1_9 and PW _ PAD2_1, the panel dummy PAD DU _ PAD _1, the first and second power lead lines PW _ LE1_1 and PW _ LE2_1, and the dummy lead line DU _ LE _1 are integrated along the first direction DR 1.

In an exemplary embodiment, referring to fig. 22, for example, the main PAD portion and the PAD connection portion of the first power PAD PW _ PAD1_9 are disposed as a whole along the first direction DR 1. Similar to the protruding PAD portion of each of the first power PADs PW _ PAD1 of fig. 3, the protruding PAD portions of the first power PAD PW _ PAD1_9 may protrude from one side and the other side of the main PAD portion of the first power PAD PW _ PAD1_9 in the first direction DR1, and may have the same area and the identical outline in a plan view.

In the exemplary embodiment of fig. 22 and 23, the integrated first and second electric PADs PW _ PAD1_9 and PW _ PAD2_1 overlap the integrated first and second electric power leads PW _ LE1_1 and PW _ LE2_1, respectively, in the thickness direction and are surface-bonded to the integrated first and second electric power leads PW _ LE1_1 and PW _ LE2_1, respectively, and the integrated panel dummy PAD DU _ PAD _1 overlaps the integrated dummy lead DU _ LE _1, and is surface-bonded to the integrated dummy lead DU _ LE _1, in the thickness direction. Therefore, the size of the area where the wiring PAD _1 and the lead-out line LE _1 can be surface-bonded together can be increased, and therefore, a bonding defect can be prevented in advance.

Fig. 24 is a plan view of another exemplary embodiment of a display device according to the present disclosure, and fig. 25 is a sectional view of another exemplary embodiment of a display device according to the present disclosure.

Referring to fig. 24 and 25, the display panel 100_1 of the display device 2 may further include a bending area BA.

The display substrate 101 (refer to fig. 2) of the display panel 100_1 may include an insulating material such as a polymer resin. In exemplary embodiments, for example, the polymeric material may include polyethersulfone ("PES"), polyacrylate ("PA"), polyarylate ("PAR"), polyetherimide ("PEI"), polyethylene naphthalate ("PEN"), polyethylene terephthalate ("PET"), polyphenylene sulfide ("PPS"), polyallylate (polyallylate), polyimide ("PI"), polycarbonate ("PC"), cellulose triacetate ("CAT"), cellulose acetate propionate ("CAP"), or combinations thereof. The display substrate 101 may be a bendable, foldable or rollable flexible substrate. The flexible substrate may include, for example, PI, but the present disclosure is not limited thereto.

The bending area BA may be disposed between the array of the plurality of pixels and the first panel pad area P _ PA _ 1. The bending area BA may be disposed in the non-display area NA. The display panel 100_1 may be folded in one direction along a bending line as a reference line disposed in the bending area BA. The folding line may be a straight line parallel to the lower (or upper) side of the display panel 100_ 1. As shown in fig. 25, the bending area BA of the display panel 100_1 may be bent downward in the third direction DR 3.

However, the present disclosure is not limited thereto. That is, the display area DA and the first panel pad area P _ PA _1 may be connected to each other without the bending area BA. In other words, the display panel 100_1 may not have the curved area BA and may be flat over the entire display area DA and the entire non-display area NA.

In the first panel PAD area P _ PA _1, a plurality of wiring PADs PAD are provided. The driver IC 900 is disposed on the wiring PAD. In the second panel pad region P _ PA _2, a plurality of panel pads may be disposed, and the main circuit board 500_1 may be attached to the panel pads.

In an exemplary embodiment, the driver IC 900 may be implemented in the form of a chip on plastic ("COP") or a chip on glass ("COG"), for example.

The driver IC 900 may include a plurality of bumps connected to the wiring PADs PAD. In an exemplary embodiment, for example, the bump may include at least one of Au, Ni, and tin (Sn).

The bump of the driver IC 900 may be directly in contact with and bonded to the wiring PAD without other layers or elements. The bumps of the driver IC 900 and the wiring PADs PAD may be bonded together by ultrasonic bonding.