阅读说明：本技术 金属氧化物半导体晶体管及其制造方法 (Metal oxide semiconductor transistor and manufacturing method thereof ) 是由 许祥华 黄良安 钟昇镇 郭镇铵 李秋德 王智充 陈广修 林克峰 李彦辉 胡凯婷 于 2019-02-20 设计创作，主要内容包括：本发明公开一种金属氧化物半导体晶体管,其包括基板。基板具有延伸于第一方向的多个沟槽在该基板的顶部。栅极结构线是在该基板上延伸于与该第一方向交叉的第二方向,且跨过该多个沟槽。第一掺杂线是在该基板中位于该栅极结构线的第一侧,跨过该多个沟槽。第二掺杂线是在该基板中位于该栅极结构线的第二侧,跨过该多个沟槽。(The invention discloses a metal oxide semiconductor transistor, which comprises a substrate. The substrate has a plurality of trenches extending in a first direction on a top portion of the substrate. A gate structure line extends in a second direction crossing the first direction on the substrate and crosses the trenches. The first doped line is positioned on the first side of the grid structure line in the substrate and crosses the plurality of grooves. A second doped line is located on a second side of the gate structure line in the substrate and crosses over the plurality of trenches.)

1. A metal oxide semiconductor transistor, comprising:

the substrate is provided with a plurality of grooves extending in a first direction and is positioned at the top of the substrate;

a gate structure line extending in a second direction crossing the first direction on the substrate and crossing the plurality of trenches;

a first doped line on a first side of the gate structure line in the substrate crossing the plurality of trenches; and

and a second doped line crossing the plurality of trenches on a second side of the gate structure line in the substrate.

2. The MOS transistor of claim 1, wherein the first direction is perpendicular to the second direction.

3. The MOS transistor of claim 1, wherein the depth of the plurality of trenches is in the range of 100-700 angstroms.

4. The MOS transistor of claim 1, wherein the depth of the plurality of trenches is in the range of 300-400 angstroms.

5. The MOS transistor of claim 1, wherein the width of the trenches is equal to the distance between two adjacent trenches.

6. The MOS transistor of claim 1, wherein the width of the trenches is 250nm or more.

7. The MOS transistor of claim 1, wherein the substrate comprises a deep P-well, and wherein the first doped line and the second doped line are formed in the deep P-well.

8. The MOS transistor of claim 1, wherein the first doped line is P-type and the second doped line is N-type.

9. The MOS transistor of claim 1, wherein the gate structure line comprises:

a gate insulating layer on the substrate; and

and a gate line layer on the gate insulating layer.

10. The MOS transistor of claim 9, wherein the gate line layer is a polysilicon layer.

11. A method of fabricating a metal oxide semiconductor transistor, comprising:

providing a substrate, wherein the substrate is provided with a plurality of grooves extending in a first direction and is positioned at the top of the substrate;

forming a gate structure line on the substrate, extending in a second direction crossing the first direction, and crossing the trenches;

implanting the substrate to form a first doped line and a second doped line in the substrate, extending in a second direction crossing the first direction and crossing the plurality of trenches; and

forming a gate structure line extending in the second direction on the substrate and crossing the plurality of trenches, wherein the first doped line is on a first side of the gate structure line and the second doped line is on a second side of the gate structure line.

12. The method of claim 11, wherein the first direction is perpendicular to the second direction.

13. The method of claim 11, wherein the plurality of trenches have a depth in a range of 100 a to 700 a.

14. The method of claim 11, wherein the depth of the plurality of trenches is in a range of 300 a to 400 a.

15. The method of claim 11, wherein a width of the plurality of trenches is equal to a distance between two adjacent trenches.

16. The method of claim 11, wherein a width of the trenches is 250nm or more.

17. The method of claim 11, wherein the step of implanting the substrate further comprises forming a deep P-well in the substrate, the first doped line and the second doped line being formed in the deep P-well.

18. The method of claim 11, wherein the first doped line is P-type and the second doped line is N-type.

19. The method of claim 11, wherein the step of forming the gate structure line comprises:

forming a gate insulating layer on the substrate, crossing the multi-partition trench; and

a gate line layer is formed on the gate insulating layer.

20. The method of claim 19, wherein the gate line layer is a polysilicon layer.

Technical Field

The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal-oxide-semiconductor (MOS) transistor and a method for manufacturing the same.

Background

As the functionality of integrated circuits has increased, a portion of the circuitry included therein may operate at a relatively high voltage range, thereby increasing the overall functionality of the integrated circuit. Although the mos transistor operated at high voltage is also composed of a gate, a source and a drain, the structure is different, so that, for example, under high voltage operation, the current passing through the channel region after the transistor is turned on can be increased.

The gate of the mos transistor is used to control the on-state of the channel region in the substrate. When the mos transistor is applied to high voltage, for example, the area of the channel region formed by the polysilicon gate and the substrate affects the performance of the mos transistor.

Taking the structure of a high voltage transistor as an example, the gate between the source and the drain is a linear structure to increase the effective gate width. The gate electrode forms a channel region on the substrate, and allows a current to flow through the channel region. The gate effective width is actually the corresponding channel effective width. As generally defined herein, the source and drain are lengthwise, which results in a channel length, and the gate effective width refers to the extension length in a direction perpendicular to the direction of the channel length. When the effective gate width (Weff) is large, the current (Ion) of the transistor at the time of turning on is also increased.

For the structural design of mos transistors, especially for transistors operating at high voltage, consideration needs to be given to increasing the effective width of the gate so as to enhance the operating performance of the transistor.

Disclosure of Invention

The present invention is directed to a metal oxide semiconductor transistor, in which a gate structure of the transistor has a structure recessed into a substrate in a width direction, so as to increase an effective width of the gate.

To achieve the above objective, the present invention provides a metal oxide semiconductor transistor, which includes a substrate. The substrate is provided with a plurality of grooves extending in a first direction and located on the top of the substrate. A gate structure line extends in a second direction crossing the first direction on the substrate and crosses the trenches. The first doped line is positioned on the first side of the grid structure line in the substrate and crosses the plurality of grooves. A second doped line is located on a second side of the gate structure line in the substrate and crosses over the plurality of trenches.

In one embodiment, the first direction is perpendicular to the second direction for the mos transistor.

In one embodiment, the plurality of trenches have a depth in a range of 100 to 700 angstroms for the mos transistor.

In one embodiment, the plurality of trenches have a depth in a range of 300 to 400 angstroms for the mos transistor.

In one embodiment, for the mos transistor, the width of the plurality of trenches is equal to the distance between two adjacent trenches.

In one embodiment, the width of the trenches is 250nm or more for the mos transistor.

In one embodiment, for the mos transistor, the substrate includes a deep P-well, wherein the first doped line and the second doped line are formed in the deep P-well.

In one embodiment, for the mos transistor, the first doped line is P-type and the second doped line is N-type.

In one embodiment, for the MOS transistor, the gate structure line comprises a gate insulating layer on the substrate; and a gate line layer on the gate insulating layer.

In one embodiment, for the mos transistor, the gate line layer is a polysilicon layer.

The invention also provides a method for manufacturing a metal oxide semiconductor transistor, which is characterized by providing a substrate, wherein the substrate is provided with a plurality of grooves extending in a first direction and is positioned on the top of the substrate. A gate structure line is formed on the substrate, extends in a second direction crossing the first direction, and crosses the plurality of trenches. The substrate is implanted to form a first doped line and a second doped line in the substrate, extending in a second direction crossing the first direction and crossing the plurality of trenches. Forming a gate structure line on the substrate, extending in the second direction and crossing the trenches, wherein the first doped line is on a first side of the gate structure line and the second doped line is on a second side of the gate structure line.

In an embodiment, for the method of fabricating a mos transistor, the first direction is perpendicular to the second direction.

In one embodiment, for the method of fabricating a metal oxide semiconductor transistor, the plurality of trenches have a depth in a range of 100 to 700 angstroms.

In one embodiment, for the method of fabricating a metal oxide semiconductor transistor, the plurality of trenches have a depth in a range of 300 to 400 angstroms.

In an embodiment, with the method for manufacturing a metal oxide semiconductor transistor, the width of the plurality of trenches is equal to the distance between two adjacent trenches.

In one embodiment, the width of the trenches is 250nm or more for the method of fabricating a mos transistor.

In an embodiment, with respect to the method for manufacturing a mos transistor, the step of implanting into the substrate further includes forming a deep P-well region in the substrate, the first doped line and the second doped line being formed in the deep P-well region.

In one embodiment, for the method of fabricating a mos transistor, the first doped line is P-type and the second doped line is N-type.

In one embodiment, for the method of fabricating a mos transistor described above, the step of forming the gate structure line includes forming a gate insulating layer on the substrate, crossing the multi-spaced trenches and forming a gate line layer on the gate insulating layer.

In one embodiment, for the method of fabricating a metal oxide semiconductor transistor, the gate line layer is a polysilicon layer.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a three-dimensional structure of a metal oxide semiconductor transistor according to an embodiment of the present invention;

FIG. 2 is a schematic top view of a MOS transistor according to an embodiment of the present invention;

FIG. 3 is a cross-sectional view of a metal oxide semiconductor transistor at line I-I of FIG. 1 according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a MOS transistor at line II-II of FIG. 1 according to an embodiment of the present invention;

fig. 5A to 5O are schematic cross-sectional views illustrating a method for fabricating a mos transistor according to an embodiment of the invention.

Description of the reference numerals

50 transistor

52 isolation structure

54 contact area

56: groove

60 first direction

62 the second direction

100 substrate

102 gate structure line

102a gate line layer

102b gate insulating layer

200 base plate

202 isolation structure

204 pad oxide layer

206 nitride layer

208 photoresist layer

210. 212, 214 opening

216 groove

218 pad oxide layer

220 gate insulation layer

222 gate layer

224 gate line structure

Detailed Description

The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a structure of a metal oxide semiconductor transistor and a method for manufacturing the same. Under the consideration of increasing the effective width of the grid electrode, the invention provides the extension of the grid electrode structure of the transistor in the width direction, and the structure with a concave part to the substrate is provided so as to improve the effective width of the grid electrode.

The invention is illustrated below by means of some examples, but is not limited to the examples. Additionally, the illustrated embodiments also allow suitable integration with each other into another embodiment.

The present invention looks at (look into) the way to increase the effective width of the gate. For the generally straight way, the gate electrode may be linearly extended along the channel width direction perpendicular to the channel length direction on the flat substrate surface to increase the gate effective width. However, the present invention proposes a structure that can further increase the effective width of the gate, in addition to modifying the gate into a linear gate structure.

FIG. 1 is a schematic three-dimensional structure of a metal oxide semiconductor transistor according to an embodiment of the present invention. Referring to fig. 1, a substrate 100 is used as a base of the structure, and the substrate 100 is, for example, a P-type substrate Psub. There are P-type or N-type doped well regions in the substrate 100, including, for example, deep N-well DNW and deep P-well DPW. In accordance with actual requirements, an N-type i/o well NWIO and a P-type i/o well PWIO are also formed in the substrate 100, which can serve as a source S and a drain D of one of the transistors 50. The substrate 100 has a Shallow Trench Isolation (STI) structure for isolation, and a P-type or N-type heavily doped contact region 54 for external contact connection, which is denoted by N + or P +. The doping regions in the substrate 100 are determined according to actual needs, and the present invention is not limited to the illustrated doping method.

A plurality of trenches 56 are also formed in the top of the substrate 100. The grooves 56 extend along a first direction 60. The transistor 50 further includes a gate structure line 102 on the substrate 100. Gate structure lines 102 extend in the second direction 62 and across the trenches 56. The first direction 60 and the second direction 62 intersect, for example, in a mutually perpendicular intersecting manner. The gate structure line 102 includes a gate line layer 102a and a gate insulating layer 102 b. A gate insulating layer 102b is on the substrate 100, also across the trenches 56. A gate line layer 102a is on the gate insulating layer 102b, also across the trenches 56. Thus, the source S and the drain D are formed in the substrate 100 at two sides of the gate structure line 102. Here, the source S and the drain D are just an example for convenience of description, and in fact, the source S and the drain D may be interchanged according to the operation. The source S and drain D structures, in one embodiment, are both linear doped regions. The gate electrode between the source S and the drain D facilitates formation of a channel region in the surface layer of the substrate 100, the channel direction of which is defined as the first direction 60. The width of the gate structure line 102 extends in the second direction 62, which is perpendicular to the first direction 60, corresponding to the channel direction. The effective length of the gate structure line 102 is the effective width of the gate.

The present invention forms a plurality of trenches 56 on top of the substrate 100. The gate structure lines 102 cross the trenches 56 and are recessed with the trenches 56, thereby increasing the total length of the gate structure lines 102, i.e., increasing the gate width. Therefore, when the transistor is started to operate, the current flowing through the channel region can be increased so as to improve the efficiency of the transistor, and the transistor can be further applied to the design of a high-voltage transistor.

The structure of transistor 50 is described further below. Fig. 2 is a top view of a mos transistor according to an embodiment of the invention. Referring also to fig. 2, the mos transistor 50 may be configured with a gate structure line 102 having a width that increases in response to, for example, high voltage operation. The gate structure line 102 extends along the direction of the cutting line II-II. A source and a drain are formed in the substrate 100 on both sides of the gate structure line 102. In the present embodiment, for example, two transistors 50 are connected in series, but the present invention is not limited thereto. The transistor 50 is based on a substrate 100. A plurality of trenches 56 are formed on the top of the substrate 100 to extend in the direction of the cutting line I-I. Contact regions 54 are formed on both sides of the trench 56 for subsequent externally connected contact terminals. Taking transistor 50 as an example, the periphery thereof is isolated by isolation structures 52, such as Shallow Trench Isolation (STI) structures.

FIG. 3 is a cross-sectional view of the MOS transistor at the cutting line I-I in FIG. 1 according to an embodiment of the invention. Referring to fig. 3, the scribe line I-I cuts through the trench 56, so that the height of the substrate 100 between the isolation structures 52 is recessed in the cross-sectional structure, which is determined by the depth of the trench 56. The gate structure line 102 crosses the trench 56 and thus also at the bottom of the trench 56.

FIG. 4 is a cross-sectional view of a MOS transistor at cut line II-II of FIG. 1 according to an embodiment of the invention. Referring to fig. 4, the cutting line II-II cuts through the gate structure line 102. Since the substrate 100 has a plurality of trenches 56, the gate structure lines 102 form a recess structure on the trenches 56, which includes the contact area on the sidewall of the trenches 56, thereby increasing the contact area between the gate structure lines 102 and the substrate 100. This area of contact forms the channel region. Thus, the present invention increases the effective width of the gate structure line 102.

Generally, the greater the depth of the trench 56, the greater the increased effective width. However, it is also relatively difficult to manufacture for trenches of large depth. In one embodiment, the depth of trench 56 is in the range of 100 angstroms (angstrom) to 700 angstroms, for example. In one embodiment, the depth of the trench is in the range of 300 to 400 angstroms, for example. In one embodiment, the width W1 of the trench is, for example, equal to the distance W2 between two adjacent trenches, and W2 is, for example, 250nm (nanometer) or more. In one embodiment, the width of the trench is 250nm or more, for example.

The flow of manufacturing a transistor is described below. Fig. 5A to 5O are schematic cross-sectional views illustrating a method for fabricating a mos transistor according to an embodiment of the invention.

Referring to fig. 5A, an isolation structure 202 is formed on a substrate 200 to isolate a subsequently formed device, such as a transistor device. A pad oxide layer 204 is formed on the substrate 200. Referring to fig. 5B, a nitride layer 206 is formed on the pad oxide layer 204. Referring to fig. 5C, a photoresist layer 208 is formed on the nitride layer 206. Photoresist layer 208 has an opening 210 that exposes a portion of nitride layer 206. Referring to fig. 5D, the nitride layer 206 is etched using the photoresist layer 208 as an etch mask, corresponding to the opening 210, to form an opening 212 in the nitride layer 206, which exposes a portion of the pad oxide layer 204.

Referring to fig. 5E, the photoresist layer 208 is removed, leaving the nitride layer 206 and the pad oxide layer 204. Referring to fig. 5F, an oxide clean step, such as a standard wet (RCA) clean step, is then used to remove the pad oxide layer 204 exposed by the openings 212 of the nitride layer 206. Thus, an opening 214 is formed entirely in the nitride layer 206 and the pad oxide layer 204, exposing a portion of the substrate 200.

Referring to fig. 5G, an etch process etches the exposed portions of the substrate 200 by forming openings 214 in the nitride layer 206 and the pad oxide layer 204 to obtain a plurality of trenches 216 at the top of the substrate 200. As previously described in fig. 4, the depth D of trench 216 is, for example, in the range of 100 angstroms to 700 angstroms. The width W1 of the trench 216 is 250nm or more, for example. The distance W2 between adjacent two of the trenches is, for example, 250nm or more. In one embodiment, the width W1 and the distance W2 are, for example, equally and uniformly distributed.

Referring to fig. 5H, after completing the structure of trench 216, since nitride layer 206 and pad oxide layer 204 are different materials, in one embodiment, nitride layer 206 may be removed first, while pad oxide layer 204 remains on substrate 200. Referring to fig. 5I, in one embodiment, the pad oxide layer 204 is removed by a cleaning step to expose the substrate 200.

Referring to fig. 5J, another pad oxide layer 218 is formed on the substrate 200 as a protection layer for the subsequent implantation process. Referring to fig. 5K, the implantation process forms the desired doped regions in the substrate 200, including, for example, deep N-well DNW, deep P-well DPW, P-input/output well PWIO, and the like, as described with reference to the structure of fig. 1. The implantation process is only schematically illustrated as various doping regions required for the substrate 200 to be formed, and the actual implantation process may be performed at other appropriate stages in the manufacturing process, and the present invention is not limited to the implantation process. Referring to fig. 5L, after the implantation process is completed, the pad oxide layer 218 is removed to expose the substrate 200.

Referring to fig. 5M, a gate insulation layer 220 is again formed on the substrate 200, covering the trench 216. Referring to fig. 5N, a gate layer 222 is also formed on the gate insulating layer 220. The gate layer 222 is made of polysilicon, for example. In one embodiment, the gate layer 222 may be doped according to a desired conductivity type. Referring to fig. 5O, in one implementation, the gate layer 222 is defined to obtain the desired gate line structure 224. After which it can proceed to complete other desired structures. The present invention is not limited to the subsequent manufacturing process, and the subsequent manufacturing process will not be described further herein.

The gate line structure 224 of the present invention can at least increase the transistor operating current by increasing the effective width of the gate electrode by forming the trench 216 in the substrate 200.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.